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":1.37,"sim_time":18.681582,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.58,"sim_time":27.884607,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":8.72,"sim_time":1064.086019,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":8.72,"sim_time":1064.086019,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":8.72,"sim_time":1064.086019,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":8.72,"sim_time":1064.086019,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.58,"sim_time":27.884607,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":8.72,"sim_time":1064.086019,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.58,"sim_time":27.884607,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":2.37,"sim_time":139.708434,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":235,"total":235,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":77.06,"sim_time":11696.92042,"passed":43,"total":50,"percent":86.0}},"passed":43,"total":50,"percent":86.0}},"passed":43,"total":50,"percent":86.0}},"coverage":{"code":{"block":null,"line_statement":98.91,"branch":96.51,"condition_expression":94.2,"toggle":97.12,"fsm":91.94},"assertion":97.61,"functional":92.66},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"5.edn_stress_all_with_rand_reset.71983249158158669320976659117878790466944517103977903466259516864123940630334","seed":71983249158158669320976659117878790466944517103977903466259516864123940630334,"line":292,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1959517638 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1959517638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"12.edn_stress_all_with_rand_reset.12965614384676706845160115854864559733796475943309085311827970265698612332825","seed":12965614384676706845160115854864559733796475943309085311827970265698612332825,"line":212,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/12.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2314937886 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2314937886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"33.edn_stress_all_with_rand_reset.115103510567209341545558794323662433220438588570053575175646195880899269188479","seed":115103510567209341545558794323662433220438588570053575175646195880899269188479,"line":135,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/33.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1110538856 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1110538856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"35.edn_stress_all_with_rand_reset.102082299974728668312389335165892182498996854003071389229019198214879927118097","seed":102082299974728668312389335165892182498996854003071389229019198214879927118097,"line":188,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/35.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 467429403 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 467429403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"43.edn_stress_all_with_rand_reset.14312615239575738906798358003577150072716198851275757101647076406551179953597","seed":14312615239575738906798358003577150072716198851275757101647076406551179953597,"line":125,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 566890927 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 566890927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"46.edn_stress_all_with_rand_reset.1829580367345728489436579284664481344709589502877470222541048745316023838829","seed":1829580367345728489436579284664481344709589502877470222541048745316023838829,"line":119,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/46.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 112745471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 112745471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"49.edn_stress_all_with_rand_reset.50040590625940253627391651463208408132093021269892089550746300464243492743906","seed":50040590625940253627391651463208408132093021269892089550746300464243492743906,"line":125,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/49.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 133440763 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 133440763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"6.edn_disable_auto_req_mode.94396765128045700137592129237113357904003128317530033680115857228417013719369","seed":94396765128045700137592129237113357904003128317530033680115857228417013719369,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  47126476 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x004886a2 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  47126476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"22.edn_disable_auto_req_mode.69723242473364265531415990306192221604963925252831916503423733339009951147027","seed":69723242473364265531415990306192221604963925252831916503423733339009951147027,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/22.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  27479326 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00a39652 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  27479326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.19320098248719976827623906589381678415040317538634074621858357122149918451515","seed":19320098248719976827623906589381678415040317538634074621858357122149918451515,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  32080321 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00f01672 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  32080321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"8.edn_disable_auto_req_mode.20827448930033091099191691742335094144256155907870048558642293830685215728182","seed":20827448930033091099191691742335094144256155907870048558642293830685215728182,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/8.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"16.edn_disable_auto_req_mode.70867776010660685390852853771368817344235968453616526680155411807704750226349","seed":70867776010660685390852853771368817344235968453616526680155411807704750226349,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/16.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"24.edn_disable_auto_req_mode.27332694683605836618356838893844622470730677831683009544278490760443783719600","seed":27332694683605836618356838893844622470730677831683009544278490760443783719600,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/24.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"35.edn_disable_auto_req_mode.65365878780493299918008489139657497833916960790565424887145319565685713859791","seed":65365878780493299918008489139657497833916960790565424887145319565685713859791,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/35.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"38.edn_disable_auto_req_mode.57729104598268568127272778598100558562601785182813570159816942238621530848534","seed":57729104598268568127272778598100558562601785182813570159816942238621530848534,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/38.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1115,"total":1130,"percent":98.67256637168141}