{"block":{"name":"edn","variant":"edn1","commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-25T09:02:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/edn_edn1/data/edn_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"edn_smoke":{"max_time":1.58,"sim_time":129.317345,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"edn_csr_hw_reset":{"max_time":0.89,"sim_time":19.218802,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"edn_csr_rw":{"max_time":0.86,"sim_time":44.536636,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"edn_csr_bit_bash":{"max_time":4.16,"sim_time":500.55960600000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"edn_csr_aliasing":{"max_time":1.16,"sim_time":139.727331,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"edn_csr_mem_rw_with_rand_reset":{"max_time":1.45,"sim_time":30.522156,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"edn_csr_rw":{"max_time":0.86,"sim_time":44.536636,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.16,"sim_time":139.727331,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"firmware":{"tests":{"edn_genbits":{"max_time":87.37,"sim_time":9153.646963,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"csrng_commands":{"tests":{"edn_genbits":{"max_time":87.37,"sim_time":9153.646963,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"genbits":{"tests":{"edn_genbits":{"max_time":87.37,"sim_time":9153.646963,"passed":300,"total":300,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"interrupts":{"tests":{"edn_intr":{"max_time":1.41,"sim_time":26.097153,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alerts":{"tests":{"edn_alert":{"max_time":1.69,"sim_time":124.217821,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"errs":{"tests":{"edn_err":{"max_time":1.78,"sim_time":91.246887,"passed":100,"total":100,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"disable":{"tests":{"edn_disable":{"max_time":1.58,"sim_time":12.774259,"passed":50,"total":50,"percent":100.0},"edn_disable_auto_req_mode":{"max_time":2.94,"sim_time":500.0,"passed":46,"total":50,"percent":92.0}},"passed":96,"total":100,"percent":96.0},"stress_all":{"tests":{"edn_stress_all":{"max_time":4.2,"sim_time":281.098482,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"edn_intr_test":{"max_time":0.85,"sim_time":15.381103999999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"edn_alert_test":{"max_time":2.81,"sim_time":253.03340100000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"edn_tl_errors":{"max_time":2.79,"sim_time":469.318146,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"edn_tl_errors":{"max_time":2.79,"sim_time":469.318146,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.89,"sim_time":19.218802,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.86,"sim_time":44.536636,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.16,"sim_time":139.727331,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.06,"sim_time":56.753665999999996,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"edn_csr_hw_reset":{"max_time":0.89,"sim_time":19.218802,"passed":5,"total":5,"percent":100.0},"edn_csr_rw":{"max_time":0.86,"sim_time":44.536636,"passed":20,"total":20,"percent":100.0},"edn_csr_aliasing":{"max_time":1.16,"sim_time":139.727331,"passed":5,"total":5,"percent":100.0},"edn_same_csr_outstanding":{"max_time":1.06,"sim_time":56.753665999999996,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":966,"total":970,"percent":99.58762886597938},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0},"edn_tl_intg_err":{"max_time":3.04,"sim_time":1077.416813,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_config_regwen":{"tests":{"edn_regwen":{"max_time":1.59,"sim_time":83.568668,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_config_mubi":{"tests":{"edn_alert":{"max_time":1.69,"sim_time":124.217821,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_main_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ack_sm_fsm_sparse":{"tests":{"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_fifo_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ctr_redun":{"tests":{"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_main_sm_ctr_local_esc":{"tests":{"edn_alert":{"max_time":1.69,"sim_time":124.217821,"passed":200,"total":200,"percent":100.0},"edn_sec_cm":{"max_time":4.06,"sim_time":451.06390999999996,"passed":5,"total":5,"percent":100.0}},"passed":205,"total":205,"percent":100.0},"sec_cm_cs_rdata_bus_consistency":{"tests":{"edn_alert":{"max_time":1.69,"sim_time":124.217821,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"sec_cm_tile_link_bus_integrity":{"tests":{"edn_tl_intg_err":{"max_time":3.04,"sim_time":1077.416813,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":235,"total":235,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"edn_stress_all_with_rand_reset":{"max_time":102.6,"sim_time":39659.663693,"passed":42,"total":50,"percent":84.0}},"passed":42,"total":50,"percent":84.0}},"passed":42,"total":50,"percent":84.0}},"coverage":{"code":{"block":null,"line_statement":98.48,"branch":94.59,"condition_expression":95.0,"toggle":96.15,"fsm":97.73},"assertion":97.14,"functional":92.23},"cov_report_page":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"4.edn_stress_all_with_rand_reset.88645640507623265163619742583280841447414812217950371129458359226850540689008","seed":88645640507623265163619742583280841447414812217950371129458359226850540689008,"line":131,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1050261592 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1050261592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"19.edn_stress_all_with_rand_reset.109158645237969434564867750010709747074870779890164837964543075412867229789","seed":109158645237969434564867750010709747074870779890164837964543075412867229789,"line":275,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/19.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2346611266 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2346611266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"20.edn_stress_all_with_rand_reset.102348489423447492241348874434246739883878245962214757981639720608177258946371","seed":102348489423447492241348874434246739883878245962214757981639720608177258946371,"line":247,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/20.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2580705990 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2580705990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"25.edn_stress_all_with_rand_reset.94550239914888380688371207440652522106487592236737058481046780290950691143783","seed":94550239914888380688371207440652522106487592236737058481046780290950691143783,"line":170,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/25.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1685373375 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1685373375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.90846350350722172701332383740232974489826285972421115862782590641794652562103","seed":90846350350722172701332383740232974489826285972421115862782590641794652562103,"line":183,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1988741287 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1988741287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"28.edn_stress_all_with_rand_reset.48309436332995635924021093835780903631358448743961687073022058971757251838736","seed":48309436332995635924021093835780903631358448743961687073022058971757251838736,"line":255,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/28.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2782397303 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2782397303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"33.edn_stress_all_with_rand_reset.10283223631132552420441569804776250616211589973665860498905905690105028201572","seed":10283223631132552420441569804776250616211589973665860498905905690105028201572,"line":310,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/33.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4021599882 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4021599882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"37.edn_stress_all_with_rand_reset.59488659548173129356568230135394515752097434241428892081105225101587087277165","seed":59488659548173129356568230135394515752097434241428892081105225101587087277165,"line":315,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2012934235 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2012934235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"9.edn_disable_auto_req_mode.49688269254058933218237883949364704430988845945824442583025779838299430285244","seed":49688269254058933218237883949364704430988845945824442583025779838299430285244,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  56026247 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  56026247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"27.edn_disable_auto_req_mode.30862080219324254650561203876756153213528595355775232854180884519426625819246","seed":30862080219324254650561203876756153213528595355775232854180884519426625819246,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/27.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  13522720 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00001903 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  13522720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"45.edn_disable_auto_req_mode.42744164679334504667975270059918502334488853606939574623876413499141974287943","seed":42744164679334504667975270059918502334488853606939574623876413499141974287943,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"47.edn_disable_auto_req_mode.79440059141451660006747916004885301192793622353597465850004217832696859876712","seed":79440059141451660006747916004885301192793622353597465850004217832696859876712,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/47.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1118,"total":1130,"percent":98.93805309734513}