{"block":{"name":"lc_ctrl","variant":"volatile_unlock_disabled","commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-25T09:02:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/lc_ctrl_volatile_unlock_disabled/data/lc_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"lc_ctrl_smoke":{"max_time":5.04,"sim_time":133.22387799999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.3,"sim_time":68.27321400000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.36,"sim_time":54.418703,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"lc_ctrl_csr_bit_bash":{"max_time":2.27,"sim_time":181.77937599999998,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"lc_ctrl_csr_aliasing":{"max_time":1.8,"sim_time":145.202661,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"lc_ctrl_csr_mem_rw_with_rand_reset":{"max_time":2.1,"sim_time":23.831773000000002,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"lc_ctrl_csr_rw":{"max_time":1.36,"sim_time":54.418703,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.8,"sim_time":145.202661,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"state_post_trans":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.84,"sim_time":182.603377,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"regwen_during_op":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":19.92,"sim_time":1745.259626,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rand_wr_claim_transition_if":{"tests":{"lc_ctrl_claim_transition_if":{"max_time":1.33,"sim_time":19.981619,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_prog_failure":{"tests":{"lc_ctrl_prog_failure":{"max_time":4.65,"sim_time":151.056923,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_state_failure":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"lc_errors":{"tests":{"lc_ctrl_errors":{"max_time":16.65,"sim_time":587.4277589999999,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"security_escalation":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_prog_failure":{"max_time":4.65,"sim_time":151.056923,"passed":50,"total":50,"percent":100.0},"lc_ctrl_errors":{"max_time":16.65,"sim_time":587.4277589999999,"passed":48,"total":50,"percent":96.0},"lc_ctrl_security_escalation":{"max_time":13.8,"sim_time":2478.126128,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_failure":{"max_time":58.18,"sim_time":15952.469516000001,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":20.4,"sim_time":3080.279084,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":59.2,"sim_time":5752.467203,"passed":18,"total":20,"percent":90.0}},"passed":256,"total":260,"percent":98.46153846153847},"jtag_access":{"tests":{"lc_ctrl_jtag_csr_hw_reset":{"max_time":3.94,"sim_time":187.471827,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_rw":{"max_time":2.49,"sim_time":559.751765,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_bit_bash":{"max_time":23.41,"sim_time":1729.749129,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_aliasing":{"max_time":7.64,"sim_time":705.729834,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_same_csr_outstanding":{"max_time":1.8,"sim_time":31.448123,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_csr_mem_rw_with_rand_reset":{"max_time":3.28,"sim_time":1009.184047,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_alert_test":{"max_time":2.35,"sim_time":122.772655,"passed":10,"total":10,"percent":100.0},"lc_ctrl_jtag_smoke":{"max_time":13.24,"sim_time":680.546593,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":32.91,"sim_time":6630.755911,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_prog_failure":{"max_time":20.4,"sim_time":3080.279084,"passed":20,"total":20,"percent":100.0},"lc_ctrl_jtag_errors":{"max_time":59.2,"sim_time":5752.467203,"passed":18,"total":20,"percent":90.0},"lc_ctrl_jtag_access":{"max_time":18.23,"sim_time":885.86442,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_regwen_during_op":{"max_time":39.9,"sim_time":1162.132338,"passed":10,"total":10,"percent":100.0}},"passed":208,"total":210,"percent":99.04761904761905},"jtag_priority":{"tests":{"lc_ctrl_jtag_priority":{"max_time":13.39,"sim_time":1343.997774,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"lc_ctrl_volatile_unlock":{"tests":{"lc_ctrl_volatile_unlock_smoke":{"max_time":1.65,"sim_time":21.699041,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"lc_ctrl_stress_all":{"max_time":547.07,"sim_time":90601.68246099999,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"alert_test":{"tests":{"lc_ctrl_alert_test":{"max_time":1.7,"sim_time":74.79636900000001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":4.29,"sim_time":153.431652,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"lc_ctrl_tl_errors":{"max_time":4.29,"sim_time":153.431652,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.3,"sim_time":68.27321400000001,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.36,"sim_time":54.418703,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.8,"sim_time":145.202661,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":2.18,"sim_time":40.795269,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"lc_ctrl_csr_hw_reset":{"max_time":1.3,"sim_time":68.27321400000001,"passed":5,"total":5,"percent":100.0},"lc_ctrl_csr_rw":{"max_time":1.36,"sim_time":54.418703,"passed":20,"total":20,"percent":100.0},"lc_ctrl_csr_aliasing":{"max_time":1.8,"sim_time":145.202661,"passed":5,"total":5,"percent":100.0},"lc_ctrl_same_csr_outstanding":{"max_time":2.18,"sim_time":40.795269,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":724,"total":730,"percent":99.17808219178082},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":4.16,"sim_time":851.718253,"passed":20,"total":20,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"lc_ctrl_tl_intg_err":{"max_time":4.16,"sim_time":851.718253,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_transition_config_regwen":{"tests":{"lc_ctrl_regwen_during_op":{"max_time":19.92,"sim_time":1745.259626,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_manuf_state_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_manuf_state_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_transition_ctr_bkgn_chk":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_state_config_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_kmac_fsm_sparse":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_local_esc":{"tests":{"lc_ctrl_state_failure":{"max_time":14.47,"sim_time":584.66247,"passed":50,"total":50,"percent":100.0},"lc_ctrl_sec_cm":{"max_time":9.59,"sim_time":907.8843889999999,"passed":5,"total":5,"percent":100.0}},"passed":55,"total":55,"percent":100.0},"sec_cm_main_fsm_global_esc":{"tests":{"lc_ctrl_security_escalation":{"max_time":13.8,"sim_time":2478.126128,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_main_ctrl_flow_consistency":{"tests":{"lc_ctrl_state_post_trans":{"max_time":9.84,"sim_time":182.603377,"passed":50,"total":50,"percent":100.0},"lc_ctrl_jtag_state_post_trans":{"max_time":32.91,"sim_time":6630.755911,"passed":20,"total":20,"percent":100.0}},"passed":70,"total":70,"percent":100.0},"sec_cm_intersig_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":23.23,"sim_time":957.495361,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_ctrl_mubi":{"tests":{"lc_ctrl_sec_mubi":{"max_time":23.23,"sim_time":957.495361,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_digest":{"tests":{"lc_ctrl_sec_token_digest":{"max_time":21.36,"sim_time":821.062911,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_mux_ctrl_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":12.61,"sim_time":648.8369009999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_token_valid_mux_redun":{"tests":{"lc_ctrl_sec_token_mux":{"max_time":12.61,"sim_time":648.8369009999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":355,"total":355,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"lc_ctrl_stress_all_with_rand_reset":{"max_time":117.86,"sim_time":5910.5681030000005,"passed":23,"total":50,"percent":46.0}},"passed":23,"total":50,"percent":46.0}},"passed":23,"total":50,"percent":46.0}},"coverage":{"code":{"block":null,"line_statement":97.26,"branch":94.12,"condition_expression":81.71,"toggle":89.54,"fsm":69.16},"assertion":94.13,"functional":96.26},"cov_report_page":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"1.lc_ctrl_stress_all_with_rand_reset.6200108580904684745114867585872894466100017435644176271611490461098697711653","seed":6200108580904684745114867585872894466100017435644176271611490461098697711653,"line":1022,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8309429581 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8309429581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"5.lc_ctrl_stress_all_with_rand_reset.53177750122054620162457485919984127827650734542087448342977799710217797798977","seed":53177750122054620162457485919984127827650734542087448342977799710217797798977,"line":323,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 212963616 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 212963616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"7.lc_ctrl_stress_all_with_rand_reset.76130748102817926217637248715620576502062501352396122821429817900349190596826","seed":76130748102817926217637248715620576502062501352396122821429817900349190596826,"line":206,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4244835143 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4244835143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"9.lc_ctrl_stress_all_with_rand_reset.23404328405555761963159681047530465820661974946694243474037991654909436040557","seed":23404328405555761963159681047530465820661974946694243474037991654909436040557,"line":6186,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5661921665 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5661921665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"10.lc_ctrl_stress_all_with_rand_reset.98096569765004782086989774472385956830598034819023541129714609871292543306832","seed":98096569765004782086989774472385956830598034819023541129714609871292543306832,"line":507,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 985549008 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 985549008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"11.lc_ctrl_stress_all_with_rand_reset.56020882120093629083111385070451420397739160290655954441419965976781579562336","seed":56020882120093629083111385070451420397739160290655954441419965976781579562336,"line":10169,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 20487648175 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 20487648175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"19.lc_ctrl_stress_all_with_rand_reset.42497912843130628478853902693439203545400562325146801636965630440824603424826","seed":42497912843130628478853902693439203545400562325146801636965630440824603424826,"line":4302,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5218781707 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5218781707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"20.lc_ctrl_stress_all_with_rand_reset.2352081200949655847504076901033924811340288191933238609018767521467454142445","seed":2352081200949655847504076901033924811340288191933238609018767521467454142445,"line":6326,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 16979375252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 16979375252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"25.lc_ctrl_stress_all_with_rand_reset.37877728900342927146615770617613180944237299804611672824470842409939495203071","seed":37877728900342927146615770617613180944237299804611672824470842409939495203071,"line":963,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1008336630 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1008336630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"26.lc_ctrl_stress_all_with_rand_reset.63485896244186653914445472659182760003695088313794832963999129949300493374642","seed":63485896244186653914445472659182760003695088313794832963999129949300493374642,"line":1357,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7867899405 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 7867899405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"27.lc_ctrl_stress_all_with_rand_reset.54458473257406982287350239506935631795684615570989133127037214868467838494676","seed":54458473257406982287350239506935631795684615570989133127037214868467838494676,"line":2432,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1160943450 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1160943450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"29.lc_ctrl_stress_all_with_rand_reset.55222355542485103544277106185998574001817720323419589655598580221959927111028","seed":55222355542485103544277106185998574001817720323419589655598580221959927111028,"line":2966,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4995618390 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 4995618390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"30.lc_ctrl_stress_all_with_rand_reset.48052689811669146833741940311937917021792550626570659183454337677174045138454","seed":48052689811669146833741940311937917021792550626570659183454337677174045138454,"line":5933,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3575225652 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3575225652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"32.lc_ctrl_stress_all_with_rand_reset.63927005243630966430060469658366501780390453684712541316442023801425615808762","seed":63927005243630966430060469658366501780390453684712541316442023801425615808762,"line":151,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 551425941 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 551425941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"33.lc_ctrl_stress_all_with_rand_reset.28765567144795019832163692224950093504419402940351796688913919424380905334061","seed":28765567144795019832163692224950093504419402940351796688913919424380905334061,"line":259,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1971460471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1971460471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"36.lc_ctrl_stress_all_with_rand_reset.65052284598164375239310651577092980080074694143298671798400059102895590724036","seed":65052284598164375239310651577092980080074694143298671798400059102895590724036,"line":986,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1792237441 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1792237441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"37.lc_ctrl_stress_all_with_rand_reset.90153037172540602503886491970342544092270709992738575698513125526315568165022","seed":90153037172540602503886491970342544092270709992738575698513125526315568165022,"line":3555,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3912223775 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3912223775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"39.lc_ctrl_stress_all_with_rand_reset.49009797794285910434877163209513593552955004590884416114978209520936944822478","seed":49009797794285910434877163209513593552955004590884416114978209520936944822478,"line":610,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6436821315 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 6436821315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"40.lc_ctrl_stress_all_with_rand_reset.14433555862822437589312307447426964227937855778403448125984834659638743478554","seed":14433555862822437589312307447426964227937855778403448125984834659638743478554,"line":749,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2140253877 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2140253877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"43.lc_ctrl_stress_all_with_rand_reset.105577720578697153025072550446608568209084126269680291038176520736182512117033","seed":105577720578697153025072550446608568209084126269680291038176520736182512117033,"line":158,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1102091733 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1102091733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])":[{"name":"lc_ctrl_jtag_errors","qual_name":"2.lc_ctrl_jtag_errors.30751398436535226523578039621945951141322612180330052781315799859208167475158","seed":30751398436535226523578039621945951141322612180330052781315799859208167475158,"line":2859,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 1249520764 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1249520764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_jtag_errors","qual_name":"8.lc_ctrl_jtag_errors.15557223999599899799564764193560868852822599743331691871280541107466949566793","seed":15557223999599899799564764193560868852822599743331691871280541107466949566793,"line":2278,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_errors/latest/run.log","log_context":["UVM_ERROR @ 867324093 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 867324093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"13.lc_ctrl_stress_all_with_rand_reset.16839319839700671592609919282966043713513413852922443785483563457108676069408","seed":16839319839700671592609919282966043713513413852922443785483563457108676069408,"line":12015,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1440762997 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 1440762997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"21.lc_ctrl_stress_all.60888817102700469454361504798788832064900759281141502851517675160664537385876","seed":60888817102700469454361504798788832064900759281141502851517675160664537385876,"line":3979,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 7986489871 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 7986489871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"21.lc_ctrl_stress_all_with_rand_reset.36851352367241722453162746135677198208283712541740615814162741721553682310689","seed":36851352367241722453162746135677198208283712541740615814162741721553682310689,"line":2510,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3173655833 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 3173655833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"25.lc_ctrl_errors.14463188182754930660499196114677204355217837065284360777621013186004329656730","seed":14463188182754930660499196114677204355217837065284360777621013186004329656730,"line":2634,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 324478306 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 324478306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_errors","qual_name":"39.lc_ctrl_errors.41837138943217599271863274929022595567498884420567485251641112570100671464367","seed":41837138943217599271863274929022595567498884420567485251641112570100671464367,"line":2250,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_errors/latest/run.log","log_context":["UVM_ERROR @ 317816140 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 317816140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all","qual_name":"49.lc_ctrl_stress_all.59773256918206061393032913066451771471392410134908559164235680809647308719194","seed":59773256918206061393032913066451771471392410134908559164235680809647308719194,"line":13635,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 90601682461 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 90601682461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked*":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"23.lc_ctrl_stress_all_with_rand_reset.38263061800995440358144701296104123928583260293242352606914087422641797959109","seed":38263061800995440358144701296104123928583260293242352606914087422641797959109,"line":4510,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2746275214 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestLocked5\n","UVM_INFO @ 2746275214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"24.lc_ctrl_stress_all_with_rand_reset.110973244649905957559268598471998357345641927472451275689381657708323276432466","seed":110973244649905957559268598471998357345641927472451275689381657708323276432466,"line":2955,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3742682431 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error\n","UVM_INFO @ 3742682431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"41.lc_ctrl_stress_all_with_rand_reset.58294169100185659181061709374902876878067601245529166237988484282838958271776","seed":58294169100185659181061709374902876878067601245529166237988484282838958271776,"line":null,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["Job timed out after 180 minutes"]}],"UVM_FATAL (alert_receiver_driver.sv:218) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q":[{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"44.lc_ctrl_stress_all_with_rand_reset.98351263115841867987535495522732662703118502967007598815147896221428265254038","seed":98351263115841867987535495522732662703118502967007598815147896221428265254038,"line":1242,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 584394557 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_state_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q \n","UVM_INFO @ 584394557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"lc_ctrl_stress_all_with_rand_reset","qual_name":"46.lc_ctrl_stress_all_with_rand_reset.107391900490629888159873844658792582252363009057568865244492705874008856399091","seed":107391900490629888159873844658792582252363009057568865244492705874008856399091,"line":9785,"log_path":"/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_FATAL @ 11489854660 ps: (alert_receiver_driver.sv:218) [uvm_test_top.env.m_alert_agent_fatal_prog_error.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q \n","UVM_INFO @ 11489854660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":997,"total":1030,"percent":96.79611650485437}