{"block":{"name":"pattgen","variant":null,"commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-04-25T09:02:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":7.0,"sim_time":689.520684,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":14.525727999999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":58.6685,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":3.0,"sim_time":62.722945,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":124.291349,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":42.478277999999996,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":58.6685,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":124.291349,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":2928.0,"sim_time":600000.0,"passed":25,"total":50,"percent":50.0}},"passed":25,"total":50,"percent":50.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":66.0,"sim_time":9228.969539000002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":56.299614,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10559.0,"sim_time":1393787.944717,"passed":14,"total":50,"percent":28.0}},"passed":14,"total":50,"percent":28.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":44.20885,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":19.811751,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":68.214006,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":68.214006,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":14.525727999999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":58.6685,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":124.291349,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":108.691704,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":14.525727999999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":58.6685,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":124.291349,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":108.691704,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":309,"total":370,"percent":83.51351351351352},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_sec_cm":{"max_time":2.0,"sim_time":232.47968,"passed":5,"total":5,"percent":100.0},"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":91.278187,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":91.278187,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":160.0,"sim_time":6309.250389999999,"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0}},"passed":1,"total":50,"percent":2.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":262.0,"sim_time":10001.015976,"passed":38,"total":50,"percent":76.0}},"passed":38,"total":50,"percent":76.0}},"passed":38,"total":50,"percent":76.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","failed_jobs":{"buckets":{"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)":[{"name":"pattgen_inactive_level","qual_name":"0.pattgen_inactive_level.90343504176506145766489761663749098995292146045138402791563462611786259724582","seed":90343504176506145766489761663749098995292146045138402791563462611786259724582,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10046427308 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x51fe150, Comparison=CompareOpEq, exp_data=0x0, call_count=12)\n","UVM_INFO @ 10046427308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"6.pattgen_inactive_level.105457075755525216709772899851793709778464086558887917973815979062965903161839","seed":105457075755525216709772899851793709778464086558887917973815979062965903161839,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10039749221 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd1b31790, Comparison=CompareOpEq, exp_data=0x0, call_count=12)\n","UVM_INFO @ 10039749221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.107380774683855113335714933708041586358749868445263907076420931355449313665512","seed":107380774683855113335714933708041586358749868445263907076420931355449313665512,"line":155,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1148433460 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1148437007 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1148437007 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1148527916 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.106947053835703301381441825450826937758274436170284704081525420154177430503971","seed":106947053835703301381441825450826937758274436170284704081525420154177430503971,"line":225,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3774754511 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 3774779128 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3774779128 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 3774882577 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.38326085556919433884961104929775028080082664705100463289427272054353184501827","seed":38326085556919433884961104929775028080082664705100463289427272054353184501827,"line":120,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 432470963 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 432477094 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 432477094 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 432551560 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.38896431716011553048043313703068217463259584341830209517543148702192643739638","seed":38896431716011553048043313703068217463259584341830209517543148702192643739638,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2190995522 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2191175136 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2191175136 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2192975136 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.26009908619097129014213736768846881099462986482274008576983624406802967632996","seed":26009908619097129014213736768846881099462986482274008576983624406802967632996,"line":124,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1104194076 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1104194509 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1104194509 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1104267428 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.69522841362178033695871821371900978646052566779652983905774615564693363906912","seed":69522841362178033695871821371900978646052566779652983905774615564693363906912,"line":127,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 846283850 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 846290961 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 846290961 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 846382797 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.32660383145645947378943155531723451669884566035349244879365360974063808374742","seed":32660383145645947378943155531723451669884566035349244879365360974063808374742,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 971018543 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 971069358 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 971069358 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 971978448 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.75663446037700088830867132717388278929481462968525039552188004210423512318880","seed":75663446037700088830867132717388278929481462968525039552188004210423512318880,"line":232,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8982983931 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 8982995880 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 8982995880 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 8983132245 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.107185003238312974793037388317335671228635984376763065345853014180727585143917","seed":107185003238312974793037388317335671228635984376763065345853014180727585143917,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3507407001 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 3507425835 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3507425835 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 3507618145 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.12966073277723258956266004376062788354982832206819058681186376821683875014240","seed":12966073277723258956266004376062788354982832206819058681186376821683875014240,"line":160,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5037408893 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 5037418668 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5037418668 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 5037752004 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.39019867779068866334131935928244704333198295539558178857658538846532510537562","seed":39019867779068866334131935928244704333198295539558178857658538846532510537562,"line":254,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1651996386 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1652005921 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1652005921 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 1652097757 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.50707883064629194916610914982276165474204414637543432897090574588643635774527","seed":50707883064629194916610914982276165474204414637543432897090574588643635774527,"line":121,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2808631764 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2808669514 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2808669514 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2809044517 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.72528210835601302662896362233062579688010209574982398781907921008826233423424","seed":72528210835601302662896362233062579688010209574982398781907921008826233423424,"line":219,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2035784473 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2035784474 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2035784474 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2035826142 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.84215374879120629670849755233787484446697522790173815674114508295718801203258","seed":84215374879120629670849755233787484446697522790173815674114508295718801203258,"line":201,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1219845725 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1219854649 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1219854649 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 1219894649 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.7013658031960124466034893329554556558436770983591470388644227362804786600387","seed":7013658031960124466034893329554556558436770983591470388644227362804786600387,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 109520382 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 109525431 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 109525431 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 109575936 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.81274048578807980732992181308078875792366350493457008099552620279049088949208","seed":81274048578807980732992181308078875792366350493457008099552620279049088949208,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 509296534 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 509341213 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 509341213 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 509841213 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.76444552173093687791408982972896129829593144506397509895744351017986321771975","seed":76444552173093687791408982972896129829593144506397509895744351017986321771975,"line":120,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 983490223 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 983496973 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 983496973 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 983586973 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.41061981778764985231951305045073504030755389838652932501501748638940661568458","seed":41061981778764985231951305045073504030755389838652932501501748638940661568458,"line":119,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4122327788 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 4122428709 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4122428709 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 4123714422 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.24829431566183449021921459017131889829592296813029820456187809219167266221469","seed":24829431566183449021921459017131889829592296813029820456187809219167266221469,"line":128,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2131805678 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2131815948 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2131815948 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2132024278 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.26543662386528567803449496627847865604524244646171927326448778278644553581342","seed":26543662386528567803449496627847865604524244646171927326448778278644553581342,"line":116,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 267601156 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 267602029 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 267602029 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 267642845 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.93103754719038508259579646468164326501302273910903824014010277136335408670131","seed":93103754719038508259579646468164326501302273910903824014010277136335408670131,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2919078428 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2919108902 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2919108902 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2919378136 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.106665031994630999811456636163808858839111105400241195780439485973315953467360","seed":106665031994630999811456636163808858839111105400241195780439485973315953467360,"line":167,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1365859267 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1365869360 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1365869360 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1365950992 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.53643800282774721025309167760125761020014407412579589478715592403500887315848","seed":53643800282774721025309167760125761020014407412579589478715592403500887315848,"line":272,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14517456793 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 14517526400 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 14517526400 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 14518926400 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.100051327654130875077934244314962005540394225320517206191816095429484777880965","seed":100051327654130875077934244314962005540394225320517206191816095429484777880965,"line":182,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11607316913 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 11607327341 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 11607327341 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 11607727341 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.5023520543078110596710190754877232965415457329123296173426239548895868810017","seed":5023520543078110596710190754877232965415457329123296173426239548895868810017,"line":121,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 725848986 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 725855840 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 725855840 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 725961104 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.26895659914696493003576496851718360168109757109823606621793306707741133569946","seed":26895659914696493003576496851718360168109757109823606621793306707741133569946,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 816542418 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 816561808 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 816561808 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 817177192 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.97776104025601956146753362212776862387592739746124878099096421610188021510766","seed":97776104025601956146753362212776862387592739746124878099096421610188021510766,"line":255,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1588339177 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1588343580 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1588343580 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1588409514 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.46326036504246954156062635735736464531077653680555152112842763828174203765750","seed":46326036504246954156062635735736464531077653680555152112842763828174203765750,"line":204,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1290267352 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1290268834 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1290268834 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 1290340262 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.60755531829930555089221478662486485621787837034817179443534769804881131546699","seed":60755531829930555089221478662486485621787837034817179443534769804881131546699,"line":119,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 593142769 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 593150938 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 593150938 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 593254028 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.88632184565367815540382326547856769519115492214116220244458660300339670874125","seed":88632184565367815540382326547856769519115492214116220244458660300339670874125,"line":222,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6927144733 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 6927179429 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6927179429 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 6927579429 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.32585129100029456013202078187196045673426618936603149601312927379659103884478","seed":32585129100029456013202078187196045673426618936603149601312927379659103884478,"line":161,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 775092576 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 775094743 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 775094743 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 775209683 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.24890847379859751574159977813767585979661027573241156173428477421529063309600","seed":24890847379859751574159977813767585979661027573241156173428477421529063309600,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 201587088 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 201594669 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 201594669 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 201656523 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.34302118471835625182894006280586915464670003463542930652248608748515510635888","seed":34302118471835625182894006280586915464670003463542930652248608748515510635888,"line":168,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1771322705 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1771328908 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1771328908 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1771358908 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.79711987380094583617856762527859262787682293160986321484463774562831909119906","seed":79711987380094583617856762527859262787682293160986321484463774562831909119906,"line":169,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2663959061 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2663977003 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2663977003 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 2664032560 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.9264696772013617061359250586642707592673768823531984428620361393654323930722","seed":9264696772013617061359250586642707592673768823531984428620361393654323930722,"line":117,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1521036912 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1521037523 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1521037523 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1521117523 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.96508002645212732311025287482730781414716753167290400831957644688227173846570","seed":96508002645212732311025287482730781414716753167290400831957644688227173846570,"line":194,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3051932310 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 3051940650 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3051940650 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 3052044815 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.45059949999165073924047706790762237501589427180008588770799831097095514027565","seed":45059949999165073924047706790762237501589427180008588770799831097095514027565,"line":231,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1548501556 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1548503472 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1548503472 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 1548597225 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.76235808752183327992669850105232775258075673553490362937225572377492906151490","seed":76235808752183327992669850105232775258075673553490362937225572377492906151490,"line":148,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1523669290 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1523670297 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1523670297 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1523792745 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.43864241725424452402777239905564671899843279906180809147932100714714659856780","seed":43864241725424452402777239905564671899843279906180809147932100714714659856780,"line":117,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 630346733 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 630350582 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 630350582 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 630453672 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.84655064158076861154708674329883839554185123941817320537808892077479679485753","seed":84655064158076861154708674329883839554185123941817320537808892077479679485753,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2880123543 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 2880158065 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2880158065 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2880324733 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.36926982735008024858317356806695319816638214186292004697845063254320633712839","seed":36926982735008024858317356806695319816638214186292004697845063254320633712839,"line":206,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 302996585 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 302998487 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 302998487 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 303048487 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.19832872810761117377526910620953617531271909972170999752918364054809470110427","seed":19832872810761117377526910620953617531271909972170999752918364054809470110427,"line":147,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 244057496 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 244062979 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 244062979 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 244123585 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.113555515546291101869817674296615753728338955079861070719751066676665128245563","seed":113555515546291101869817674296615753728338955079861070719751066676665128245563,"line":237,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15086042358 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 15086062496 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 15086062496 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 15087395832 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.62315469463354904038109661137706721019543021554354637112197187796011579229236","seed":62315469463354904038109661137706721019543021554354637112197187796011579229236,"line":236,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 822599525 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 822604615 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 822604615 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 822625449 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.55979665369902308171799010702698156206813897111714020358203450490929833336966","seed":55979665369902308171799010702698156206813897111714020358203450490929833336966,"line":187,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 996169919 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 996176217 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 996176217 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 996207468 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.22818326810995742806535830240931901986593804646581044712180036706919684634702","seed":22818326810995742806535830240931901986593804646581044712180036706919684634702,"line":500,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 33289376950 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 33289426194 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 33289426194 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 10/10\n","UVM_INFO @ 33290126194 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.44852757674239383308801025676346046297381687719339087810397506390380299613425","seed":44852757674239383308801025676346046297381687719339087810397506390380299613425,"line":195,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 636069200 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 636073472 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 636073472 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 636164381 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.98413975593251065071463044383368017840877537286733183769570461344089794134232","seed":98413975593251065071463044383368017840877537286733183769570461344089794134232,"line":273,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1617074108 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 1617074272 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1617074272 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 1617114272 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.67770472022907442572084291383402036663673745863401209887109841216739582045896","seed":67770472022907442572084291383402036663673745863401209887109841216739582045896,"line":121,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 767023071 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_ERROR @ 767023306 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 767023306 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 767103306 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"Job timed out after * minutes":[{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.16260908668738504541621259911756279004437651468113654544273255646707647781791","seed":16260908668738504541621259911756279004437651468113654544273255646707647781791,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"1.pattgen_perf.54823555218809390002967475995135634277220013380677665471323034249185721469015","seed":54823555218809390002967475995135634277220013380677665471323034249185721469015,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"2.pattgen_perf.109628458462011715892604941023467128794581352492162122909869477038225310375739","seed":109628458462011715892604941023467128794581352492162122909869477038225310375739,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"4.pattgen_perf.41090619021030048446904325959621152272089910823897156249503982543399316229008","seed":41090619021030048446904325959621152272089910823897156249503982543399316229008,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"5.pattgen_perf.26909949183048795267234726200936424366592870469644847508097863951216002956010","seed":26909949183048795267234726200936424366592870469644847508097863951216002956010,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"8.pattgen_stress_all.31812421793184584837160460825598782563044585879913196327451564766777524818380","seed":31812421793184584837160460825598782563044585879913196327451564766777524818380,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.85308356240634130518957387850180958769640391107432444097404795323107568819750","seed":85308356240634130518957387850180958769640391107432444097404795323107568819750,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"12.pattgen_perf.69287739480717812203725589118647631994999296732781823745686442784599648117277","seed":69287739480717812203725589118647631994999296732781823745686442784599648117277,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"12.pattgen_stress_all.56971639158009969599724916583453532625569416708663819599470744601601238127320","seed":56971639158009969599724916583453532625569416708663819599470744601601238127320,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"13.pattgen_perf.35216890072365417779127470748293632884866575587088643114946296199037577531802","seed":35216890072365417779127470748293632884866575587088643114946296199037577531802,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"14.pattgen_perf.82516417168178110995466813274274766384062559373920355629324621410560183896441","seed":82516417168178110995466813274274766384062559373920355629324621410560183896441,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"16.pattgen_perf.20759141049599235217690828640955364762307301689580673183714866433650548190197","seed":20759141049599235217690828640955364762307301689580673183714866433650548190197,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"19.pattgen_stress_all.102032505843223423202640090097377733697832612816036172467918312257378033201481","seed":102032505843223423202640090097377733697832612816036172467918312257378033201481,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_stress_all","qual_name":"23.pattgen_stress_all.13421681517841150279353012751215439606669059344888042529933700343234503873912","seed":13421681517841150279353012751215439606669059344888042529933700343234503873912,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"28.pattgen_perf.89704428829840666907844415881898898092007700546946729022784850870015720934053","seed":89704428829840666907844415881898898092007700546946729022784850870015720934053,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"32.pattgen_perf.110344122798998357543074010080950017344289011236232763662866727175979893157144","seed":110344122798998357543074010080950017344289011236232763662866727175979893157144,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"33.pattgen_perf.77469374541595593949719632530047126818888493363534106239255665030240853136867","seed":77469374541595593949719632530047126818888493363534106239255665030240853136867,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.8503419391776894216024669227843537139629367376370569118282014413342642737523","seed":8503419391776894216024669227843537139629367376370569118282014413342642737523,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"35.pattgen_perf.106692483467962728407887315737948787907322217762149781553743346392798872592611","seed":106692483467962728407887315737948787907322217762149781553743346392798872592611,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"36.pattgen_perf.83684226445872867247126407345984882996146035532673727485804103880904930932263","seed":83684226445872867247126407345984882996146035532673727485804103880904930932263,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"38.pattgen_perf.98994717155069493402650239261800652077188514894494356597097657486324793266512","seed":98994717155069493402650239261800652077188514894494356597097657486324793266512,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"38.pattgen_stress_all.36837118168590191984344520611706673359757172533505903642175580438373209725914","seed":36837118168590191984344520611706673359757172533505903642175580438373209725914,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_stress_all","qual_name":"39.pattgen_stress_all.86878449535843687009419503855752735263999148712124718785508803548734576950745","seed":86878449535843687009419503855752735263999148712124718785508803548734576950745,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"40.pattgen_perf.84600698099721114832209609520022534982938066179106300823660634308374001916043","seed":84600698099721114832209609520022534982938066179106300823660634308374001916043,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"40.pattgen_stress_all.1668050988266903828742491927484237415402845882465856882848075286179758623829","seed":1668050988266903828742491927484237415402845882465856882848075286179758623829,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]},{"name":"pattgen_perf","qual_name":"47.pattgen_perf.41986604269711255638229943918435256078821146194493418713360960187542575262572","seed":41986604269711255638229943918435256078821146194493418713360960187542575262572,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_perf","qual_name":"48.pattgen_perf.86948591354467070527007725004727731697792685450738794249844242427367268709142","seed":86948591354467070527007725004727731697792685450738794249844242427367268709142,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_perf/latest/run.log","log_context":["Job timed out after 60 minutes"]},{"name":"pattgen_stress_all","qual_name":"48.pattgen_stress_all.43439430881851604613625819500714738550976858672328687177649026476004671330043","seed":43439430881851604613625819500714738550976858672328687177649026476004671330043,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all/latest/run.log","log_context":["Job timed out after 180 minutes"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"3.pattgen_perf.45493007792531310795801162948135785813675212107142295633089257539921390459359","seed":45493007792531310795801162948135785813675212107142295633089257539921390459359,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"6.pattgen_perf.24582489201644254853435330514602110942473354985336682750279097891799755356019","seed":24582489201644254853435330514602110942473354985336682750279097891799755356019,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"8.pattgen_perf.25874385239894430840974370654232450118693568199528844261038647065278143096250","seed":25874385239894430840974370654232450118693568199528844261038647065278143096250,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"18.pattgen_perf.1390983841768721094977974249929105554218361972237022393718804117680316441223","seed":1390983841768721094977974249929105554218361972237022393718804117680316441223,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"27.pattgen_perf.68807225456168282704866545503510702142967990512223538371161162084969874531093","seed":68807225456168282704866545503510702142967990512223538371161162084969874531093,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"31.pattgen_perf.88497657772434891591826236653554099135139411658956539989523945966720793654255","seed":88497657772434891591826236653554099135139411658956539989523945966720793654255,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"34.pattgen_perf.36409264637567036840153016096706687679559777615458196653457908030280449208579","seed":36409264637567036840153016096706687679559777615458196653457908030280449208579,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_perf/latest/run.log","log_context":["UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"3.pattgen_stress_all.111553188309830418096447389309023846503384025417033352523053124458846306210867","seed":111553188309830418096447389309023846503384025417033352523053124458846306210867,"line":152,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1393787944717 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","---------------------------------------\n","Name        Type          Size  Value  \n","---------------------------------------\n","exp_item    pattgen_item  -     @119289\n"]},{"name":"pattgen_stress_all","qual_name":"5.pattgen_stress_all.79940497343817900183329307711510267646417882043283947971608709295254833578671","seed":79940497343817900183329307711510267646417882043283947971608709295254833578671,"line":153,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 720659012 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10247\n"]},{"name":"pattgen_stress_all","qual_name":"7.pattgen_stress_all.65986982490833162734168001860746782686849864712743635165048076729338144297139","seed":65986982490833162734168001860746782686849864712743635165048076729338144297139,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 21085182432 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10096\n"]},{"name":"pattgen_stress_all","qual_name":"11.pattgen_stress_all.84659501195759014695216824029173253410973261006235866691658225330188372127782","seed":84659501195759014695216824029173253410973261006235866691658225330188372127782,"line":153,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 89352417710 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @10078\n"]},{"name":"pattgen_stress_all","qual_name":"13.pattgen_stress_all.87423891338232450587997033469096758696478624630129822716221190786821092855336","seed":87423891338232450587997033469096758696478624630129822716221190786821092855336,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @  37593928 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10183\n"]},{"name":"pattgen_stress_all","qual_name":"14.pattgen_stress_all.15376572970046847992235886258973385001098073807808017556403584259221411411586","seed":15376572970046847992235886258973385001098073807808017556403584259221411411586,"line":154,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6208687549986 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @94426\n"]},{"name":"pattgen_stress_all","qual_name":"16.pattgen_stress_all.110042884341887953268075695348194891246722840847930560008547191718295249434065","seed":110042884341887953268075695348194891246722840847930560008547191718295249434065,"line":149,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2920791680 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","-------------------------------------\n","Name       Type          Size  Value \n","-------------------------------------\n","exp_item   pattgen_item  -     @10302\n"]},{"name":"pattgen_stress_all","qual_name":"17.pattgen_stress_all.54020841693210677831765028993993949439690827356317659668261880303395326007661","seed":54020841693210677831765028993993949439690827356317659668261880303395326007661,"line":138,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 169264727 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10184\n"]},{"name":"pattgen_stress_all","qual_name":"18.pattgen_stress_all.8353026089625379907175751738920725695978722680086609010664835914023910921652","seed":8353026089625379907175751738920725695978722680086609010664835914023910921652,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 6242524950 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10096\n"]},{"name":"pattgen_stress_all","qual_name":"20.pattgen_stress_all.39494603544944245497500071488802263808721276661524360742318778092352222605226","seed":39494603544944245497500071488802263808721276661524360742318778092352222605226,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2855993713 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10262\n"]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.83240970408972991515825656533491605626795311096288144282506769914142965074775","seed":83240970408972991515825656533491605626795311096288144282506769914142965074775,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @  68125566 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10178\n"]},{"name":"pattgen_stress_all","qual_name":"24.pattgen_stress_all.66540901618909446774304678549714528096063021367249534032964974007265866628133","seed":66540901618909446774304678549714528096063021367249534032964974007265866628133,"line":157,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 26092488648 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11650\n"]},{"name":"pattgen_stress_all","qual_name":"25.pattgen_stress_all.91230148840848969831943020326263824332706565453541714086189526602787471605121","seed":91230148840848969831943020326263824332706565453541714086189526602787471605121,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1372274914349 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @88087\n"]},{"name":"pattgen_stress_all","qual_name":"26.pattgen_stress_all.16760240935702581194955132108889311605572716139393923079946065336327436686578","seed":16760240935702581194955132108889311605572716139393923079946065336327436686578,"line":152,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1467973146173 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10208\n"]},{"name":"pattgen_stress_all","qual_name":"27.pattgen_stress_all.75202006321233703343351359604496942847541062812281167161521552563054729345142","seed":75202006321233703343351359604496942847541062812281167161521552563054729345142,"line":150,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 22010374947 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11510\n"]},{"name":"pattgen_stress_all","qual_name":"28.pattgen_stress_all.20385737771745329401715321001046612158061155027542020805647405009921324106791","seed":20385737771745329401715321001046612158061155027542020805647405009921324106791,"line":153,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 50631375279 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10184\n"]},{"name":"pattgen_stress_all","qual_name":"30.pattgen_stress_all.19205994376252119389187932487769088279675819041088939719195713838794024475954","seed":19205994376252119389187932487769088279675819041088939719195713838794024475954,"line":148,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5379626674336 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10130\n"]},{"name":"pattgen_stress_all","qual_name":"31.pattgen_stress_all.52475679079708525946770774319891896927670586281397812706267537005894075169401","seed":52475679079708525946770774319891896927670586281397812706267537005894075169401,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @  90410929 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10232\n"]},{"name":"pattgen_stress_all","qual_name":"33.pattgen_stress_all.10778350360971105855209490907981376218241919934065273638394995397670875859320","seed":10778350360971105855209490907981376218241919934065273638394995397670875859320,"line":135,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @  99057276 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10162\n"]},{"name":"pattgen_stress_all","qual_name":"35.pattgen_stress_all.108503162003110810540287592262428766496621098844787240358473718483496332205720","seed":108503162003110810540287592262428766496621098844787240358473718483496332205720,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 147427764 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10180\n"]},{"name":"pattgen_stress_all","qual_name":"36.pattgen_stress_all.104022823191705199285503837874363301138054473164419741575596241235001575371048","seed":104022823191705199285503837874363301138054473164419741575596241235001575371048,"line":144,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @  83190375 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10207\n"]},{"name":"pattgen_stress_all","qual_name":"37.pattgen_stress_all.9856476261130540437487644138565444843891851270825171121963373636136080822975","seed":9856476261130540437487644138565444843891851270825171121963373636136080822975,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5475746437 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @10277\n"]},{"name":"pattgen_stress_all","qual_name":"41.pattgen_stress_all.38654351910195052405623567317922562312828478222272822018790064167905661412460","seed":38654351910195052405623567317922562312828478222272822018790064167905661412460,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 56324148670 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @12527\n"]},{"name":"pattgen_stress_all","qual_name":"42.pattgen_stress_all.50603125522720197833885036428987428617347876838402366332737050898148928622339","seed":50603125522720197833885036428987428617347876838402366332737050898148928622339,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 48230485017 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @10186\n"]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.28052591203249952203453287201610387906079947680092204589026311563243109581020","seed":28052591203249952203453287201610387906079947680092204589026311563243109581020,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 338566545 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","-----------------------------------\n","Name      Type          Size  Value\n","-----------------------------------\n","exp_item  pattgen_item  -     @2669\n"]},{"name":"pattgen_stress_all","qual_name":"49.pattgen_stress_all.77530159820965922391163194044814746195259506603870941563413776557951159918587","seed":77530159820965922391163194044814746195259506603870941563413776557951159918587,"line":143,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_stress_all/latest/run.log","log_context":["UVM_ERROR @ 135437880 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:\n","------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10236\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"5.pattgen_inactive_level.10881181184975956522876752393224027865008139490581161567072360977698336228548","seed":10881181184975956522876752393224027865008139490581161567072360977698336228548,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10038451515 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x459688d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)\n","UVM_INFO @ 10038451515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"8.pattgen_inactive_level.9541011932912617510798091801665584276482276681401182091477480567981038808407","seed":9541011932912617510798091801665584276482276681401182091477480567981038808407,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10027862070 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdaee4a90, Comparison=CompareOpEq, exp_data=0x0, call_count=7)\n","UVM_INFO @ 10027862070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"11.pattgen_inactive_level.57112841952842468621552656542640902862784319099810886777029637649163027647007","seed":57112841952842468621552656542640902862784319099810886777029637649163027647007,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10010593595 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4aaffc90, Comparison=CompareOpEq, exp_data=0x0, call_count=7)\n","UVM_INFO @ 10010593595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)":[{"name":"pattgen_inactive_level","qual_name":"15.pattgen_inactive_level.55450579977365351568514391017377168880786790815383146426402014228187462262560","seed":55450579977365351568514391017377168880786790815383146426402014228187462262560,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 15472805676 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x823538d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)\n","UVM_INFO @ 15472805676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"22.pattgen_inactive_level.80468488138676664951314470234330398361576788968456149508663309405465023259921","seed":80468488138676664951314470234330398361576788968456149508663309405465023259921,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10013205378 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4312d790, Comparison=CompareOpEq, exp_data=0x0, call_count=5)\n","UVM_INFO @ 10013205378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"43.pattgen_inactive_level.88279134295991075257607112120739832214284920054482252848643323061591791509520","seed":88279134295991075257607112120739832214284920054482252848643323061591791509520,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10010054838 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb8db3350, Comparison=CompareOpEq, exp_data=0x0, call_count=5)\n","UVM_INFO @ 10010054838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"pattgen_inactive_level","qual_name":"32.pattgen_inactive_level.17567317169089436825387513350276123173611388623014412627758072575797060474951","seed":17567317169089436825387513350276123173611388623014412627758072575797060474951,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10001015976 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd7efa950, Comparison=CompareOpEq, exp_data=0x0, call_count=3)\n","UVM_INFO @ 10001015976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"46.pattgen_inactive_level.16152555416114714812805826444598008780640801259832171814255217603969295527268","seed":16152555416114714812805826444598008780640801259832171814255217603969295527268,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10002445602 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc2cb0210, Comparison=CompareOpEq, exp_data=0x0, call_count=3)\n","UVM_INFO @ 10002445602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)":[{"name":"pattgen_inactive_level","qual_name":"39.pattgen_inactive_level.58328056263723579537694313204047222853466987378740930709507794804171929248714","seed":58328056263723579537694313204047222853466987378740930709507794804171929248714,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10008197193 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x941bc510, Comparison=CompareOpEq, exp_data=0x0, call_count=6)\n","UVM_INFO @ 10008197193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"pattgen_inactive_level","qual_name":"47.pattgen_inactive_level.56064126575614116511601941195029298827008895668689824534376223142953353743181","seed":56064126575614116511601941195029298827008895668689824534376223142953353743181,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log","log_context":["UVM_FATAL @ 10010052930 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x4d8cd150, Comparison=CompareOpEq, exp_data=0x0, call_count=8)\n","UVM_INFO @ 10010052930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":448,"total":570,"percent":78.59649122807018}