{"block":{"name":"rstmgr_cnsty_chk","variant":null,"commit":"8007f614bd52d7ac557e5e3253489f0bf7b820c5","commit_short":"8007f61","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5","revision_info":"GitHub Revision: [`8007f61`](https://github.com/lowrisc/opentitan/tree/8007f614bd52d7ac557e5e3253489f0bf7b820c5)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-04-25T09:02:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/rstmgr/dv/data/rstmgr_cnsty_chk_testplan.html","stages":{"unmapped":{"testpoints":{"Unmapped":{"tests":{"rstmgr_cnsty_chk_test":{"max_time":2.99,"sim_time":9812.208207,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0}},"coverage":{"code":{"block":null,"line_statement":98.41,"branch":98.31,"condition_expression":86.21,"toggle":100.0,"fsm":92.31},"assertion":100.0,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))":[{"name":"rstmgr_cnsty_chk_test","qual_name":"1.rstmgr_cnsty_chk_test.99764600549097455322590770279227229705812562470475447910442293449804650881871","seed":99764600549097455322590770279227229705812562470475447910442293449804650881871,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 1750616094 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 1768216094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 1785816094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 1803416094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 1821016094 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]},{"name":"rstmgr_cnsty_chk_test","qual_name":"6.rstmgr_cnsty_chk_test.16660068807378681460929661910517301372146387625919196997466432351920750625388","seed":16660068807378681460929661910517301372146387625919196997466432351920750625388,"line":175,"log_path":"/nightly/current_run/scratch/master/rstmgr_cnsty_chk-sim-vcs/6.rstmgr_cnsty_chk_test/latest/run.log","log_context":["UVM_ERROR @ 2020408927 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))  \n","UVM_INFO @ 2040728927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16\n","UVM_INFO @ 2061048927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16\n","UVM_INFO @ 2081368927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16\n","UVM_INFO @ 2101688927 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16\n"]}]}},"passed":8,"total":10,"percent":80.0}