{"block":{"name":"alert_handler","variant":null,"commit":"63c8a5025a0b02f50c3502e8ae0653cfd4a36ff9","commit_short":"63c8a50","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/63c8a5025a0b02f50c3502e8ae0653cfd4a36ff9","revision_info":"GitHub Revision: [`63c8a50`](https://github.com/lowrisc/opentitan/tree/63c8a5025a0b02f50c3502e8ae0653cfd4a36ff9)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-02T09:12:14Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"alert_handler_csr_hw_reset":{"max_time":9.9,"sim_time":121.066431,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"alert_handler_csr_rw":{"max_time":9.96,"sim_time":446.528105,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"alert_handler_csr_bit_bash":{"max_time":303.04,"sim_time":22802.019479,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"alert_handler_csr_aliasing":{"max_time":276.55,"sim_time":8113.843972,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"alert_handler_csr_mem_rw_with_rand_reset":{"max_time":16.23,"sim_time":228.31375,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"alert_handler_csr_rw":{"max_time":9.96,"sim_time":446.528105,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":276.55,"sim_time":8113.843972,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"esc_accum":{"tests":{"alert_handler_esc_alert_accum":{"max_time":280.22,"sim_time":5705.893771999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"esc_timeout":{"tests":{"alert_handler_esc_intr_timeout":{"max_time":63.10000000000001,"sim_time":1111.848584,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"entropy":{"tests":{"alert_handler_entropy":{"max_time":2224.9,"sim_time":47754.659647,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sig_int_fail":{"tests":{"alert_handler_sig_int_fail":{"max_time":62.42,"sim_time":8646.059647,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"clk_skew":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_alerts":{"tests":{"alert_handler_random_alerts":{"max_time":74.42,"sim_time":1322.4605,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"random_classes":{"tests":{"alert_handler_random_classes":{"max_time":67.72,"sim_time":2403.743464,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ping_timeout":{"tests":{"alert_handler_ping_timeout":{"max_time":591.2,"sim_time":64449.446792999996,"passed":22,"total":50,"percent":44.0}},"passed":22,"total":50,"percent":44.0},"lpg":{"tests":{"alert_handler_lpg":{"max_time":2558.96,"sim_time":62405.590207999994,"passed":49,"total":50,"percent":98.0},"alert_handler_lpg_stub_clk":{"max_time":2249.01,"sim_time":204388.71429300003,"passed":50,"total":50,"percent":100.0}},"passed":99,"total":100,"percent":99.0},"stress_all":{"tests":{"alert_handler_stress_all":{"max_time":2484.11,"sim_time":107371.99209,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_handler_entropy_stress_test":{"tests":{"alert_handler_entropy_stress":{"max_time":35.05,"sim_time":7751.3447989999995,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"alert_handler_alert_accum_saturation":{"tests":{"alert_handler_alert_accum_saturation":{"max_time":4.79,"sim_time":211.155586,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"intr_test":{"tests":{"alert_handler_intr_test":{"max_time":2.3,"sim_time":18.256754,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"alert_handler_tl_errors":{"max_time":22.52,"sim_time":1110.534446,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"alert_handler_tl_errors":{"max_time":22.52,"sim_time":1110.534446,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":9.9,"sim_time":121.066431,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":9.96,"sim_time":446.528105,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":276.55,"sim_time":8113.843972,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":51.82,"sim_time":6657.835131,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"alert_handler_csr_hw_reset":{"max_time":9.9,"sim_time":121.066431,"passed":5,"total":5,"percent":100.0},"alert_handler_csr_rw":{"max_time":9.96,"sim_time":446.528105,"passed":20,"total":20,"percent":100.0},"alert_handler_csr_aliasing":{"max_time":276.55,"sim_time":8113.843972,"passed":5,"total":5,"percent":100.0},"alert_handler_same_csr_outstanding":{"max_time":51.82,"sim_time":6657.835131,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":678,"total":710,"percent":95.49295774647888},"V2S":{"testpoints":{"shadow_reg_update_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":309.22,"sim_time":20680.118625,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":309.22,"sim_time":20680.118625,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_storage_error":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":309.22,"sim_time":20680.118625,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadowed_reset_glitch":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":309.22,"sim_time":20680.118625,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"alert_handler_shadow_reg_errors_with_csr_rw":{"max_time":985.9300000000001,"sim_time":332908.15025199996,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_intg_err":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0},"alert_handler_tl_intg_err":{"max_time":72.59,"sim_time":2233.1947769999997,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"alert_handler_tl_intg_err":{"max_time":72.59,"sim_time":2233.1947769999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_config_shadow":{"tests":{"alert_handler_shadow_reg_errors":{"max_time":309.22,"sim_time":20680.118625,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"sec_cm_ping_timer_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_loc_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_class_config_regwen":{"tests":{"alert_handler_smoke":{"max_time":64.13,"sim_time":2247.496845,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_alert_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":62.42,"sim_time":8646.059647,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sec_cm_lpg_intersig_mubi":{"tests":{"alert_handler_lpg":{"max_time":2558.96,"sim_time":62405.590207999994,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sec_cm_esc_intersig_diff":{"tests":{"alert_handler_sig_int_fail":{"max_time":62.42,"sim_time":8646.059647,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sec_cm_alert_rx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":2224.9,"sim_time":47754.659647,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_esc_tx_intersig_bkgn_chk":{"tests":{"alert_handler_entropy":{"max_time":2224.9,"sim_time":47754.659647,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sec_cm_esc_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_sparse":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_fsm_local_esc":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_fsm_global_esc":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_accu_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_esc_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_ctr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_ping_timer_lfsr_redun":{"tests":{"alert_handler_sec_cm":{"max_time":27.03,"sim_time":545.581311,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":262,"total":265,"percent":98.86792452830188},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"alert_handler_stress_all_with_rand_reset":{"max_time":392.62,"sim_time":36199.336468999994,"passed":27,"total":50,"percent":54.0}},"passed":27,"total":50,"percent":54.0}},"passed":27,"total":50,"percent":54.0}},"coverage":{"code":{"block":null,"line_statement":99.99,"branch":99.99,"condition_expression":97.5,"toggle":97.09,"fsm":100.0},"assertion":98.88,"functional":99.23},"cov_report_page":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/cov_report/dashboard.html","failed_jobs":{"buckets":{"UVM_ERROR (alert_handler_scoreboard.sv:343) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*])":[{"name":"alert_handler_sig_int_fail","qual_name":"2.alert_handler_sig_int_fail.47435401218606401227902990141139699979624743169403379900179945763321628228369","seed":47435401218606401227902990141139699979624743169403379900179945763321628228369,"line":82,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest/run.log","log_context":["UVM_ERROR @ 175808162 ps: (alert_handler_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (99 [0x63] vs 158 [0x9e]) \n","UVM_INFO @ 175808162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_sig_int_fail","qual_name":"37.alert_handler_sig_int_fail.91712310398932216565314739967284471428399559306670665711244937935335306994394","seed":91712310398932216565314739967284471428399559306670665711244937935335306994394,"line":82,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest/run.log","log_context":["UVM_ERROR @ 137350863 ps: (alert_handler_scoreboard.sv:343) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (174 [0xae] vs 65 [0x41]) \n","UVM_INFO @ 137350863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state":[{"name":"alert_handler_ping_timeout","qual_name":"2.alert_handler_ping_timeout.40887181130313060504910230475965543243592553399415761142342190658647129815723","seed":40887181130313060504910230475965543243592553399415761142342190658647129815723,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 5723557142 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 5723557142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"3.alert_handler_ping_timeout.52006770853875071723853859299906738233007355857677058047400124897648190894903","seed":52006770853875071723853859299906738233007355857677058047400124897648190894903,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 11737834680 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 11737834680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"6.alert_handler_ping_timeout.4530008042399663229125802890118959016896761878259682875154821889582106731179","seed":4530008042399663229125802890118959016896761878259682875154821889582106731179,"line":123,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 26190981559 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 26190981559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"8.alert_handler_ping_timeout.439976404843410331802631522242816214201413294462041024352746116397602158849","seed":439976404843410331802631522242816214201413294462041024352746116397602158849,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4646486358 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 4646486358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"9.alert_handler_ping_timeout.73000952141807331113688946870222282177080143652250139950037934954623210453033","seed":73000952141807331113688946870222282177080143652250139950037934954623210453033,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1519939320 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 1519939320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"10.alert_handler_ping_timeout.67859586198675821445361922451009292259162854824849471008668427004175893019445","seed":67859586198675821445361922451009292259162854824849471008668427004175893019445,"line":107,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3927126778 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 3927126778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"11.alert_handler_ping_timeout.28998336729368281538482766299491215802148491154913710292845555583786637929837","seed":28998336729368281538482766299491215802148491154913710292845555583786637929837,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10676310881 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 10676310881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"14.alert_handler_ping_timeout.109103805868858046771746776627637728883618927833199555656466327175636696106038","seed":109103805868858046771746776627637728883618927833199555656466327175636696106038,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4517897179 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 4517897179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"15.alert_handler_ping_timeout.90527822862009775721319556839000297340198046024136633481988726457581459007719","seed":90527822862009775721319556839000297340198046024136633481988726457581459007719,"line":112,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 10138196575 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 10138196575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"16.alert_handler_ping_timeout.97933693325258873734800536862990610400430433058124414787498158247841562783450","seed":97933693325258873734800536862990610400430433058124414787498158247841562783450,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 40921017795 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 40921017795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"21.alert_handler_ping_timeout.6603401581992969170216640209256610902014239612829013940261215730134899660413","seed":6603401581992969170216640209256610902014239612829013940261215730134899660413,"line":135,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 27450802842 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 27450802842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"26.alert_handler_ping_timeout.114360727348144463952741387395273295238798657462392477596507229106635174141847","seed":114360727348144463952741387395273295238798657462392477596507229106635174141847,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 15745013405 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 15745013405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"27.alert_handler_ping_timeout.49268865959397469348597851302507211139088718756618494075325197754058137500604","seed":49268865959397469348597851302507211139088718756618494075325197754058137500604,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2026304648 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2026304648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"28.alert_handler_ping_timeout.43431576669191822510139833908128899904163958332019953093234930410254573413346","seed":43431576669191822510139833908128899904163958332019953093234930410254573413346,"line":87,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 2215582068 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 2215582068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"31.alert_handler_ping_timeout.17250964798951576690688712517084069332696572096180068865886572046573386891844","seed":17250964798951576690688712517084069332696572096180068865886572046573386891844,"line":147,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 9563317058 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state\n","UVM_INFO @ 9563317058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"32.alert_handler_ping_timeout.12576387755656922708151098342666681246655000728894217263693752585465695249047","seed":12576387755656922708151098342666681246655000728894217263693752585465695249047,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 805663246 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 805663246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"33.alert_handler_ping_timeout.96084978387416688370654777610563493726344963683064990317889473257504868458430","seed":96084978387416688370654777610563493726344963683064990317889473257504868458430,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 24060691939 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 24060691939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"34.alert_handler_ping_timeout.25750635257075575046791541214902101381469558392824207162001438765744930207389","seed":25750635257075575046791541214902101381469558392824207162001438765744930207389,"line":99,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 3125282224 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 3125282224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"37.alert_handler_ping_timeout.16563007438984514640222993466987466645820633184574224180706337563101679070051","seed":16563007438984514640222993466987466645820633184574224180706337563101679070051,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 12418031454 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 12418031454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"38.alert_handler_ping_timeout.86300476754979170654562180081048991149847047661687166333275788620632714815097","seed":86300476754979170654562180081048991149847047661687166333275788620632714815097,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 12167341271 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 12167341271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"40.alert_handler_ping_timeout.115044836038823276121728909501466096108994321337430806352748994398953321983968","seed":115044836038823276121728909501466096108994321337430806352748994398953321983968,"line":93,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 1795221848 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 1795221848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"43.alert_handler_ping_timeout.23487006276847965345927323284557633343830695116985060996295352556715958511408","seed":23487006276847965345927323284557633343830695116985060996295352556715958511408,"line":102,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 14641914524 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state\n","UVM_INFO @ 14641914524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"45.alert_handler_ping_timeout.80307120095319266354201189676684876060742416341396620834617515105520276034059","seed":80307120095319266354201189676684876060742416341396620834617515105520276034059,"line":112,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 4625852866 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 4625852866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"46.alert_handler_ping_timeout.63752873337021759165790149342252648389843194354525959962223588894808700883652","seed":63752873337021759165790149342252648389843194354525959962223588894808700883652,"line":122,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 39964091745 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state\n","UVM_INFO @ 39964091745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"47.alert_handler_ping_timeout.95611877144723965195567840652767014611103929697551118399513211753015140506092","seed":95611877144723965195567840652767014611103929697551118399513211753015140506092,"line":99,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 30441093981 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 30441093981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"49.alert_handler_ping_timeout.32631247271898306557464500640442510809876620639472699351880043068964260051154","seed":32631247271898306557464500640442510809876620639472699351880043068964260051154,"line":129,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 30569963428 ps: (alert_handler_scoreboard.sv:486) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state\n","UVM_INFO @ 30569963428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"2.alert_handler_stress_all_with_rand_reset.111836186630840309520412811069268745216426015753049965538352488876087125877758","seed":111836186630840309520412811069268745216426015753049965538352488876087125877758,"line":85,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 320022486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 320022486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"3.alert_handler_stress_all_with_rand_reset.113030251581108252437425203461514833245914725604148181214521255717289499792787","seed":113030251581108252437425203461514833245914725604148181214521255717289499792787,"line":159,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3216521471 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3216521471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"5.alert_handler_stress_all_with_rand_reset.80409732187110206832124951745992926895451708541043845380248755581602120647138","seed":80409732187110206832124951745992926895451708541043845380248755581602120647138,"line":160,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3395009708 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3395009708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"6.alert_handler_stress_all_with_rand_reset.10302774084540959538540243557411064588056103176996704972263154892361403543625","seed":10302774084540959538540243557411064588056103176996704972263154892361403543625,"line":91,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3668467370 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 3668467370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"8.alert_handler_stress_all_with_rand_reset.106210886070450513712502135066456622273554471615928746178037896036718023718124","seed":106210886070450513712502135066456622273554471615928746178037896036718023718124,"line":122,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5594187780 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5594187780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"9.alert_handler_stress_all_with_rand_reset.70692258404630496251066293907364729850934923898697481599898173119656658346262","seed":70692258404630496251066293907364729850934923898697481599898173119656658346262,"line":205,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13744159516 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 13744159516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"12.alert_handler_stress_all_with_rand_reset.74037639874555426991130752561850353141213269731651159041775058576490034862891","seed":74037639874555426991130752561850353141213269731651159041775058576490034862891,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 107821347 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 107821347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"14.alert_handler_stress_all_with_rand_reset.87331151787761946150462353255867893384772632340615769576980493073134415564520","seed":87331151787761946150462353255867893384772632340615769576980493073134415564520,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2959105121 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2959105121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"19.alert_handler_stress_all_with_rand_reset.22017653884113561754869273627020985367329327187897842279455000517104653858864","seed":22017653884113561754869273627020985367329327187897842279455000517104653858864,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10968486229 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 10968486229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"21.alert_handler_stress_all_with_rand_reset.108645869230773863348172715238693543191414152569906249148381631860909365308991","seed":108645869230773863348172715238693543191414152569906249148381631860909365308991,"line":110,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 820885375 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 820885375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"23.alert_handler_stress_all_with_rand_reset.31509286682678612038293428613433420885749091677963909186229401148557209774056","seed":31509286682678612038293428613433420885749091677963909186229401148557209774056,"line":86,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2309631915 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2309631915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"26.alert_handler_stress_all_with_rand_reset.87294826565544917632928325012065786574994679622713555338582247636105288396312","seed":87294826565544917632928325012065786574994679622713555338582247636105288396312,"line":120,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2158484293 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2158484293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"27.alert_handler_stress_all_with_rand_reset.67236953173746428695089572319641686610504577354992661876069183569268964951827","seed":67236953173746428695089572319641686610504577354992661876069183569268964951827,"line":84,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 410562454 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 410562454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"28.alert_handler_stress_all_with_rand_reset.18512860590379232822820617353441272584708647028146878158137232024549392128277","seed":18512860590379232822820617353441272584708647028146878158137232024549392128277,"line":130,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1713957490 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1713957490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"31.alert_handler_stress_all_with_rand_reset.29061275235443823998614183880473660662951944978701588427759142868696709304300","seed":29061275235443823998614183880473660662951944978701588427759142868696709304300,"line":117,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5140884331 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 5140884331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"32.alert_handler_stress_all_with_rand_reset.41245302273733864660872258686353983768958913995594239440895308374388793164209","seed":41245302273733864660872258686353983768958913995594239440895308374388793164209,"line":188,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13080233284 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 13080233284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"33.alert_handler_stress_all_with_rand_reset.34786766521460257738943486411787680046651798659443796697019978423898948922967","seed":34786766521460257738943486411787680046651798659443796697019978423898948922967,"line":105,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2705368778 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2705368778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"37.alert_handler_stress_all_with_rand_reset.20694665480851346246637316332777137237429825320349263593493160138543965083856","seed":20694665480851346246637316332777137237429825320349263593493160138543965083856,"line":140,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8068483932 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8068483932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"40.alert_handler_stress_all_with_rand_reset.108582974364405762989034032069408738340070054516130226782915434041579576109366","seed":108582974364405762989034032069408738340070054516130226782915434041579576109366,"line":90,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2278081631 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2278081631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"41.alert_handler_stress_all_with_rand_reset.67827376708313309753856335167956292115318856423402400396719681642624471853174","seed":67827376708313309753856335167956292115318856423402400396719681642624471853174,"line":96,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1218760149 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1218760149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"44.alert_handler_stress_all_with_rand_reset.36635465559275026166496290270161877131425084494808524780973726420579670892039","seed":36635465559275026166496290270161877131425084494808524780973726420579670892039,"line":212,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8804448900 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 8804448900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"48.alert_handler_stress_all_with_rand_reset.80904378840760118179549565973015268821594967370275803193056311865759638423243","seed":80904378840760118179549565973015268821594967370275803193056311865759638423243,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 220862195 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 220862195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_stress_all_with_rand_reset","qual_name":"49.alert_handler_stress_all_with_rand_reset.80911590587531065025091690335296988790798581698807123488051685360712867446305","seed":80911590587531065025091690335296988790798581698807123488051685360712867446305,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 939584946 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 939584946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model.":[{"name":"alert_handler_ping_timeout","qual_name":"13.alert_handler_ping_timeout.102581171540500760819994124311945209513237399567835396716580965495637150477017","seed":102581171540500760819994124311945209513237399567835396716580965495637150477017,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 134475876 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 134475876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_ping_timeout","qual_name":"17.alert_handler_ping_timeout.21781075297342620619218666132947476251673009628114439751308363081383476396290","seed":21781075297342620619218666132947476251673009628114439751308363081383476396290,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest/run.log","log_context":["UVM_ERROR @ 991243970 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 991243970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"alert_handler_lpg","qual_name":"49.alert_handler_lpg.2249052174350352378654595317946390628715504522131477506687047576371515874380","seed":2249052174350352378654595317946390628715504522131477506687047576371515874380,"line":80,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_lpg/latest/run.log","log_context":["UVM_ERROR @ 42326721657 ps: (alert_handler_scoreboard.sv:608) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Register/crashdump mismatch. loc_alert_cause[0] is 0x1 in the crashdump and 0x0 in the register model.\n","UVM_INFO @ 42326721657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertIntFail)":[{"name":"alert_handler_stress_all","qual_name":"25.alert_handler_stress_all.34058020706102820506467089381588205288335891122396904090698955982919828477956","seed":34058020706102820506467089381588205288335891122396904090698955982919828477956,"line":83,"log_path":"/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2013669984 ps: (alert_handler_scoreboard.sv:258) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[1]: saw 0, but expected 1. (is_int_err = 0, local_alert_type = LocalAlertIntFail)\n","UVM_INFO @ 2013669984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":795,"total":850,"percent":93.52941176470588}