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(cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"4.edn_stress_all_with_rand_reset.6281933069726215544765981759270576449337711681950616453297302350411266690022","seed":6281933069726215544765981759270576449337711681950616453297302350411266690022,"line":252,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2766291523 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2766291523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"21.edn_stress_all_with_rand_reset.84467808302970362656254100921757644846734805823742180267202899215629207218618","seed":84467808302970362656254100921757644846734805823742180267202899215629207218618,"line":189,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1527166687 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1527166687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"24.edn_stress_all_with_rand_reset.32784188580454258583221273273907776133278786272535645155594214052660555843781","seed":32784188580454258583221273273907776133278786272535645155594214052660555843781,"line":209,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/24.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2439649640 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2439649640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"26.edn_stress_all_with_rand_reset.31742178507778874036032274283933208579635085736313859778333022984864369329177","seed":31742178507778874036032274283933208579635085736313859778333022984864369329177,"line":140,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/26.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 534647079 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 534647079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"48.edn_stress_all_with_rand_reset.98440491078343691659793071041194998030807090564946209117097135975783526750453","seed":98440491078343691659793071041194998030807090564946209117097135975783526750453,"line":153,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/48.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1038575704 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1038575704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"7.edn_disable_auto_req_mode.3942886149535210986322600489680598851275987486218721447749939439297356380009","seed":3942886149535210986322600489680598851275987486218721447749939439297356380009,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/7.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"10.edn_disable_auto_req_mode.9012811786234204181478928689766935322829711353575034613562470035349724126641","seed":9012811786234204181478928689766935322829711353575034613562470035349724126641,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/10.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"23.edn_disable_auto_req_mode.106349617914791069048815483408045783745253561679334994039685667899621861498837","seed":106349617914791069048815483408045783745253561679334994039685667899621861498837,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/23.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"40.edn_disable_auto_req_mode.43664361312998300613884176219915932699982893021310486242076708640136545435800","seed":43664361312998300613884176219915932699982893021310486242076708640136545435800,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/40.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.37835678309244681411108488966814491974113917747587379411185671129037459510732","seed":37835678309244681411108488966814491974113917747587379411185671129037459510732,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  46557327 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00000652 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  46557327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"17.edn_disable_auto_req_mode.68333927456815730170858129372887218084568834099867362558363891258731065295374","seed":68333927456815730170858129372887218084568834099867362558363891258731065295374,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/17.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  68114566 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0005e952 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  68114566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"30.edn_disable_auto_req_mode.14064537228574708772012261722663475019007470776441417203576233289310358944066","seed":14064537228574708772012261722663475019007470776441417203576233289310358944066,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/30.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  10808552 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0064e902 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  10808552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (edn_scoreboard.sv:318) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts":[{"name":"edn_stress_all_with_rand_reset","qual_name":"18.edn_stress_all_with_rand_reset.641606137474112810709873725678330348507626021489589024710131241303178215243","seed":641606137474112810709873725678330348507626021489589024710131241303178215243,"line":204,"log_path":"/nightly/current_run/scratch/master/edn_edn0-sim-vcs/18.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2720030356 ps: (edn_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed sw_cmd_sts == item.d_data (7 [0x7] vs 1 [0x1]) reg name: edn_reg_block.sw_cmd_sts\n","UVM_INFO @ 2720030356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1117,"total":1130,"percent":98.84955752212389}