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(cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"edn_stress_all_with_rand_reset","qual_name":"4.edn_stress_all_with_rand_reset.65594406300265161512015377176380234864850802392434788953363405164583516774029","seed":65594406300265161512015377176380234864850802392434788953363405164583516774029,"line":176,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 950368198 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 950368198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"9.edn_stress_all_with_rand_reset.68150366183526541032161029071393045984261282093565406309930144047285671840376","seed":68150366183526541032161029071393045984261282093565406309930144047285671840376,"line":194,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/9.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1763196578 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1763196578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"15.edn_stress_all_with_rand_reset.4243945570864609902730612239926246774034882294078479896771945099460183430352","seed":4243945570864609902730612239926246774034882294078479896771945099460183430352,"line":178,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1413437576 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1413437576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"21.edn_stress_all_with_rand_reset.59072461334350053088028349218824107186837465667806586263645336813328233228327","seed":59072461334350053088028349218824107186837465667806586263645336813328233228327,"line":242,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2476201769 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 2476201769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"37.edn_stress_all_with_rand_reset.46902621640183976992413346142668654274876360107014935917776596176348833918135","seed":46902621640183976992413346142668654274876360107014935917776596176348833918135,"line":117,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/37.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 365335937 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 365335937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"40.edn_stress_all_with_rand_reset.46277426972569271995810524900002514899632572932792753076432305449529543644834","seed":46277426972569271995810524900002514899632572932792753076432305449529543644834,"line":216,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1341673799 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1341673799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"42.edn_stress_all_with_rand_reset.34840436809507305716587253909605186666824012265176736481998819200574841201507","seed":34840436809507305716587253909605186666824012265176736481998819200574841201507,"line":131,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1328691252 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1328691252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_stress_all_with_rand_reset","qual_name":"48.edn_stress_all_with_rand_reset.13533169447460524614963215583469895712364832386096832442329672620886308722767","seed":13533169447460524614963215583469895712364832386096832442329672620886308722767,"line":166,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/48.edn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 918946567 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 918946567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"edn_disable_auto_req_mode","qual_name":"6.edn_disable_auto_req_mode.14566726269345335219917790387800596654171493332627980793278064081862353491828","seed":14566726269345335219917790387800596654171493332627980793278064081862353491828,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/6.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"13.edn_disable_auto_req_mode.77709406921185683778165206897189083071217323720895280918312665348948760401030","seed":77709406921185683778165206897189083071217323720895280918312665348948760401030,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/13.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"17.edn_disable_auto_req_mode.2156371964551935425939398186442415273267242138951256185145797927368861678093","seed":2156371964551935425939398186442415273267242138951256185145797927368861678093,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/17.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"45.edn_disable_auto_req_mode.13654275453334667145365825275380389230768446946981238779290219536403627695204","seed":13654275453334667145365825275380389230768446946981238779290219536403627695204,"line":89,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/45.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue\n","UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.":[{"name":"edn_disable_auto_req_mode","qual_name":"15.edn_disable_auto_req_mode.736273794713543758852168988071767425145956787040880847663880278383375352614","seed":736273794713543758852168988071767425145956787040880847663880278383375352614,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/15.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  20169676 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00340612 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  20169676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"26.edn_disable_auto_req_mode.72377768634257816501414941058074653260913830863682312688665474549210531433194","seed":72377768634257816501414941058074653260913830863682312688665474549210531433194,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/26.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  21881790 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x0091e972 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  21881790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"edn_disable_auto_req_mode","qual_name":"42.edn_disable_auto_req_mode.97583751866100770226717773696867745043120837858820556691039454894271381885482","seed":97583751866100770226717773696867745043120837858820556691039454894271381885482,"line":88,"log_path":"/nightly/current_run/scratch/master/edn_edn1-sim-vcs/42.edn_disable_auto_req_mode/latest/run.log","log_context":["UVM_FATAL @  42901804 ps: (edn_scoreboard.sv:428) [uvm_test_top.env.scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data 0x00e64662 in auto_req_mode has to match the value from sw_cmd_req register 0xxxxxxxxx. \n","UVM_INFO @  42901804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1115,"total":1130,"percent":98.67256637168141}