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---\n","\n","\n"]},{"name":"keymgr_kmac_rsp_err","qual_name":"23.keymgr_kmac_rsp_err.85854493485286292922393577823887983066426922552568508358728912849784442240313","seed":85854493485286292922393577823887983066426922552568508358728912849784442240313,"line":139,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest/run.log","log_context":["UVM_ERROR @  14102638 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @  14102638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_sideload_otbn","qual_name":"24.keymgr_sideload_otbn.53762001998201175669311796027390314092945369713323447264899256723648636604214","seed":53762001998201175669311796027390314092945369713323447264899256723648636604214,"line":89,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest/run.log","log_context":["UVM_ERROR @   2500769 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4\n","UVM_INFO @   2500769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"keymgr_stress_all_with_rand_reset","qual_name":"1.keymgr_stress_all_with_rand_reset.42774918023040592970396779454635460752825132456644355129064273428407360810232","seed":42774918023040592970396779454635460752825132456644355129064273428407360810232,"line":939,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 387297784 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 387297784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"2.keymgr_stress_all_with_rand_reset.21619613883194528330932303167306381120981067931202377137439481712716036036798","seed":21619613883194528330932303167306381120981067931202377137439481712716036036798,"line":193,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 464762757 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 464762757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"6.keymgr_stress_all_with_rand_reset.40828928272384302359872367444025087161905541034787210610431126123642837332394","seed":40828928272384302359872367444025087161905541034787210610431126123642837332394,"line":931,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1743425213 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 1743425213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"7.keymgr_stress_all_with_rand_reset.81807441637539710471579242688387982505734340411404957549912416737793712845851","seed":81807441637539710471579242688387982505734340411404957549912416737793712845851,"line":122,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 121099221 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 121099221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"16.keymgr_stress_all_with_rand_reset.49567447179299847993729510948236868486787013297849463515307163156537826836947","seed":49567447179299847993729510948236868486787013297849463515307163156537826836947,"line":1002,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 909684822 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 909684822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"19.keymgr_stress_all_with_rand_reset.19311451277129352108729220834183776407457023744747249297910301091499123294062","seed":19311451277129352108729220834183776407457023744747249297910301091499123294062,"line":586,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 175183341 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 175183341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"23.keymgr_stress_all_with_rand_reset.27200046864684064456195500605418721976594263320332891821810340600920975747251","seed":27200046864684064456195500605418721976594263320332891821810340600920975747251,"line":148,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 451132831 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 451132831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"24.keymgr_stress_all_with_rand_reset.48883000339556410852675962357683834450484909033303431530426760979937952093718","seed":48883000339556410852675962357683834450484909033303431530426760979937952093718,"line":561,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 333753193 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 333753193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"25.keymgr_stress_all_with_rand_reset.79619086171404804116614014112426785238645152973532561539766262074413505641788","seed":79619086171404804116614014112426785238645152973532561539766262074413505641788,"line":259,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/25.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 145973195 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 145973195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"31.keymgr_stress_all_with_rand_reset.45891751928564885273773366158240972923277224559874609934291724109154758295565","seed":45891751928564885273773366158240972923277224559874609934291724109154758295565,"line":121,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114053436 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 114053436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"32.keymgr_stress_all_with_rand_reset.106787888080629798890951956300252007120348488521896992183278866461741170683950","seed":106787888080629798890951956300252007120348488521896992183278866461741170683950,"line":405,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 157088306 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 157088306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"33.keymgr_stress_all_with_rand_reset.65324012282200720401606499872263744371255230706023408273554286448970112713367","seed":65324012282200720401606499872263744371255230706023408273554286448970112713367,"line":1095,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 350541879 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 350541879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"34.keymgr_stress_all_with_rand_reset.54824613053821114637366570759669244512631817509603044887444380265488244941929","seed":54824613053821114637366570759669244512631817509603044887444380265488244941929,"line":288,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 520065188 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 520065188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"37.keymgr_stress_all_with_rand_reset.46435303353192425587665408242827564874527858423183790311509443763443707269581","seed":46435303353192425587665408242827564874527858423183790311509443763443707269581,"line":585,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/37.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 156650709 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 156650709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"42.keymgr_stress_all_with_rand_reset.20422428632498349211768873842954532335664015647155477041937441218972293493815","seed":20422428632498349211768873842954532335664015647155477041937441218972293493815,"line":167,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 472971198 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 472971198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"43.keymgr_stress_all_with_rand_reset.60637772240291539751556093566957348288568659018072758581177616284951731672638","seed":60637772240291539751556093566957348288568659018072758581177616284951731672638,"line":867,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 387105404 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 387105404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"45.keymgr_stress_all_with_rand_reset.89565184547929828772022959550790613720802032178276787229751931806057211922311","seed":89565184547929828772022959550790613720802032178276787229751931806057211922311,"line":704,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 254234486 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 254234486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"keymgr_stress_all_with_rand_reset","qual_name":"48.keymgr_stress_all_with_rand_reset.48270442237261585229676392133407366225522430934932076546531682724794266325177","seed":48270442237261585229676392133407366225522430934932076546531682724794266325177,"line":729,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/48.keymgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 990782925 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. \n","UVM_INFO @ 990782925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!":[{"name":"keymgr_sync_async_fault_cross","qual_name":"20.keymgr_sync_async_fault_cross.39362054521747399290115310831228788433436145975826430906342348486390975348221","seed":39362054521747399290115310831228788433436145975826430906342348486390975348221,"line":166,"log_path":"/nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest/run.log","log_context":["UVM_ERROR @ 370023470 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!\n","UVM_INFO @ 370023470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1088,"total":1110,"percent":98.01801801801801}