{"block":{"name":"sysrst_ctrl","variant":null,"commit":"f3ee88db1f6c979a899d8b35ac6ea706a46db43b","commit_short":"f3ee88d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b","revision_info":"GitHub Revision: [`f3ee88d`](https://github.com/lowrisc/opentitan/tree/f3ee88db1f6c979a899d8b35ac6ea706a46db43b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-09T22:36:56Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":8.46,"sim_time":2112.2823110000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":10.44,"sim_time":2459.2082170000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":8.9,"sim_time":2401.501549,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":8.71,"sim_time":2340.651393,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":20.76,"sim_time":6034.3986859999995,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.78,"sim_time":2052.457984,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":224.56,"sim_time":76119.511395,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":14.42,"sim_time":3174.739795,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":7.84,"sim_time":2048.823766,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.78,"sim_time":2052.457984,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":14.42,"sim_time":3174.739795,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":165,"total":165,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":479.39,"sim_time":178554.274549,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":518.83,"sim_time":176796.030626,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":528.87,"sim_time":336006.00541900005,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":2277.11,"sim_time":1426954.866759,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":10.04,"sim_time":2510.378025,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.22,"sim_time":2074.752737,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":3600.104895564728,"sim_time":0.0,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":10.81,"sim_time":2612.023001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":251.67,"sim_time":971745.039003,"passed":46,"total":50,"percent":92.0}},"passed":46,"total":50,"percent":92.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":56.66,"sim_time":39998.255374,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":811.74,"sim_time":305983.074551,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.81,"sim_time":2012.4740829999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":8.94,"sim_time":2013.706458,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.04,"sim_time":2031.092385,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.04,"sim_time":2031.092385,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":20.76,"sim_time":6034.3986859999995,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.78,"sim_time":2052.457984,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":14.42,"sim_time":3174.739795,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":54.4,"sim_time":10550.731709000002,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":20.76,"sim_time":6034.3986859999995,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.78,"sim_time":2052.457984,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":14.42,"sim_time":3174.739795,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":54.4,"sim_time":10550.731709000002,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":709,"total":722,"percent":98.1994459833795},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":97.73,"sim_time":42008.263676,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":120.91,"sim_time":42460.842699,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":120.91,"sim_time":42460.842699,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":27.22,"sim_time":8062.604857,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"coverage":{"code":{"block":null,"line_statement":99.03,"branch":99.18,"condition_expression":98.09,"toggle":100.0,"fsm":96.79},"assertion":98.47,"functional":90.34},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"7.sysrst_ctrl_ultra_low_pwr.49527591863137331231105732564000255445160830640430315240803172294369399859476","seed":49527591863137331231105732564000255445160830640430315240803172294369399859476,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3168965248 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 3168965248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"20.sysrst_ctrl_ultra_low_pwr.72238809718514930134565248787075798126112750333520875772742021308664032671783","seed":72238809718514930134565248787075798126112750333520875772742021308664032671783,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 4565110590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 4885110590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 4898444883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"42.sysrst_ctrl_ultra_low_pwr.55374185992423323965569369243568315349920901831355766324628778642701277493243","seed":55374185992423323965569369243568315349920901831355766324628778642701277493243,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 394775051044 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 394775051044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"43.sysrst_ctrl_ultra_low_pwr.85046815324922946827575687674502192792979786074023155790428924717231690755986","seed":85046815324922946827575687674502192792979786074023155790428924717231690755986,"line":659,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 8820596241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 11250596241 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 11261672109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"Job timed out after * minutes":[{"name":"sysrst_ctrl_ec_pwr_on_rst","qual_name":"13.sysrst_ctrl_ec_pwr_on_rst.107037551351909873361952558895612375632335905879055272229712328377095726220503","seed":107037551351909873361952558895612375632335905879055272229712328377095726220503,"line":null,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest/run.log","log_context":[]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"16.sysrst_ctrl_combo_detect_with_pre_cond.5858081200841378846093787305100306716377485692257372878118799060643547943684","seed":5858081200841378846093787305100306716377485692257372878118799060643547943684,"line":678,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 60203988462 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2f\n","UVM_INFO @ 60204009296 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xc1\n","UVM_INFO @ 64303545538 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 64303630063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"27.sysrst_ctrl_combo_detect_with_pre_cond.64590897426865135034137854331923444817413010467083572496259070994914536072514","seed":64590897426865135034137854331923444817413010467083572496259070994914536072514,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 13917828302 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 13937828302 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_ERROR @ 14137878681 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (1 [0x1] vs 3 [0x3]) \n","UVM_INFO @ 14137878681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"66.sysrst_ctrl_combo_detect_with_pre_cond.38157715853546085018245324991481442225221600454814591311018650013064491859352","seed":38157715853546085018245324991481442225221600454814591311018650013064491859352,"line":693,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 38706037816 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 38706037816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"21.sysrst_ctrl_combo_detect_with_pre_cond.71882174982532783648193250481159091293740580632450166758093877450846791940357","seed":71882174982532783648193250481159091293740580632450166758093877450846791940357,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13520092383 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4 \n","UVM_INFO @ 13520092383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*])":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"29.sysrst_ctrl_stress_all_with_rand_reset.91094281890017985643678302965288784271867394457513295902529402587856728894354","seed":91094281890017985643678302965288784271867394457513295902529402587856728894354,"line":690,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11067495865 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 11067495865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"42.sysrst_ctrl_combo_detect_with_pre_cond.91138322988233276246159774440958156751882019354735516439866602064260511297254","seed":91138322988233276246159774440958156751882019354735516439866602064260511297254,"line":738,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 102213266636 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 102213266636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*])":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"49.sysrst_ctrl_stress_all_with_rand_reset.33281212403885391531725223435841669322139714164129820297825680768785580904227","seed":33281212403885391531725223435841669322139714164129820297825680768785580904227,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4188207435 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 4188207435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"73.sysrst_ctrl_combo_detect_with_pre_cond.22912035137448613290070791863438077216655568160802015967965305020838865698285","seed":22912035137448613290070791863438077216655568160802015967965305020838865698285,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 12831154174 ps: (cip_base_vseq.sv:708) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 12831154174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"84.sysrst_ctrl_combo_detect_with_pre_cond.50460437372151815306096215678355592263025344520576133231079054718970868652635","seed":50460437372151815306096215678355592263025344520576133231079054718970868652635,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 14936283611 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4 \n","UVM_INFO @ 14936283611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"95.sysrst_ctrl_combo_detect_with_pre_cond.20168211883776127704842009706548779239569183837092933940749841993751323692296","seed":20168211883776127704842009706548779239569183837092933940749841993751323692296,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 12710469963 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4 \n","UVM_INFO @ 12710469963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":917,"total":932,"percent":98.39055793991416}