{"block":{"name":"pattgen","variant":null,"commit":"5eeb50d2355fe0971a539579065bbb4a0596071b","commit_short":"5eeb50d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b","revision_info":"GitHub Revision: [`5eeb50d`](https://github.com/lowrisc/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-16T23:17:21Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":6.0,"sim_time":125.659557,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":109.81643799999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":7.0,"sim_time":15.655342000000001,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":4.0,"sim_time":192.521685,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":52.819237,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":8.0,"sim_time":38.323215,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":7.0,"sim_time":15.655342000000001,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":52.819237,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3601.0,"sim_time":0.0,"passed":23,"total":50,"percent":46.0}},"passed":23,"total":50,"percent":46.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":77.0,"sim_time":5177.7443619999995,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":3.0,"sim_time":87.44993600000001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10802.137805420905,"sim_time":0.0,"passed":21,"total":50,"percent":42.0}},"passed":21,"total":50,"percent":42.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":3.0,"sim_time":23.113399,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":21.871346000000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":66.696502,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":66.696502,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":109.81643799999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":7.0,"sim_time":15.655342000000001,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":52.819237,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":24.943488000000002,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":109.81643799999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":7.0,"sim_time":15.655342000000001,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":52.819237,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":24.943488000000002,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":314,"total":370,"percent":84.86486486486487},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":8.0,"sim_time":107.995789,"passed":20,"total":20,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":264.125089,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":8.0,"sim_time":107.995789,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":157.0,"sim_time":5395.453421,"passed":4,"total":50,"percent":8.0}},"passed":4,"total":50,"percent":8.0}},"passed":4,"total":50,"percent":8.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":235.0,"sim_time":10039.997817,"passed":37,"total":50,"percent":74.0}},"passed":37,"total":50,"percent":74.0}},"passed":37,"total":50,"percent":74.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.90081592504564286794782808850711888352635623665876178803285038250378923243046","seed":90081592504564286794782808850711888352635623665876178803285038250378923243046,"line":136,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4837253205 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4837253205 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 4837853208 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.35276983835959756110236564456085601888549970441415456054126730998109346726948","seed":35276983835959756110236564456085601888549970441415456054126730998109346726948,"line":189,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5273517044 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5273517044 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 5273928812 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.48839378229913486659675083285362342173817209834039913931578387777310727866753","seed":48839378229913486659675083285362342173817209834039913931578387777310727866753,"line":245,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1954343852 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1954343852 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1954399408 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.47017389226609438091282583667768084762333004868469526377191853913026244364782","seed":47017389226609438091282583667768084762333004868469526377191853913026244364782,"line":161,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5306359112 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5306359112 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 5307359114 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.111072883110145995842617475437943720592613256368384305329743874976941632602395","seed":111072883110145995842617475437943720592613256368384305329743874976941632602395,"line":214,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 17194338738 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 17194338738 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 17194755403 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.17807781109438778904515681635449226347702420272855224950394483195135565851621","seed":17807781109438778904515681635449226347702420272855224950394483195135565851621,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 284691868 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 284691868 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 284791868 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.38250403828468685187624963519583751052653618005673561800026687062422167596272","seed":38250403828468685187624963519583751052653618005673561800026687062422167596272,"line":233,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1061722935 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1061722935 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1061765039 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.76281927562207176972347499654054636174380189558038042047076290264780197366048","seed":76281927562207176972347499654054636174380189558038042047076290264780197366048,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1558811439 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1558811439 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1558903749 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.91304209950678109203146560396026706291821558758452328649330092875785048485807","seed":91304209950678109203146560396026706291821558758452328649330092875785048485807,"line":232,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3804036299 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3804036299 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 3804082811 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.48015998190262929100075643455171813760514350575666295927231160269159006095459","seed":48015998190262929100075643455171813760514350575666295927231160269159006095459,"line":183,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1611413820 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1611413820 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1611580484 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.101727247698917507143282490259072324557391542114908142653857822601397355921871","seed":101727247698917507143282490259072324557391542114908142653857822601397355921871,"line":133,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1716916068 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1716916068 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1716956884 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.32987131049291147780345801693047534725322603183589367585086634333369215948721","seed":32987131049291147780345801693047534725322603183589367585086634333369215948721,"line":338,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8511487444 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 8511487444 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 8511727444 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.46019133774963257493635303128712300205570066900853629687963290802288222047948","seed":46019133774963257493635303128712300205570066900853629687963290802288222047948,"line":117,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 493769969 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 493769969 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 493791021 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.1007189346687845385117760019448519208088753184834468424748592971909398071601","seed":1007189346687845385117760019448519208088753184834468424748592971909398071601,"line":115,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 481006621 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 481006621 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 481027673 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.36428319363766913239734248627332425182653592867569642666799456262679316440166","seed":36428319363766913239734248627332425182653592867569642666799456262679316440166,"line":147,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 134494663 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 134494663 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 134545168 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.51795652183972163139613095427167842847241432197553214182566476568172601950801","seed":51795652183972163139613095427167842847241432197553214182566476568172601950801,"line":121,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 875730907 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 875730907 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 875812539 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.10609144267291729474070268383561629464811579198685777309702194378172805681214","seed":10609144267291729474070268383561629464811579198685777309702194378172805681214,"line":244,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 14018331224 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 14018331224 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 14018775672 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.63400379959603543845908471591084255706481754428195481046923747228181853221358","seed":63400379959603543845908471591084255706481754428195481046923747228181853221358,"line":250,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 933998471 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 933998471 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 934040139 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.56813689140736525965081749267076875123632511549101898650353280185341461686310","seed":56813689140736525965081749267076875123632511549101898650353280185341461686310,"line":124,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2600905149 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2600905149 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2601201445 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.15131925689012004905847907990866621777366698279462431810469287095252201875090","seed":15131925689012004905847907990866621777366698279462431810469287095252201875090,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 441732443 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 441732443 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 442132443 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.58806437807824291324945089490548047711913957360791949492491096201496339386996","seed":58806437807824291324945089490548047711913957360791949492491096201496339386996,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 713044776 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 713044776 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 713076354 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.77886936189394607565084600626698285384417336974387253957461951403347076001113","seed":77886936189394607565084600626698285384417336974387253957461951403347076001113,"line":120,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1212812447 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1212812447 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1213145783 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.101520854336999456659808644261352080914282608430294595143999074423014394416461","seed":101520854336999456659808644261352080914282608430294595143999074423014394416461,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 240989830 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 240989830 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 241185481 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.49508382193199110836549209758765677886983323212596980223939635520837158112286","seed":49508382193199110836549209758765677886983323212596980223939635520837158112286,"line":123,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 903849932 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 903849932 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 903899932 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.5013246512050891970964704707039999359380690559226125701117858593559121083074","seed":5013246512050891970964704707039999359380690559226125701117858593559121083074,"line":115,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2078907348 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2078907348 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2079067348 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.100304198532814251981329400437558891619245561009104218901937743769067699093899","seed":100304198532814251981329400437558891619245561009104218901937743769067699093899,"line":195,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 754719420 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 754719420 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 754802756 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.61285956679364796171592571578699394831573308481480729877509303198996422175380","seed":61285956679364796171592571578699394831573308481480729877509303198996422175380,"line":226,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9369168511 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 9369168511 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 9369368511 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.79732961979512762045296430686313632201230520408244317074578514048880096744593","seed":79732961979512762045296430686313632201230520408244317074578514048880096744593,"line":239,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8162824399 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 8162824399 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 8163236167 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.63700927131966723597543970522440871735240815211905632456664311743029075678602","seed":63700927131966723597543970522440871735240815211905632456664311743029075678602,"line":124,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2321316566 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2321316566 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2321733236 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.69403486943077965354079179978854395111137063974447775781953569465256575169914","seed":69403486943077965354079179978854395111137063974447775781953569465256575169914,"line":131,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 773666098 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 773666098 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 773697025 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.3336961203046189022234439442770459379209770676748376645219617652144263906458","seed":3336961203046189022234439442770459379209770676748376645219617652144263906458,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 108709036 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 108709036 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 108761121 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.84710478034712801687819290473000555765683785283165900132906519051070265310087","seed":84710478034712801687819290473000555765683785283165900132906519051070265310087,"line":304,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2329920365 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2329920365 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 6/10\n","UVM_INFO @ 2330025625 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.93636755230658533433822119941925177700948548075429232319902827826714922442659","seed":93636755230658533433822119941925177700948548075429232319902827826714922442659,"line":119,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3728563304 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3728563304 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3728683304 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.85865598753873771981423672856917308271005606464425742343064586275323754049794","seed":85865598753873771981423672856917308271005606464425742343064586275323754049794,"line":161,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 776677516 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 776677516 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 776780606 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.107589869354154855265811857324161466466314536370796528430123704757801144945916","seed":107589869354154855265811857324161466466314536370796528430123704757801144945916,"line":391,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4330758645 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4330758645 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 4330865025 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.50642207549331449169348330325131122844740545161385371720171832080748889270321","seed":50642207549331449169348330325131122844740545161385371720171832080748889270321,"line":327,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1218907238 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1218907238 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 8/10\n","UVM_INFO @ 1218977238 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.34413023864103618997208695071411444583357273784353389124544616544368843624771","seed":34413023864103618997208695071411444583357273784353389124544616544368843624771,"line":237,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7906246720 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7906246720 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 7906538389 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.107726328932918503301922372568111454824160151905424819706084470591655424556215","seed":107726328932918503301922372568111454824160151905424819706084470591655424556215,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 113030156 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 113030156 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 113101584 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.51348247006045988859210981651327628750450177842917608657248799046047848249062","seed":51348247006045988859210981651327628750450177842917608657248799046047848249062,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7772211007 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7772211007 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 7773336007 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.31915427206502025791867487066176858225166442199251748894766720862510594993097","seed":31915427206502025791867487066176858225166442199251748894766720862510594993097,"line":124,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1538954427 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1538954427 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1539146737 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.27055373130655786262795328452432999645033508228506229941967230400766698939939","seed":27055373130655786262795328452432999645033508228506229941967230400766698939939,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 449473043 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 449473043 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 449681378 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.107354723710886048970805774338773623462091121243479563689063673984509617708890","seed":107354723710886048970805774338773623462091121243479563689063673984509617708890,"line":121,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1528569157 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1528569157 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1528650789 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.64814600451594656953719817452662475705777148062403429951980118869108820066844","seed":64814600451594656953719817452662475705777148062403429951980118869108820066844,"line":312,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4743513205 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4743513205 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 6/10\n","UVM_INFO @ 4743679869 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.92419832014326554956293823299538418809019881383882966617769353095398571767737","seed":92419832014326554956293823299538418809019881383882966617769353095398571767737,"line":126,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 451807076 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 451807076 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 451837688 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.9290369287730020262124474724195880506791750682241706578658005774693565638577","seed":9290369287730020262124474724195880506791750682241706578658005774693565638577,"line":145,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11312\n"]},{"name":"pattgen_stress_all","qual_name":"2.pattgen_stress_all.69683769214933540020150431939186286459291609618197150927739743448312285028003","seed":69683769214933540020150431939186286459291609618197150927739743448312285028003,"line":156,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11352\n"]},{"name":"pattgen_stress_all","qual_name":"5.pattgen_stress_all.44777953153205644839991344999376631175779627277654058370254868842294311896877","seed":44777953153205644839991344999376631175779627277654058370254868842294311896877,"line":146,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log","log_context":["----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @11318\n"]},{"name":"pattgen_stress_all","qual_name":"8.pattgen_stress_all.11255505279348586170425565947248540606158496308729736588580690674590612042599","seed":11255505279348586170425565947248540606158496308729736588580690674590612042599,"line":132,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11265\n"]},{"name":"pattgen_stress_all","qual_name":"17.pattgen_stress_all.39804998362978254194283610470274765418921532060579857483583364170719134896212","seed":39804998362978254194283610470274765418921532060579857483583364170719134896212,"line":160,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11486\n"]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.43442426311641123142813220151654496096605668385825008513919514774242537920084","seed":43442426311641123142813220151654496096605668385825008513919514774242537920084,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11315\n"]},{"name":"pattgen_stress_all","qual_name":"22.pattgen_stress_all.45562959884053207431737896449399681631229860808555346329565189909748876730218","seed":45562959884053207431737896449399681631229860808555346329565189909748876730218,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11336\n"]},{"name":"pattgen_stress_all","qual_name":"26.pattgen_stress_all.56802283862099972557711751290099053839618865568079989460583165702382677561130","seed":56802283862099972557711751290099053839618865568079989460583165702382677561130,"line":148,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11267\n"]},{"name":"pattgen_stress_all","qual_name":"31.pattgen_stress_all.5053867776149741109129812767961389360377867633846842748418428187867750112186","seed":5053867776149741109129812767961389360377867633846842748418428187867750112186,"line":148,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log","log_context":["----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @11322\n"]},{"name":"pattgen_stress_all","qual_name":"33.pattgen_stress_all.81662932082177250094921334582200957994412006097248686217482382978733353103891","seed":81662932082177250094921334582200957994412006097248686217482382978733353103891,"line":145,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11364\n"]},{"name":"pattgen_stress_all","qual_name":"35.pattgen_stress_all.34294984290891580830963137197934130168400462027348029636791601451748402795298","seed":34294984290891580830963137197934130168400462027348029636791601451748402795298,"line":133,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11362\n"]},{"name":"pattgen_stress_all","qual_name":"38.pattgen_stress_all.83899147186738324789284494720450646775308332364310796443177518476818713999596","seed":83899147186738324789284494720450646775308332364310796443177518476818713999596,"line":142,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11299\n"]},{"name":"pattgen_stress_all","qual_name":"39.pattgen_stress_all.100259475829669011141554733117955097373127234658502662262829021888552638435571","seed":100259475829669011141554733117955097373127234658502662262829021888552638435571,"line":146,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @16110\n"]},{"name":"pattgen_stress_all","qual_name":"40.pattgen_stress_all.534039723852615636889366863975011650525619714128931843863588657236590449475","seed":534039723852615636889366863975011650525619714128931843863588657236590449475,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11312\n"]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.11257518474463687553735729740864965192730168409030452939749467921370010956967","seed":11257518474463687553735729740864965192730168409030452939749467921370010956967,"line":162,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11307\n"]},{"name":"pattgen_stress_all","qual_name":"45.pattgen_stress_all.25063735085801305773613799941482535321121798222678845885591079599235331168793","seed":25063735085801305773613799941482535321121798222678845885591079599235331168793,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11296\n"]},{"name":"pattgen_stress_all","qual_name":"46.pattgen_stress_all.97413836824598740979089433592119664230250672271186966016017331067732646599888","seed":97413836824598740979089433592119664230250672271186966016017331067732646599888,"line":149,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11347\n"]},{"name":"pattgen_stress_all","qual_name":"47.pattgen_stress_all.57508389647951307989370643226744050996715267965185229993321299149905984221138","seed":57508389647951307989370643226744050996715267965185229993321299149905984221138,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11338\n"]},{"name":"pattgen_stress_all","qual_name":"48.pattgen_stress_all.54475615548090050378187438267775515403329818089256248142848737620419894963805","seed":54475615548090050378187438267775515403329818089256248142848737620419894963805,"line":135,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11326\n"]}],"Job timed out after * minutes":[{"name":"pattgen_perf","qual_name":"1.pattgen_perf.30158642806199826019004144901320143569291465912295063888234183455376161031255","seed":30158642806199826019004144901320143569291465912295063888234183455376161031255,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"1.pattgen_stress_all.46338419348400068112564106534297812426368401884796808575438251052668607122211","seed":46338419348400068112564106534297812426368401884796808575438251052668607122211,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"4.pattgen_stress_all.60191363295066186036433745219813809791859634346208216498861851188033539705190","seed":60191363295066186036433745219813809791859634346208216498861851188033539705190,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"7.pattgen_perf.47797645464613375375857928641093840538397563579151267813547593048866413291976","seed":47797645464613375375857928641093840538397563579151267813547593048866413291976,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.104120626405368722841967739723435089434659341009638281429397417638180559976636","seed":104120626405368722841967739723435089434659341009638281429397417638180559976636,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"12.pattgen_stress_all.90285981344130261727305758934879106041613052368995547493472946939372345976153","seed":90285981344130261727305758934879106041613052368995547493472946939372345976153,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"13.pattgen_stress_all.85549500709732908395934944504168472517844732966088716923863080124728888200009","seed":85549500709732908395934944504168472517844732966088716923863080124728888200009,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"14.pattgen_stress_all.80052149055786218684833087482229970663939882130407994157595360354483172371488","seed":80052149055786218684833087482229970663939882130407994157595360354483172371488,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"16.pattgen_perf.115756733591958260732730093795954434937902491066214443610810506063193216312361","seed":115756733591958260732730093795954434937902491066214443610810506063193216312361,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"16.pattgen_stress_all.87027358824014226816284344961044052606196948443100970977453383669105731285408","seed":87027358824014226816284344961044052606196948443100970977453383669105731285408,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"17.pattgen_perf.107581369993006852549882101937519457528407276416872671904651407682942734346372","seed":107581369993006852549882101937519457528407276416872671904651407682942734346372,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"26.pattgen_perf.73733775560500791097696911659143239614521397174953942685372151258792130441129","seed":73733775560500791097696911659143239614521397174953942685372151258792130441129,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"27.pattgen_perf.61970987880500944361145582515314356375531230479392339901433948306802481473323","seed":61970987880500944361145582515314356375531230479392339901433948306802481473323,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"28.pattgen_stress_all.32733228480448405530996656748398617209281988751710038608908797781355320857459","seed":32733228480448405530996656748398617209281988751710038608908797781355320857459,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"29.pattgen_perf.55702402983946472249947859944720395448418991236498252932555402502673207716795","seed":55702402983946472249947859944720395448418991236498252932555402502673207716795,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"30.pattgen_perf.19362695909577089037047494325262616208804533979398078826737062815721464185649","seed":19362695909577089037047494325262616208804533979398078826737062815721464185649,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"30.pattgen_stress_all.27745729437005656321218921416046678656464401364507320422845759789432522814596","seed":27745729437005656321218921416046678656464401364507320422845759789432522814596,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"32.pattgen_perf.76373833293546509067673112581123489515176139961524277830004729732561225374729","seed":76373833293546509067673112581123489515176139961524277830004729732561225374729,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"33.pattgen_perf.108794512436739553479028585250376175330875590795071535945897945776556368212697","seed":108794512436739553479028585250376175330875590795071535945897945776556368212697,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.30006573568062117285502321650230911343124998250479608894099844511545655352584","seed":30006573568062117285502321650230911343124998250479608894099844511545655352584,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"38.pattgen_perf.106933884909270017658253398474685216049189876106553660757073681793617635376520","seed":106933884909270017658253398474685216049189876106553660757073681793617635376520,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"40.pattgen_perf.38933583884700159236504911040795009440100447905827848789845242015928788468693","seed":38933583884700159236504911040795009440100447905827848789845242015928788468693,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"42.pattgen_perf.98033244198754240674505144131396980074151907696048937550081083888086833234177","seed":98033244198754240674505144131396980074151907696048937550081083888086833234177,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"45.pattgen_perf.33536052785440378072096950551056927772406787895969225902884496897289809905992","seed":33536052785440378072096950551056927772406787895969225902884496897289809905992,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_perf/latest/run.log","log_context":[]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)":[{"name":"pattgen_inactive_level","qual_name":"1.pattgen_inactive_level.105841738821014516416095834826710872172081998173386132234103153443317677048699","seed":105841738821014516416095834826710872172081998173386132234103153443317677048699,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10003671014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"3.pattgen_inactive_level.46787411136451135418218189855940992170118822425449977917023163558567604659454","seed":46787411136451135418218189855940992170118822425449977917023163558567604659454,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10006590487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"13.pattgen_inactive_level.10587447501539300878893241509867109479386380960446267283654437367878332678856","seed":10587447501539300878893241509867109479386380960446267283654437367878332678856,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10013133971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"30.pattgen_inactive_level.83144438943200987876351237556140990640551824365853184246915999711500457545833","seed":83144438943200987876351237556140990640551824365853184246915999711500457545833,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10041116361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.86040570059090482933945531881065764977684085696145125865038291743158129868803","seed":86040570059090482933945531881065764977684085696145125865038291743158129868803,"line":131,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 0 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.7741225344209263305438840317975618271874193643863202631280003167616598402516","seed":7741225344209263305438840317975618271874193643863202631280003167616598402516,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"4.pattgen_perf.82299480572350802435151459222138835933808857500862277041054632051619710640356","seed":82299480572350802435151459222138835933808857500862277041054632051619710640356,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_stress_all","qual_name":"6.pattgen_stress_all.96062907366384950801596554804654564696542306023723638769459989402544548120915","seed":96062907366384950801596554804654564696542306023723638769459989402544548120915,"line":136,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log","log_context":["UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"11.pattgen_perf.73536730348220436287195740562121108948009872031132264881290727539758934722794","seed":73536730348220436287195740562121108948009872031132264881290727539758934722794,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"12.pattgen_perf.50074956338765206359282427133945607522398365280920180011605781153165680370165","seed":50074956338765206359282427133945607522398365280920180011605781153165680370165,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"20.pattgen_perf.25298249432090899982229127049000505942878294922571365041653211241510718884637","seed":25298249432090899982229127049000505942878294922571365041653211241510718884637,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"21.pattgen_perf.87974452708272469898126257450761409390163028441171097906505232506751393569910","seed":87974452708272469898126257450761409390163028441171097906505232506751393569910,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"22.pattgen_perf.37781863453228333394254630254660961085328137004587170396699239577317116880708","seed":37781863453228333394254630254660961085328137004587170396699239577317116880708,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"34.pattgen_perf.12248666156291758808155712152019089881095155888831213252665714632181330793148","seed":12248666156291758808155712152019089881095155888831213252665714632181330793148,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"37.pattgen_perf.31684024804247211909409659885467138331157366277883241913358622498578853124327","seed":31684024804247211909409659885467138331157366277883241913358622498578853124327,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"39.pattgen_perf.54702416543696176608271549304572385592977021814607631647245720765422113406650","seed":54702416543696176608271549304572385592977021814607631647245720765422113406650,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"44.pattgen_perf.45905632199203188889425803379109919935349585551440691565580831446459410130384","seed":45905632199203188889425803379109919935349585551440691565580831446459410130384,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"46.pattgen_perf.100240814141012759796612959439889222907901017124278652713551242747065263965100","seed":100240814141012759796612959439889222907901017124278652713551242747065263965100,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"49.pattgen_perf.113346931655370408387346822797424483294331497146482026031514539978550766823135","seed":113346931655370408387346822797424483294331497146482026031514539978550766823135,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)":[{"name":"pattgen_inactive_level","qual_name":"14.pattgen_inactive_level.12581364760935739865997286277581043719085304665181287395057660527064925976116","seed":12581364760935739865997286277581043719085304665181287395057660527064925976116,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10075356526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"pattgen_inactive_level","qual_name":"15.pattgen_inactive_level.62559092425846343564600203660171029316698338659178760076961681713604339214858","seed":62559092425846343564600203660171029316698338659178760076961681713604339214858,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10007191511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)":[{"name":"pattgen_inactive_level","qual_name":"16.pattgen_inactive_level.72908259520243992272920024398332259922778431134827309116044768450375853510491","seed":72908259520243992272920024398332259922778431134827309116044768450375853510491,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10017528043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)":[{"name":"pattgen_inactive_level","qual_name":"28.pattgen_inactive_level.101510407093270488343144164384136006490340840838467622113989966328929041138131","seed":101510407093270488343144164384136006490340840838467622113989966328929041138131,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10039997817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)":[{"name":"pattgen_inactive_level","qual_name":"32.pattgen_inactive_level.44336910583510273928111128955154768506068930262620554171048348987315611783090","seed":44336910583510273928111128955154768506068930262620554171048348987315611783090,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10067976787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"43.pattgen_inactive_level.106578622127466386385083496262575283000611106708724981228869531479584181285795","seed":106578622127466386385083496262575283000611106708724981228869531479584181285795,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10029450859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)":[{"name":"pattgen_inactive_level","qual_name":"33.pattgen_inactive_level.30252885739280758506419916380806334706382556222145626003656614809033327804118","seed":30252885739280758506419916380806334706382556222145626003656614809033327804118,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10276945327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"37.pattgen_inactive_level.86752947530332142752944677272661446789963990338011439927399874331441981008673","seed":86752947530332142752944677272661446789963990338011439927399874331441981008673,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10011418978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"pattgen_inactive_level","qual_name":"39.pattgen_inactive_level.64130950822226535997139947338415798941860267125619090653019059145233137090587","seed":64130950822226535997139947338415798941860267125619090653019059145233137090587,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10002237587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":455,"total":570,"percent":79.82456140350877}