{"block":{"name":"sysrst_ctrl","variant":null,"commit":"5eeb50d2355fe0971a539579065bbb4a0596071b","commit_short":"5eeb50d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b","revision_info":"GitHub Revision: [`5eeb50d`](https://github.com/lowrisc/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-16T23:17:21Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":9.3,"sim_time":2113.6877940000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":11.08,"sim_time":2448.923989,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":7.39,"sim_time":2437.780068,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":9.25,"sim_time":2295.283073,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":13.77,"sim_time":4029.1166690000005,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":9.09,"sim_time":2060.8229380000002,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":180.48,"sim_time":52524.733218,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":9.07,"sim_time":2613.423807,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":8.92,"sim_time":2089.365715,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":9.09,"sim_time":2060.8229380000002,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.07,"sim_time":2613.423807,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":165,"total":165,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":414.06,"sim_time":145990.535928,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":365.73,"sim_time":137818.569874,"passed":90,"total":100,"percent":90.0}},"passed":90,"total":100,"percent":90.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":755.55,"sim_time":318764.208019,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":2591.29,"sim_time":1687031.53244,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":11.09,"sim_time":2507.9899130000003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.89,"sim_time":2023.4662409999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":196.32,"sim_time":180862.444819,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":11.12,"sim_time":2607.9310440000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":413.4,"sim_time":1715222.6403929999,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":46.83,"sim_time":34848.696434,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":469.22,"sim_time":139250.585068,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":8.16,"sim_time":2010.7261170000004,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.9,"sim_time":2009.943121,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.23,"sim_time":2048.9857039999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.23,"sim_time":2048.9857039999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":13.77,"sim_time":4029.1166690000005,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":9.09,"sim_time":2060.8229380000002,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.07,"sim_time":2613.423807,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":22.29,"sim_time":5197.526476,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":13.77,"sim_time":4029.1166690000005,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":9.09,"sim_time":2060.8229380000002,"passed":20,"total":20,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":9.07,"sim_time":2613.423807,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":22.29,"sim_time":5197.526476,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":706,"total":722,"percent":97.78393351800554},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":94.74,"sim_time":42010.444158,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":123.93,"sim_time":42478.218846,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":123.93,"sim_time":42478.218846,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":23.03,"sim_time":22686.512802,"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"passed":48,"total":50,"percent":96.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":99.56,"condition_expression":98.04,"toggle":100.0,"fsm":96.15},"assertion":98.37,"functional":91.92},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"0.sysrst_ctrl_ultra_low_pwr.58073148248517172441314122731601127888806988803324166465321039562762419143452","seed":58073148248517172441314122731601127888806988803324166465321039562762419143452,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4858214789 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 4858214789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"14.sysrst_ctrl_stress_all_with_rand_reset.82606708024036939372260499029162215535144101590313913497260155158987704419711","seed":82606708024036939372260499029162215535144101590313913497260155158987704419711,"line":731,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 14636132160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 17811132160 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 17829809336 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq\n","UVM_INFO @ 19826192936 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"24.sysrst_ctrl_stress_all.99495800926112634740755120875339084748546309303118685717277444593927582843016","seed":99495800926112634740755120875339084748546309303118685717277444593927582843016,"line":660,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 7005651347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 9245651347 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 9279927118 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_edge_detect_vseq\n","UVM_INFO @ 11275877503 ps: (sysrst_ctrl_edge_detect_vseq.sv:141) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Starting the body from edge_detect_vseq\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"36.sysrst_ctrl_stress_all.75947782674720122640338089327150217531698193343799310063285517932774456809950","seed":75947782674720122640338089327150217531698193343799310063285517932774456809950,"line":658,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 4549825371 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 7334935754 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7365769334 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ultra_low_pwr_vseq\n","UVM_INFO @ 9364993661 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:106) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Starting the body from ultra_low_pwr_vseq\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"37.sysrst_ctrl_ultra_low_pwr.69473487459622522372193033293217921399254330474323119836219949399290520145823","seed":69473487459622522372193033293217921399254330474323119836219949399290520145823,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2163126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 5128126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 6163126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 10503126649 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"3.sysrst_ctrl_combo_detect_with_pre_cond.110393192347460444260526860594571018498136848519198327670051899610672494944564","seed":110393192347460444260526860594571018498136848519198327670051899610672494944564,"line":690,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 35909977361 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 35909977361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"15.sysrst_ctrl_combo_detect_with_pre_cond.105063915598416150203694043560331363872538941332343388621502034650852137652112","seed":105063915598416150203694043560331363872538941332343388621502034650852137652112,"line":665,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13803513400 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 13803513400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"45.sysrst_ctrl_combo_detect_with_pre_cond.39710360970189443115414178275751812578691185019425579982747099781770525122384","seed":39710360970189443115414178275751812578691185019425579982747099781770525122384,"line":707,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 115867074054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 115867074054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"95.sysrst_ctrl_combo_detect_with_pre_cond.27052261497898121410726359007734045854830124772346580981956128624160538019352","seed":27052261497898121410726359007734045854830124772346580981956128624160538019352,"line":691,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 38243804579 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 38243804579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *":[{"name":"sysrst_ctrl_ec_pwr_on_rst","qual_name":"4.sysrst_ctrl_ec_pwr_on_rst.5494099966872817153195808554150762918284899267545487809302016230446758373799","seed":5494099966872817153195808554150762918284899267545487809302016230446758373799,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest/run.log","log_context":["UVM_INFO @ 2519511631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"16.sysrst_ctrl_stress_all_with_rand_reset.43932284016282659765761038049040786371397692587192348900668382198818268865561","seed":43932284016282659765761038049040786371397692587192348900668382198818268865561,"line":678,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10989644107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sysrst_ctrl_ec_pwr_on_rst","qual_name":"19.sysrst_ctrl_ec_pwr_on_rst.25042888832596275902002792614282255394657863003215489667963421196041697248317","seed":25042888832596275902002792614282255394657863003215489667963421196041697248317,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest/run.log","log_context":["UVM_INFO @ 2276033987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"5.sysrst_ctrl_combo_detect_with_pre_cond.44076664032702627488483876526503355903095802761393474288503527385673965299396","seed":44076664032702627488483876526503355903095802761393474288503527385673965299396,"line":719,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 68631856163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 68631856163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"54.sysrst_ctrl_combo_detect_with_pre_cond.63195137361364008701796169187932179013183540427865999344600896304021465600071","seed":63195137361364008701796169187932179013183540427865999344600896304021465600071,"line":722,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 98105733100 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 98105733100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"61.sysrst_ctrl_combo_detect_with_pre_cond.48359114482571422286692148365052676362772470048931171153469176393144551797004","seed":48359114482571422286692148365052676362772470048931171153469176393144551797004,"line":683,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 31288305469 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 31288305469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"9.sysrst_ctrl_combo_detect_with_pre_cond.88996132197905333792568198942613955920328539061858498186884786020541333861873","seed":88996132197905333792568198942613955920328539061858498186884786020541333861873,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 23490770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0\n","UVM_INFO @ 24620770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 24640770313 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 34667540336 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xe6\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"13.sysrst_ctrl_combo_detect_with_pre_cond.94892712165571456403905959099211046486750796452894355737860477235369014696861","seed":94892712165571456403905959099211046486750796452894355737860477235369014696861,"line":694,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 35296770591 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o \n","UVM_INFO @ 35296770591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"66.sysrst_ctrl_combo_detect_with_pre_cond.8716363181777686638035053636216771364244331445757753557896508339935949911781","seed":8716363181777686638035053636216771364244331445757753557896508339935949911781,"line":697,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 38806424952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 38826424952 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_ERROR @ 38951447872 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4]) \n","UVM_INFO @ 38951447872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}]}},"passed":914,"total":932,"percent":98.068669527897}