{"block":{"name":"uart","variant":null,"commit":"5eeb50d2355fe0971a539579065bbb4a0596071b","commit_short":"5eeb50d","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b","revision_info":"GitHub Revision: [`5eeb50d`](https://github.com/lowrisc/opentitan/tree/5eeb50d2355fe0971a539579065bbb4a0596071b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-16T23:17:21Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":39.43,"sim_time":6166.824547,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":0.97,"sim_time":23.11264,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.98,"sim_time":33.288638,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.86,"sim_time":428.54996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.14,"sim_time":28.685926,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.92,"sim_time":43.779603,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.98,"sim_time":33.288638,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.14,"sim_time":28.685926,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":235.89,"sim_time":90068.659503,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":39.43,"sim_time":6166.824547,"passed":50,"total":50,"percent":100.0},"uart_tx_rx":{"max_time":235.89,"sim_time":90068.659503,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":386.06,"sim_time":227998.492812,"passed":50,"total":50,"percent":100.0},"uart_rx_parity_err":{"max_time":213.05,"sim_time":123385.57906,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":235.89,"sim_time":90068.659503,"passed":50,"total":50,"percent":100.0},"uart_intr":{"max_time":386.06,"sim_time":227998.492812,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":469.08,"sim_time":194013.80196900002,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":285.9,"sim_time":145645.411117,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":427.41,"sim_time":91182.518496,"passed":298,"total":300,"percent":99.33333333333333}},"passed":298,"total":300,"percent":99.33333333333333},"rx_frame_err":{"tests":{"uart_intr":{"max_time":386.06,"sim_time":227998.492812,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":386.06,"sim_time":227998.492812,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":386.06,"sim_time":227998.492812,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":1042.05,"sim_time":24746.576307,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":23.94,"sim_time":14469.369573,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":23.94,"sim_time":14469.369573,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":86.56,"sim_time":44802.950827,"passed":5,"total":50,"percent":10.0}},"passed":5,"total":50,"percent":10.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":45.3,"sim_time":39460.789391000006,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":17.27,"sim_time":6126.173308,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":62.93,"sim_time":6860.233009,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":776.7,"sim_time":120062.04325399999,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":1304.42,"sim_time":336825.227037,"passed":38,"total":50,"percent":76.0}},"passed":38,"total":50,"percent":76.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.94,"sim_time":17.001106,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.97,"sim_time":52.105515,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.6,"sim_time":137.695616,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.6,"sim_time":137.695616,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.97,"sim_time":23.11264,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.98,"sim_time":33.288638,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.14,"sim_time":28.685926,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.18,"sim_time":30.154087999999998,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.97,"sim_time":23.11264,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.98,"sim_time":33.288638,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.14,"sim_time":28.685926,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.18,"sim_time":30.154087999999998,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1109,"total":1170,"percent":94.78632478632478},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.26,"sim_time":276.21856099999997,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.72,"sim_time":492.15387699999997,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.72,"sim_time":492.15387699999997,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":116.25,"sim_time":5301.242198,"passed":84,"total":100,"percent":84.0}},"passed":84,"total":100,"percent":84.0}},"passed":84,"total":100,"percent":84.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":91.55,"fsm":null},"assertion":97.12,"functional":99.5},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.46772100449965251743166759360248198131891894468902621676677273350917676335814","seed":46772100449965251743166759360248198131891894468902621676677273350917676335814,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 28333565769 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 28456935347 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 28462106698 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 28462220982 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.115283170572988888750834260881049888332660880720766947746516638888701251409343","seed":115283170572988888750834260881049888332660880720766947746516638888701251409343,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5732261909 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 5732282742 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5732303575 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5732324408 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.48368611916488714215964469724086030518864461423567681102408762278013079375347","seed":48368611916488714215964469724086030518864461423567681102408762278013079375347,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 122161976 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 122161976 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 122161976 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 191559894 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.11915915473844828147469561547702879648860500197976869620006273408179284790075","seed":11915915473844828147469561547702879648860500197976869620006273408179284790075,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10927861435 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10928861440 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10937128148 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10947328199 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.33242924876036226193119913119951423689419275053926015252552440126582669703729","seed":33242924876036226193119913119951423689419275053926015252552440126582669703729,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @   5120768 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 101609792 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 116191308 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 9,                                 clk_pulses: 0\n","UVM_ERROR @ 303169404 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 28,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.82311145732324455845054692659767786565729001321312759982703023646119330590475","seed":82311145732324455845054692659767786565729001321312759982703023646119330590475,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 777054589 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 872324589 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 883664589 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 883684589 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.54415852278283483683470287743160279429089148364298343311750133404423810574188","seed":54415852278283483683470287743160279429089148364298343311750133404423810574188,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 9153165414 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9158716390 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9223307710 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9229919902 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.56719483490101547878454666316283900300952719547627284468249467230745343136684","seed":56719483490101547878454666316283900300952719547627284468249467230745343136684,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2171390111 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2267981175 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 2267981175 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2298368687 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"8.uart_stress_all_with_rand_reset.12540514812966783089366800188950344819931983111326546077199273130683232934251","seed":12540514812966783089366800188950344819931983111326546077199273130683232934251,"line":170,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2031003247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2031933247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2033753247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2034663247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.73495244239010469032181334827133257415695523443099876413651035500997597781690","seed":73495244239010469032181334827133257415695523443099876413651035500997597781690,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 715078733 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3376198733 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 3376198733 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_INFO @ 4992058733 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/11\n"]},{"name":"uart_noise_filter","qual_name":"10.uart_noise_filter.62772373006617571306947501255715628775530250673127713559206472772029032887439","seed":62772373006617571306947501255715628775530250673127713559206472772029032887439,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/10.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 27768967769 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27771376884 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27774967829 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27777513309 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"15.uart_noise_filter.63584073832036856190615557729956433622208455404770106922513494463713476120932","seed":63584073832036856190615557729956433622208455404770106922513494463713476120932,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/15.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 15474016343 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 16629176343 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 17355336343 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 17355336343 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"16.uart_stress_all_with_rand_reset.16503612519989854403153071009713328329235901641507786115344372897602049363291","seed":16503612519989854403153071009713328329235901641507786115344372897602049363291,"line":203,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4577688143 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 4582844558 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/891\n","UVM_INFO @ 4677837181 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/891\n","UVM_ERROR @ 4681962313 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"18.uart_noise_filter.97528963263947824817960551725195914943379281547002587126909929504437713708145","seed":97528963263947824817960551725195914943379281547002587126909929504437713708145,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/18.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3462580849 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 27401090133 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/13\n","UVM_INFO @ 28134708999 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/13\n","UVM_INFO @ 32293962319 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/13\n"]},{"name":"uart_stress_all","qual_name":"19.uart_stress_all.42490744800152380229813504630662934820337472081931964257685280859361557635264","seed":42490744800152380229813504630662934820337472081931964257685280859361557635264,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/19.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4957514208 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5008385124 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5009278716 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5010087204 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"21.uart_noise_filter.52534681912592475831205167281413746665214416190689428366498535653693997233222","seed":52534681912592475831205167281413746665214416190689428366498535653693997233222,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1130477201 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1480188332 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 1480188332 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1482105014 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"21.uart_stress_all_with_rand_reset.73409676621479406521034996673266743392543815091209686738300874125529541987993","seed":73409676621479406521034996673266743392543815091209686738300874125529541987993,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2062175404 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 2542606858 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/926\n","UVM_INFO @ 2968180840 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/926\n","UVM_ERROR @ 3092467300 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 2\n"]},{"name":"uart_stress_all","qual_name":"21.uart_stress_all.89915902888335520362029756328790607048361362806365258681676561574131462380972","seed":89915902888335520362029756328790607048361362806365258681676561574131462380972,"line":87,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 77379332800 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 77413230488 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 77413230488 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 77418801872 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"22.uart_noise_filter.24117707766083356282161673092674374540201659787458641998915702118450617504694","seed":24117707766083356282161673092674374540201659787458641998915702118450617504694,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/22.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 27744916603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27745556603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27746316603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 27746916603 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"23.uart_stress_all.104263396388207289488474222386232296535820779873543659308200776438525986406380","seed":104263396388207289488474222386232296535820779873543659308200776438525986406380,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/23.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 18785519503 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18785879503 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18787679503 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18788399503 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"24.uart_noise_filter.102147968680497881564561566803149218139471695178053858618573103906321281157817","seed":102147968680497881564561566803149218139471695178053858618573103906321281157817,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/24.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 6535441711 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6535569916 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6535698121 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6535826326 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"25.uart_noise_filter.106188019198626751610301635056204482102946922535239438882273566582196806736290","seed":106188019198626751610301635056204482102946922535239438882273566582196806736290,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/25.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 92182079366 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 92537766422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 92538661166 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 92539450646 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"27.uart_noise_filter.3222483057284541873680212538467282803529508390659056602239506975480425365574","seed":3222483057284541873680212538467282803529508390659056602239506975480425365574,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/27.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 116904555 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 186760957 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 196480018 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 196521686 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"30.uart_noise_filter.31333687008536171979269863875076095553765502256571225155781063249534928312348","seed":31333687008536171979269863875076095553765502256571225155781063249534928312348,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/30.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5807098741 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 5807098741 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 34061199772 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/4\n","UVM_INFO @ 36452968906 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/4\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"30.uart_stress_all_with_rand_reset.68162457232044126737473459461773901330450066830835015194705244023050818947635","seed":68162457232044126737473459461773901330450066830835015194705244023050818947635,"line":119,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2790779422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2792659422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2793039422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2793679422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"31.uart_stress_all_with_rand_reset.1297705444805659826328704987146744902156948109304707731424898487329086393885","seed":1297705444805659826328704987146744902156948109304707731424898487329086393885,"line":119,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3618668581 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 3666828581 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/331\n","UVM_INFO @ 4003748581 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/331\n","UVM_INFO @ 4336468581 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/331\n"]},{"name":"uart_stress_all","qual_name":"32.uart_stress_all.4116396416467920122672782382560928771675846529496302097708409836277351737186","seed":4116396416467920122672782382560928771675846529496302097708409836277351737186,"line":116,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/32.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 150704864713 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 151753662577 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 151753662577 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 151816663081 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"35.uart_noise_filter.92823592217916450903999353439461555482348687736656451772333944224899304663577","seed":92823592217916450903999353439461555482348687736656451772333944224899304663577,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/35.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18870814049 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18871452359 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18991752517 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19126074218 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"36.uart_noise_filter.10176792983746433065946029632078860266978534004871796102297319914616559153140","seed":10176792983746433065946029632078860266978534004871796102297319914616559153140,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/36.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 171079920320 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 173070362774 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 173070362774 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 174352917047 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (243 [0xf3] vs 53 [0x35]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"37.uart_stress_all.105481817569232527503482147748778618392781018176836347217087731925707680323329","seed":105481817569232527503482147748778618392781018176836347217087731925707680323329,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/37.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 621821703 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 622502097 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 623161873 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 623821649 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"38.uart_noise_filter.107924113649414885752468165449006319813303068842711196682070610270136390042187","seed":107924113649414885752468165449006319813303068842711196682070610270136390042187,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/38.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 44755250827 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 44756150827 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 44757050827 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 44757950827 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"41.uart_stress_all.26204729931225114486111958209641494548171549668301080361758821017923039862342","seed":26204729931225114486111958209641494548171549668301080361758821017923039862342,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/41.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @  21180078 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  25630078 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  32830078 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 120420078 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n"]},{"name":"uart_noise_filter","qual_name":"42.uart_noise_filter.15778973556950812156691581980851765493762501869961569731280672551058594917716","seed":15778973556950812156691581980851765493762501869961569731280672551058594917716,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1718300515 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2868518050 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 2868518050 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2903476663 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"43.uart_noise_filter.30802166318437090970932868078745811366062853952645848362611704937572234217772","seed":30802166318437090970932868078745811366062853952645848362611704937572234217772,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/43.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 21011389702 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 21074608582 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 21518311462 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 21518311462 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"49.uart_noise_filter.24877429771272578568287512936930285863609162565002564227581994260222590718935","seed":24877429771272578568287512936930285863609162565002564227581994260222590718935,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/49.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  26451231 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 736544036 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 736564869 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 736585702 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (54 [0x36] vs 250 [0xfa]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.68473799287835099201032518624601892162016621455260772528253007044014863931679","seed":68473799287835099201032518624601892162016621455260772528253007044014863931679,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 111254121362 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 111254407078 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (105 [0x69] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 112194269860 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 112194269860 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"12.uart_noise_filter.30274927186416772142973282253315564077773739182297457188271196998907463052328","seed":30274927186416772142973282253315564077773739182297457188271196998907463052328,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/12.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  82206371 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @  82216371 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @  97136371 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @  98226371 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n"]},{"name":"uart_noise_filter","qual_name":"13.uart_noise_filter.96932740155582471360532300195813656045093464717714531362865450956680133035972","seed":96932740155582471360532300195813656045093464717714531362865450956680133035972,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1734594166 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1735005934 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1735064758 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1735300054 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 250 [0xfa]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"13.uart_stress_all_with_rand_reset.98966238617720901385628718888807518432669848923835524669901469644214121762606","seed":98966238617720901385628718888807518432669848923835524669901469644214121762606,"line":137,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10133984360 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10134043184 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (141 [0x8d] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 10134102008 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10134160832 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (141 [0x8d] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"13.uart_stress_all.63683602399600116005508259728905880917263742141127198042734998994327203665483","seed":63683602399600116005508259728905880917263742141127198042734998994327203665483,"line":104,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 356333447683 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 356333656018 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 356333864353 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 356333906020 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"14.uart_noise_filter.34092966563606787319401743191893273816778511435138890026455351411996255977040","seed":34092966563606787319401743191893273816778511435138890026455351411996255977040,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/14.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 7821598303 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 7821618303 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (132 [0x84] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 7950178303 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 7950198303 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"14.uart_stress_all.100029230127649723376286715806269031931106422104944994169147964261844507687705","seed":100029230127649723376286715806269031931106422104944994169147964261844507687705,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 13340576077 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 13340586077 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (171 [0xab] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 13381876077 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 13381876077 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"16.uart_noise_filter.44524047589348852732798885201503120547994890800977701583562768673948906708148","seed":44524047589348852732798885201503120547994890800977701583562768673948906708148,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2890963421 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2890974410 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2994732548 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 2994743537 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"17.uart_noise_filter.57873422256943552960220737659669291797153513970680000623676062532163671810021","seed":57873422256943552960220737659669291797153513970680000623676062532163671810021,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/17.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 311567615 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 311611093 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 595391999 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 595435477 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"19.uart_noise_filter.91622752890555697110428344015122121705224317028124068037446233308403430335688","seed":91622752890555697110428344015122121705224317028124068037446233308403430335688,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/19.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5325305761 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5325326169 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (66 [0x42] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5494753385 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 5494773793 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"23.uart_noise_filter.94039958241634548977509065165369630573488665649654008155650606852450108469041","seed":94039958241634548977509065165369630573488665649654008155650606852450108469041,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/23.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5020593481 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5020603898 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 5020614315 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5020624732 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"31.uart_noise_filter.113255141682107435346715448727232560525280886600652656635638717659171151328041","seed":113255141682107435346715448727232560525280886600652656635638717659171151328041,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/31.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2214440669 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2214461946 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (59 [0x3b] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2446147199 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2446147199 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"33.uart_noise_filter.64227675310202966328162911976510416566655675325585222017159121655555852889441","seed":64227675310202966328162911976510416566655675325585222017159121655555852889441,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/33.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 16721987427 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 16722042983 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 16778210099 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 16778210099 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"34.uart_noise_filter.18576229075210080362570309377272083183539881406800685514199265158429895856135","seed":18576229075210080362570309377272083183539881406800685514199265158429895856135,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/34.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2662843797 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2662854214 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2662864631 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2662875048 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"37.uart_noise_filter.115738556899613999195330851900265212306196910718296134714685244294905700036134","seed":115738556899613999195330851900265212306196910718296134714685244294905700036134,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/37.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 20406184394 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 20406224394 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (239 [0xef] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 20477624394 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 20477624394 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"39.uart_noise_filter.38992958770417678704596495179580922973086328045374674230290512419456636466803","seed":38992958770417678704596495179580922973086328045374674230290512419456636466803,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/39.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 233688711 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 233699128 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 233709545 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 233719962 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 183 [0xb7]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"40.uart_noise_filter.66276671215184342995782262139042740748692318566224428713868245927801209677471","seed":66276671215184342995782262139042740748692318566224428713868245927801209677471,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 283499661 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 283582996 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 433552662 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 433569329 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"44.uart_noise_filter.69642340273267774946430267422416454540296545008470366730545282384990737584440","seed":69642340273267774946430267422416454540296545008470366730545282384990737584440,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 5953136602 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 5953296602 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 6141576602 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6141576602 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"47.uart_noise_filter.89983478251165198227775387399639854055798658066689322234589913730624355307710","seed":89983478251165198227775387399639854055798658066689322234589913730624355307710,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/47.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 22739158358 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 22739269469 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 189 [0xbd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 22739491691 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 22739602802 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"48.uart_noise_filter.10306206065954900701498612224129690666450921076957236236119124017024695990999","seed":10306206065954900701498612224129690666450921076957236236119124017024695990999,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/48.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2327405257 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2327460813 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2327516369 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2327571925 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"48.uart_stress_all.21959100691219550696763608604101945053286037815337752009644912630928265108129","seed":21959100691219550696763608604101945053286037815337752009644912630928265108129,"line":83,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/48.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 236294137975 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 236294262975 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (228 [0xe4] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 236739762975 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 239025512975 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 18,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"96.uart_stress_all_with_rand_reset.49757644570045222250576090828259497748740357792676388847606148301073024654400","seed":49757644570045222250576090828259497748740357792676388847606148301073024654400,"line":105,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 364280402 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 364412478 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 443412794 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/498\n","UVM_ERROR @ 472790270 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_perf","qual_name":"7.uart_perf.113508643752494333304054142607306707867405462661094548617120306700714676563269","seed":113508643752494333304054142607306707867405462661094548617120306700714676563269,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_perf/latest/run.log","log_context":["UVM_INFO @ 1357533232 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/6\n","UVM_INFO @ 2647383231 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6\n","UVM_INFO @ 2735023231 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/6\n","UVM_INFO @ 7188703231 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/6\n"]},{"name":"uart_stress_all","qual_name":"9.uart_stress_all.31591177857261204264344069234039880736856305143116570686513774576089430074930","seed":31591177857261204264344069234039880736856305143116570686513774576089430074930,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_stress_all/latest/run.log","log_context":["UVM_INFO @ 90668797072 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/8\n","UVM_INFO @ 94553804883 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/8\n","UVM_INFO @ 99280944897 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/8\n","UVM_INFO @ 106972884883 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/8\n"]},{"name":"uart_fifo_reset","qual_name":"226.uart_fifo_reset.71296050475221715676909271831031803045546024456402039983602278783516249244150","seed":71296050475221715676909271831031803045546024456402039983602278783516249244150,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/226.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 307861651 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10\n","UVM_INFO @ 477561651 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10\n","UVM_INFO @ 6469961651 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10\n","UVM_INFO @ 25769381651 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10\n"]}],"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"11.uart_noise_filter.250210304893717182210794567467742130908581577780293859531544986999571260299","seed":250210304893717182210794567467742130908581577780293859531544986999571260299,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2937967479 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2938127479 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2938127479 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3149887479 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"14.uart_stress_all_with_rand_reset.111481919410863940876158007954541865181542940691140605291261608694656624088647","seed":111481919410863940876158007954541865181542940691140605291261608694656624088647,"line":143,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 22566446207 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 22566446207 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 22583585978 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 6/10\n"]},{"name":"uart_noise_filter","qual_name":"20.uart_noise_filter.24562395693071759240226113525903412892904021603544953343143655875246556773335","seed":24562395693071759240226113525903412892904021603544953343143655875246556773335,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 12470982729 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12470982729 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 12514233075 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12514524744 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"28.uart_noise_filter.66159770564069879341318454592925249384476341826002750715696336502288026137132","seed":66159770564069879341318454592925249384476341826002750715696336502288026137132,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/28.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 340687176 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 340687176 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 609998100 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 609998100 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"32.uart_noise_filter.108325744845464414909627975011945279606335298818401279997787371265177936578000","seed":108325744845464414909627975011945279606335298818401279997787371265177936578000,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/32.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 123498715422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 123516315422 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 123516315422 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 123532315422 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_long_xfer_wo_dly","qual_name":"38.uart_long_xfer_wo_dly.114803492629491442595886256527684657717380199484315910307195216360996389682230","seed":114803492629491442595886256527684657717380199484315910307195216360996389682230,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest/run.log","log_context":["UVM_ERROR @ 15345425835 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 16278021531 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 16829084763 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 17503913691 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"42.uart_stress_all_with_rand_reset.95709548952467832210396807726194959966079412798899155006926809622260344941587","seed":95709548952467832210396807726194959966079412798899155006926809622260344941587,"line":133,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9772991126 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9772991126 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 9785638286 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 9845894488 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n"]},{"name":"uart_stress_all","qual_name":"44.uart_stress_all.15140233207182300742010824882178844637477069876726628976803684349377866102895","seed":15140233207182300742010824882178844637477069876726628976803684349377866102895,"line":108,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 336356817037 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 336356817037 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 336363567037 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 336363567037 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"45.uart_stress_all.41814403183413202861732186454875929839136205969623764238322486808527343236402","seed":41814403183413202861732186454875929839136205969623764238322486808527343236402,"line":93,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/45.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 118883724067 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 118883835179 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (62 [0x3e] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 118883890735 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 119518951371 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"47.uart_stress_all_with_rand_reset.19630462028784665752681162122488287321058336763367512339495241622134975533163","seed":19630462028784665752681162122488287321058336763367512339495241622134975533163,"line":98,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3499121300 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3502303115 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 3502303115 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3504212204 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"70.uart_stress_all_with_rand_reset.88011308459416888765471902908490855284568167007771639664354677723413251016571","seed":88011308459416888765471902908490855284568167007771639664354677723413251016571,"line":120,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 13902293998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 13908693998 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 13908693998 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 13910093998 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"75.uart_stress_all_with_rand_reset.12337888344899369391384786618700699306565101729259825026416135841624009548132","seed":12337888344899369391384786618700699306565101729259825026416135841624009548132,"line":146,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10163738723 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10163738723 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 10249864412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 10374240407 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n"]}],"UVM_ERROR (cip_base_vseq.sv:1236) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"26.uart_stress_all_with_rand_reset.14378041926829517443766848036930107449143858964161847044464216104089702791400","seed":14378041926829517443766848036930107449143858964161847044464216104089702791400,"line":152,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2688452253 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2688452253 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 2688462165 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"94.uart_stress_all_with_rand_reset.24212505452985320080032232407862488075184489436489614176725158763759268857630","seed":24212505452985320080032232407862488075184489436489614176725158763759268857630,"line":98,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 976315418 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 976315418 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 976320148 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"35.uart_stress_all_with_rand_reset.43253656898274140123952327562344559897490882186513155966407089393481579582422","seed":43253656898274140123952327562344559897490882186513155966407089393481579582422,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 274310458 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 526687477 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 526687477 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_INFO @ 561479422 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/638\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark":[{"name":"uart_stress_all_with_rand_reset","qual_name":"99.uart_stress_all_with_rand_reset.66972559907322106932023473540884373205153315958970221960852403342188213716767","seed":66972559907322106932023473540884373205153315958970221960852403342188213716767,"line":172,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2163296612 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/739\n","UVM_INFO @ 2249057183 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/739\n","UVM_INFO @ 2288726215 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/739\n","UVM_INFO @ 2382661823 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/739\n"]},{"name":"uart_fifo_reset","qual_name":"212.uart_fifo_reset.7232138810392848772980434083747334711711477329722253798827989001768656254137","seed":7232138810392848772980434083747334711711477329722253798827989001768656254137,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/212.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 80317845877 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5\n","UVM_INFO @ 82573953875 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5\n","UVM_INFO @ 83824721158 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5\n","UVM_INFO @ 83970407881 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5\n"]}]}},"passed":1243,"total":1320,"percent":94.16666666666667}