{"block":{"name":"pattgen","variant":null,"commit":"21f062eb67c8749fec263739cd0f1eea14560a15","commit_short":"21f062e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/21f062eb67c8749fec263739cd0f1eea14560a15","revision_info":"GitHub Revision: [`21f062e`](https://github.com/lowrisc/opentitan/tree/21f062eb67c8749fec263739cd0f1eea14560a15)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-23T11:52:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":3.0,"sim_time":593.130646,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":15.650397000000002,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.263952,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":5.0,"sim_time":282.420288,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":46.47262,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":26.531734,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.263952,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":46.47262,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3601.0,"sim_time":0.0,"passed":25,"total":50,"percent":50.0}},"passed":25,"total":50,"percent":50.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":73.0,"sim_time":2743.292545,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":36.051646,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10801.0,"sim_time":0.0,"passed":19,"total":50,"percent":38.0}},"passed":19,"total":50,"percent":38.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":78.386461,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":15.571288000000001,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":86.256089,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":86.256089,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":15.650397000000002,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.263952,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":46.47262,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":61.808555,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":2.0,"sim_time":15.650397000000002,"passed":5,"total":5,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.263952,"passed":20,"total":20,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":46.47262,"passed":5,"total":5,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":61.808555,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":314,"total":370,"percent":84.86486486486487},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":146.49400899999998,"passed":20,"total":20,"percent":100.0},"pattgen_sec_cm":{"max_time":1.0,"sim_time":37.940713,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":146.49400899999998,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":132.0,"sim_time":6977.996593000001,"passed":2,"total":50,"percent":4.0}},"passed":2,"total":50,"percent":4.0}},"passed":2,"total":50,"percent":4.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":228.0,"sim_time":10008.125915999999,"passed":40,"total":50,"percent":80.0}},"passed":40,"total":50,"percent":80.0}},"passed":40,"total":50,"percent":80.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":98.78,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Job timed out after * minutes":[{"name":"pattgen_perf","qual_name":"0.pattgen_perf.10292664804112933496542032108444619252233489198652300100636275365516411825879","seed":10292664804112933496542032108444619252233489198652300100636275365516411825879,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"0.pattgen_stress_all.27365812504564642118682815790652006713247792975551761241548711726825544839525","seed":27365812504564642118682815790652006713247792975551761241548711726825544839525,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"2.pattgen_perf.110500170921448654862772545409414357841231217124280849988881840931940346718917","seed":110500170921448654862772545409414357841231217124280849988881840931940346718917,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"3.pattgen_perf.21107394313701062252119264599226990099534174669361284992155424021695010297342","seed":21107394313701062252119264599226990099534174669361284992155424021695010297342,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"5.pattgen_perf.103519440323529907973770396547921686612245916640210655135771464748233238871221","seed":103519440323529907973770396547921686612245916640210655135771464748233238871221,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"5.pattgen_stress_all.61689027839491184890794892520937667094935379261594967274012482401156451414657","seed":61689027839491184890794892520937667094935379261594967274012482401156451414657,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"7.pattgen_perf.115178688491909590990076533013388395793931188899677024688711462812412999664539","seed":115178688491909590990076533013388395793931188899677024688711462812412999664539,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.77664379092099245247184540795451691356315961774076603852441095318940419643871","seed":77664379092099245247184540795451691356315961774076603852441095318940419643871,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"15.pattgen_perf.72589715669728174162874484139939480298878950664454762216080878834431630583238","seed":72589715669728174162874484139939480298878950664454762216080878834431630583238,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"17.pattgen_stress_all.39420015680248797244727263380351373516407459073213106999324799683254674973794","seed":39420015680248797244727263380351373516407459073213106999324799683254674973794,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"20.pattgen_perf.105475264432611677732238565896840235069130558643067830338986261394926471693929","seed":105475264432611677732238565896840235069130558643067830338986261394926471693929,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.101636899079973333663005469547072983664792542519963897714842455254802321533305","seed":101636899079973333663005469547072983664792542519963897714842455254802321533305,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"25.pattgen_stress_all.65572905610603254017432793740460666920892607560893600150569539961558897738133","seed":65572905610603254017432793740460666920892607560893600150569539961558897738133,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"28.pattgen_stress_all.11958509174465533334168026053886642446518549753927350714904035411221464821957","seed":11958509174465533334168026053886642446518549753927350714904035411221464821957,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"31.pattgen_perf.44343284386210111737558367912632095995600452669651700010971882913074016419883","seed":44343284386210111737558367912632095995600452669651700010971882913074016419883,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"35.pattgen_perf.6218035121662944543584471304045355889070778941032310434931619577924663965615","seed":6218035121662944543584471304045355889070778941032310434931619577924663965615,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"35.pattgen_stress_all.22880007270853918033776722353137198036750942721230020799488059295895706076696","seed":22880007270853918033776722353137198036750942721230020799488059295895706076696,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"40.pattgen_perf.2965852812735285496137026309299604408625556027089109216787389569002612817220","seed":2965852812735285496137026309299604408625556027089109216787389569002612817220,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"42.pattgen_perf.7482219961353300617345674335647878706930627347046292454504866556021143348935","seed":7482219961353300617345674335647878706930627347046292454504866556021143348935,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"49.pattgen_stress_all.108558964671095238053942277449615722963386793006736252574931497442858128236809","seed":108558964671095238053942277449615722963386793006736252574931497442858128236809,"line":null,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_stress_all/latest/run.log","log_context":[]}],"UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.74208275523922642666460010744715693661137589357515054480183666947741839582091","seed":74208275523922642666460010744715693661137589357515054480183666947741839582091,"line":184,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2989167050 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2989167050 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 2989367050 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.108117791367871806310227790058133346280021752312474805705860052370656573707153","seed":108117791367871806310227790058133346280021752312474805705860052370656573707153,"line":158,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1492505829 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1492505829 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1492705829 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.1218602117200240339816493827391647968829621442376126944094725758672077252988","seed":1218602117200240339816493827391647968829621442376126944094725758672077252988,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 535487536 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 535487536 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 535687536 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.65237938236493704671110649863187159049877206420896844328711987332466453991699","seed":65237938236493704671110649863187159049877206420896844328711987332466453991699,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 134685975 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 134685975 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 134758894 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.104345657667212255749637324669411505193396967368148443168355934088109012972448","seed":104345657667212255749637324669411505193396967368148443168355934088109012972448,"line":147,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4306333605 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4306333605 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 4306533605 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.27090243388892201702577753237022929242074735386036868777869733322580716026590","seed":27090243388892201702577753237022929242074735386036868777869733322580716026590,"line":163,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1425380354 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1425380354 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1425750724 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.11833344412416238852741965385665995841249113494517110126360440928310504863833","seed":11833344412416238852741965385665995841249113494517110126360440928310504863833,"line":293,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1511272345 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1511272345 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 1511376515 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.29788255656140756381946277361497187695019458933706233051719464481647155113302","seed":29788255656140756381946277361497187695019458933706233051719464481647155113302,"line":154,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1422469876 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1422469876 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1422907376 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.46187724443637324184971208709015759434592329867604214998124333117996617111569","seed":46187724443637324184971208709015759434592329867604214998124333117996617111569,"line":119,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 771191004 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 771191004 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 771494034 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.21404727728803116288334111073680446067740892343160062314419470296792843632455","seed":21404727728803116288334111073680446067740892343160062314419470296792843632455,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1561124556 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1561124556 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1561165372 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.46760610405019536753575874934229971551277977477974752790418451919230794976763","seed":46760610405019536753575874934229971551277977477974752790418451919230794976763,"line":153,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4431606490 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4431606490 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 4431939826 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.95957174359014128640963393384698577877671252187794933407836648825850674236489","seed":95957174359014128640963393384698577877671252187794933407836648825850674236489,"line":122,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 954622816 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 954622816 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 954777985 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.56734958831126895567457613847218872644500178404722005847854844963195416855571","seed":56734958831126895567457613847218872644500178404722005847854844963195416855571,"line":122,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 949774314 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 949774314 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 949889700 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.33498690617419094720546796258680276752826821591220084480569999711990984096016","seed":33498690617419094720546796258680276752826821591220084480569999711990984096016,"line":143,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3276763123 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3276763123 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3276935538 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.50387804696972487154452188843590003448777672675766027347462344582564362177006","seed":50387804696972487154452188843590003448777672675766027347462344582564362177006,"line":135,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2143630544 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2143630544 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2143990544 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.7583995086345076106600600223593633871633549740327747169104798864557345272039","seed":7583995086345076106600600223593633871633549740327747169104798864557345272039,"line":119,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2722381290 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2722381290 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2722468246 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.112339880641093126380396830345233876410907873674547754355083320857728942768799","seed":112339880641093126380396830345233876410907873674547754355083320857728942768799,"line":123,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 461433459 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 461433459 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 461516795 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.7498365561014162606334412065476695409363271393116050237299128940532994640201","seed":7498365561014162606334412065476695409363271393116050237299128940532994640201,"line":227,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2351833629 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2351833629 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 2351874445 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.41512162494231030176438196563609430677106820493282915274666719516268750134138","seed":41512162494231030176438196563609430677106820493282915274666719516268750134138,"line":255,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2202113733 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2202113733 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2202134567 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.797906772602127050218109478019124282965552799249971949039709153718590698052","seed":797906772602127050218109478019124282965552799249971949039709153718590698052,"line":238,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3270524187 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3270524187 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 3270644187 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.10033427317946952452900967746265175901639591537815105096067107247382639166202","seed":10033427317946952452900967746265175901639591537815105096067107247382639166202,"line":126,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 545577535 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 545577535 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 545744199 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.62887512552275418170619528849310720907164561364533692647337754407027306229340","seed":62887512552275418170619528849310720907164561364533692647337754407027306229340,"line":131,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 520999392 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 520999392 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 521055732 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.95959071640630054220665724575011910416422683455940832509328801488935319358161","seed":95959071640630054220665724575011910416422683455940832509328801488935319358161,"line":114,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1655747958 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1655747958 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1656547958 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.43710960051281898507085026725754096229779485417783698385999136105252765693200","seed":43710960051281898507085026725754096229779485417783698385999136105252765693200,"line":122,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2792997392 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2792997392 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2793071466 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.92268258958523294132811043639064936633079599979512546082045522460473781693644","seed":92268258958523294132811043639064936633079599979512546082045522460473781693644,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2529367477 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2529367477 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2529626736 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.22054913653464792331089417654775183521347851496274672744124353508302699801465","seed":22054913653464792331089417654775183521347851496274672744124353508302699801465,"line":115,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1778701155 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1778701155 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1779048979 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.37407007597262641440426465340520014880990289367237450767517528563170826680645","seed":37407007597262641440426465340520014880990289367237450767517528563170826680645,"line":261,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1900965124 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1900965124 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 1901069294 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.90266584304741570656297318901018600593156621692642909225634680656483768683855","seed":90266584304741570656297318901018600593156621692642909225634680656483768683855,"line":222,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1072479092 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1072479092 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1072552011 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.66474784804829350499768418955281133659285350895980011223064599689690489526550","seed":66474784804829350499768418955281133659285350895980011223064599689690489526550,"line":242,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 286628085 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 286628085 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 286668901 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.7593807590520684398597357728567618332809255255501005641580062500950076341020","seed":7593807590520684398597357728567618332809255255501005641580062500950076341020,"line":118,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 899870455 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 899870455 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 899891289 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.26003529255321143985331822892446412784874877655029544752768731463608800178284","seed":26003529255321143985331822892446412784874877655029544752768731463608800178284,"line":289,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3518826849 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3518826849 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 3518918685 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.73809574803512064411213300593016115294229778824730166214217526175124581975427","seed":73809574803512064411213300593016115294229778824730166214217526175124581975427,"line":240,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2477785074 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2477785074 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2477878827 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.56713316735538163923949463555881143338299515709711540472042622977633508472139","seed":56713316735538163923949463555881143338299515709711540472042622977633508472139,"line":246,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 426728668 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 426728668 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 426771680 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.87366632662892088818747974716612211986417208905390233868655732420089831702765","seed":87366632662892088818747974716612211986417208905390233868655732420089831702765,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 443811928 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 443811928 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 443978596 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.21689490848302665344118825216863834479131480353704864073626655097721149013182","seed":21689490848302665344118825216863834479131480353704864073626655097721149013182,"line":183,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2591081029 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2591081029 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 2591259599 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.94092689981093379200903232746534440323204844141359990847784622304805592505289","seed":94092689981093379200903232746534440323204844141359990847784622304805592505289,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1738160762 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1738160762 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1739827432 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.38383163064118064594064127968479654690253618135638216940599556247138964187743","seed":38383163064118064594064127968479654690253618135638216940599556247138964187743,"line":128,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1239664807 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1239664807 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1239725782 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.67288191563150528456643053084363313134120202758946161227833141122707717519794","seed":67288191563150528456643053084363313134120202758946161227833141122707717519794,"line":203,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 511986228 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 511986228 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 512017479 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.111967648184934617822940558896666508041547199444205306486673659340406430731162","seed":111967648184934617822940558896666508041547199444205306486673659340406430731162,"line":283,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 11807798991 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 11807798991 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 11808146815 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.78410249195735079647061444171973868040956796267357075228136760425975353207566","seed":78410249195735079647061444171973868040956796267357075228136760425975353207566,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 211426337 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 211426337 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 211466337 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.28426328548158770374162479491874001858765876715071588950102463683859346062627","seed":28426328548158770374162479491874001858765876715071588950102463683859346062627,"line":114,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 449211327 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 449211327 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 449377991 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.37507529420857860880013918186057719659522418610664152001329616338823810626629","seed":37507529420857860880013918186057719659522418610664152001329616338823810626629,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 223640490 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 223640490 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 223723822 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.104338213252475229111929833895876746582932952464871683516706921842678894733121","seed":104338213252475229111929833895876746582932952464871683516706921842678894733121,"line":157,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2386118790 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2386118790 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 2386285458 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.69450062877807790499093707480995760682296446283602539475426168143914912190181","seed":69450062877807790499093707480995760682296446283602539475426168143914912190181,"line":205,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4278169597 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4278169597 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 4278290809 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.87958176978479549082173681309610838989152119298309938710751431837903379154128","seed":87958176978479549082173681309610838989152119298309938710751431837903379154128,"line":147,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4353387559 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4353387559 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 4353751199 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.11504900651598157903047842008003712564450096407396370793044545651108991441978","seed":11504900651598157903047842008003712564450096407396370793044545651108991441978,"line":113,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 474848587 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 474848587 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 475152933 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)":[{"name":"pattgen_inactive_level","qual_name":"1.pattgen_inactive_level.57890552986424873571484668605656565885075156323546744990919810894538617314768","seed":57890552986424873571484668605656565885075156323546744990919810894538617314768,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10036269393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"39.pattgen_inactive_level.90857240302525071768735129478629970702555698330590493194814506761123527813205","seed":90857240302525071768735129478629970702555698330590493194814506761123527813205,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10015698424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"3.pattgen_stress_all.115547977225462862606489701387212641929932944977931082774475004967990508463217","seed":115547977225462862606489701387212641929932944977931082774475004967990508463217,"line":132,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11431\n"]},{"name":"pattgen_stress_all","qual_name":"4.pattgen_stress_all.80801235973960044319857263043048722642695740287397288683876416184455574986993","seed":80801235973960044319857263043048722642695740287397288683876416184455574986993,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11331\n"]},{"name":"pattgen_stress_all","qual_name":"7.pattgen_stress_all.108936115999975532858354325469042549265517515667694738690338080790635440992967","seed":108936115999975532858354325469042549265517515667694738690338080790635440992967,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11241\n"]},{"name":"pattgen_stress_all","qual_name":"8.pattgen_stress_all.13300076230331632106331396602927079543996888530677017336303710914938662366843","seed":13300076230331632106331396602927079543996888530677017336303710914938662366843,"line":150,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11317\n"]},{"name":"pattgen_stress_all","qual_name":"9.pattgen_stress_all.9685031529011303704596772157527574912871901847335239176375509741379057813272","seed":9685031529011303704596772157527574912871901847335239176375509741379057813272,"line":149,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @60974\n"]},{"name":"pattgen_stress_all","qual_name":"10.pattgen_stress_all.94803632653828512854423253900891224403853634960297881046148368091529292100719","seed":94803632653828512854423253900891224403853634960297881046148368091529292100719,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_stress_all/latest/run.log","log_context":["----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @11300\n"]},{"name":"pattgen_stress_all","qual_name":"11.pattgen_stress_all.37767303659108934805071891645131114554786184746162339262616840071254368840897","seed":37767303659108934805071891645131114554786184746162339262616840071254368840897,"line":146,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11298\n"]},{"name":"pattgen_stress_all","qual_name":"14.pattgen_stress_all.80538673040621354979760249135341939385281173531177560568241480368408561899625","seed":80538673040621354979760249135341939385281173531177560568241480368408561899625,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11233\n"]},{"name":"pattgen_stress_all","qual_name":"19.pattgen_stress_all.2982049119754465347776315028715589757463453415553375728583946362578330738150","seed":2982049119754465347776315028715589757463453415553375728583946362578330738150,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11325\n"]},{"name":"pattgen_stress_all","qual_name":"20.pattgen_stress_all.23523978413832720292207479885288330490475288133221831253800452178589030425715","seed":23523978413832720292207479885288330490475288133221831253800452178589030425715,"line":136,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_stress_all/latest/run.log","log_context":["-------------------------------------\n","Name       Type          Size  Value \n","-------------------------------------\n","exp_item   pattgen_item  -     @11355\n"]},{"name":"pattgen_stress_all","qual_name":"24.pattgen_stress_all.22584274678934405096602123547168706732451169580509048437394704069733310795236","seed":22584274678934405096602123547168706732451169580509048437394704069733310795236,"line":132,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/24.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11374\n"]},{"name":"pattgen_stress_all","qual_name":"26.pattgen_stress_all.33285580027962813291177445245612799377818342228455583088997655159939392314149","seed":33285580027962813291177445245612799377818342228455583088997655159939392314149,"line":133,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11307\n"]},{"name":"pattgen_stress_all","qual_name":"27.pattgen_stress_all.114088419365158429839254899465824441022872525911495070695648193466223898423039","seed":114088419365158429839254899465824441022872525911495070695648193466223898423039,"line":149,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/27.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11313\n"]},{"name":"pattgen_stress_all","qual_name":"30.pattgen_stress_all.69181441186586056888156653221417457601772824061906761865129058368297871444560","seed":69181441186586056888156653221417457601772824061906761865129058368297871444560,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11253\n"]},{"name":"pattgen_stress_all","qual_name":"31.pattgen_stress_all.72713321719590230686912573862113769989651823904491032895962917193448448233929","seed":72713321719590230686912573862113769989651823904491032895962917193448448233929,"line":157,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11300\n"]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.24929975848657795507341115743961555448859830910884442228920640345329498449916","seed":24929975848657795507341115743961555448859830910884442228920640345329498449916,"line":151,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11352\n"]},{"name":"pattgen_stress_all","qual_name":"36.pattgen_stress_all.35277982816085792894107769585976643524885983147204859552549141029566882587978","seed":35277982816085792894107769585976643524885983147204859552549141029566882587978,"line":140,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11378\n"]},{"name":"pattgen_stress_all","qual_name":"37.pattgen_stress_all.2013876800412285153974957501004276038741162948684385805312845179515865020945","seed":2013876800412285153974957501004276038741162948684385805312845179515865020945,"line":160,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11357\n"]},{"name":"pattgen_stress_all","qual_name":"38.pattgen_stress_all.15261587757328713175814332727567928193304065522816193419004705043724844521338","seed":15261587757328713175814332727567928193304065522816193419004705043724844521338,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11263\n"]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.62618216971332458664272557964307068050874424474737990368711700758513687513831","seed":62618216971332458664272557964307068050874424474737990368711700758513687513831,"line":144,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11329\n"]},{"name":"pattgen_stress_all","qual_name":"45.pattgen_stress_all.67740564749194001501051056736849861958861437725492196281678197082386076094","seed":67740564749194001501051056736849861958861437725492196281678197082386076094,"line":137,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11210\n"]},{"name":"pattgen_stress_all","qual_name":"47.pattgen_stress_all.46824721915057915332187831762972878821379069771687613458833809787179845616091","seed":46824721915057915332187831762972878821379069771687613458833809787179845616091,"line":148,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11395\n"]},{"name":"pattgen_stress_all","qual_name":"48.pattgen_stress_all.108493678981013677594133732187839151407061665000001758059966388788502996808038","seed":108493678981013677594133732187839151407061665000001758059966388788502996808038,"line":125,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/48.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11324\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20)":[{"name":"pattgen_inactive_level","qual_name":"5.pattgen_inactive_level.109440755551889932812445297163840681353843764496331003709138168522913948101809","seed":109440755551889932812445297163840681353843764496331003709138168522913948101809,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10019651766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"7.pattgen_inactive_level.28858601327799943661886232316395760484461498282465393564766617012800263674907","seed":28858601327799943661886232316395760484461498282465393564766617012800263674907,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10030030951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"9.pattgen_perf.101980940381297723496781284409828344673481287375342846342050624852948454725187","seed":101980940381297723496781284409828344673481287375342846342050624852948454725187,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"13.pattgen_perf.110551400852524353460910810872536304208196384712578299789076553983321990503418","seed":110551400852524353460910810872536304208196384712578299789076553983321990503418,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"14.pattgen_perf.46028307837924281034424468795834090174184469756024447515727067541144746735838","seed":46028307837924281034424468795834090174184469756024447515727067541144746735838,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/14.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"17.pattgen_perf.63807466735089311067215402775038499703881680900907574490507174291535229466511","seed":63807466735089311067215402775038499703881680900907574490507174291535229466511,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"18.pattgen_perf.94464058750845092868817817301824520774940652472174444563072883223454049106754","seed":94464058750845092868817817301824520774940652472174444563072883223454049106754,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"21.pattgen_perf.106623938542199843314797720391166933878021525812911690529736590004542872666645","seed":106623938542199843314797720391166933878021525812911690529736590004542872666645,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/21.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"22.pattgen_perf.85810202381158334049651818600491718540821727768419807561570530656893439652814","seed":85810202381158334049651818600491718540821727768419807561570530656893439652814,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"26.pattgen_perf.17191363744795744061036895883954024902556027066991165787744116681653953530424","seed":17191363744795744061036895883954024902556027066991165787744116681653953530424,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"29.pattgen_perf.70496239451531540243920550634060119337330248779741932452235422463589180658150","seed":70496239451531540243920550634060119337330248779741932452235422463589180658150,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"36.pattgen_perf.107448281433627280316299112031374981464605119263853721367362659879779526261359","seed":107448281433627280316299112031374981464605119263853721367362659879779526261359,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/36.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"39.pattgen_perf.111020037485654318212980021129223306426301414943124290929921951860005840086421","seed":111020037485654318212980021129223306426301414943124290929921951860005840086421,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"46.pattgen_perf.3782631504010425857902793052631373364047477475279604189461410555421428798284","seed":3782631504010425857902793052631373364047477475279604189461410555421428798284,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"47.pattgen_perf.47474756359739664835410676582797631270926693945956999735734748676370688696713","seed":47474756359739664835410676582797631270926693945956999735734748676370688696713,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)":[{"name":"pattgen_inactive_level","qual_name":"15.pattgen_inactive_level.11821910775762252094619906362579948786798927303571603766326831911904096658733","seed":11821910775762252094619906362579948786798927303571603766326831911904096658733,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10201548249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.80514855773589570170452233709200005124294575475416412817015265462799639176022","seed":80514855773589570170452233709200005124294575475416412817015265462799639176022,"line":130,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.48252732310045126977747910259804913095556682565206696356934794811410805994282","seed":48252732310045126977747910259804913095556682565206696356934794811410805994282,"line":131,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)":[{"name":"pattgen_inactive_level","qual_name":"18.pattgen_inactive_level.7520701214170845620071122527792096344231973718628355724121934925884496948226","seed":7520701214170845620071122527792096344231973718628355724121934925884496948226,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10313772880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)":[{"name":"pattgen_inactive_level","qual_name":"20.pattgen_inactive_level.108946856919684353572177299022826599714368479162471237515002797141877993297008","seed":108946856919684353572177299022826599714368479162471237515002797141877993297008,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10008125916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"25.pattgen_inactive_level.19915655407174619549134425023370595612937968938070972144714406476015143039711","seed":19915655407174619549134425023370595612937968938070972144714406476015143039711,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10141078961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"32.pattgen_inactive_level.63270489797984154104879626193906865253344617690200833452646921402978406594970","seed":63270489797984154104879626193906865253344617690200833452646921402978406594970,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10017063076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"46.pattgen_inactive_level.104973659461080414400100530327582094805548840989384630065010604527119997270776","seed":104973659461080414400100530327582094805548840989384630065010604527119997270776,"line":99,"log_path":"/nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10004989825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":456,"total":570,"percent":80.0}