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percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":31.13,"sim_time":13483.572684,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":31.13,"sim_time":13483.572684,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":31.13,"sim_time":13483.572684,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":39.82,"sim_time":12043.414189,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":99.08,"sim_time":48376.119264,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":99.08,"sim_time":48376.119264,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":99.08,"sim_time":48376.119264,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":43.6,"sim_time":4998.148972,"passed":50,"total":50,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":12.55,"sim_time":1332.2262039999998,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":99.08,"sim_time":48376.119264,"passed":50,"total":50,"percent":100.0},"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":336.87,"sim_time":270929.09886699996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":25.82,"sim_time":6167.602489,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":25.82,"sim_time":6167.602489,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":502.73999999999995,"sim_time":169863.293304,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":523.81,"sim_time":86386.993301,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":647.76,"sim_time":912282.501418,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.2,"sim_time":17.944371999999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.2,"sim_time":20.057391,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":4.86,"sim_time":495.311133,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":4.86,"sim_time":495.311133,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.69,"sim_time":22.535591,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":3.3,"sim_time":113.434806,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":18.93,"sim_time":1037.839693,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":5.05,"sim_time":426.099812,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.69,"sim_time":22.535591,"passed":5,"total":5,"percent":100.0},"spi_device_csr_rw":{"max_time":3.3,"sim_time":113.434806,"passed":20,"total":20,"percent":100.0},"spi_device_csr_aliasing":{"max_time":18.93,"sim_time":1037.839693,"passed":5,"total":5,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":5.05,"sim_time":426.099812,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1019,"total":1041,"percent":97.8866474543708},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.69,"sim_time":111.718075,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":20.27,"sim_time":989.777236,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":20.27,"sim_time":989.777236,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":333.77,"sim_time":112815.55676899999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.9,"branch":98.3,"condition_expression":96.55,"toggle":83.54,"fsm":89.36},"assertion":95.51,"functional":99.26},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.54731344309480554819220743529790181598633625499124264418778701081925481387898","seed":54731344309480554819220743529790181598633625499124264418778701081925481387898,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5817271 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5817271 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[991])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.80699695894886337493381938395628412893810406692349802859374533760164789560227","seed":80699695894886337493381938395628412893810406692349802859374533760164789560227,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4919597 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4919597 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.11598764491339498761121084823171340352312144491107388629956231495895196735264","seed":11598764491339498761121084823171340352312144491107388629956231495895196735264,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4124461 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4124461 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.54029450910215262887317347131893865984009815177038493309995533955671644709036","seed":54029450910215262887317347131893865984009815177038493309995533955671644709036,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4300884 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4300884 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.92808819145468508011541888733394550385862874608741932305389167971443347689689","seed":92808819145468508011541888733394550385862874608741932305389167971443347689689,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    876806 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    876806 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[902])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.112709295587980952534068884496885088952400336760366013116586353325955880325945","seed":112709295587980952534068884496885088952400336760366013116586353325955880325945,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4972615 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4972615 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.34117751868059575481817159619003740879878688731481705031671153717308350676523","seed":34117751868059575481817159619003740879878688731481705031671153717308350676523,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1179804 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1179804 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[999])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.9816657151713886446308050777834094778278607661761285621254637206537074371764","seed":9816657151713886446308050777834094778278607661761285621254637206537074371764,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4176788 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4176788 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.23481531390549951313937319564697277779302787155306709801244203836996253868918","seed":23481531390549951313937319564697277779302787155306709801244203836996253868918,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   9897795 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   9897795 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[904])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.15693747391848785291236370420807831074726157718668042047335602675464464291980","seed":15693747391848785291236370420807831074726157718668042047335602675464464291980,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2395849 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2395849 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.59808822818768072078725767554886067888134110160701061027250766382225528692331","seed":59808822818768072078725767554886067888134110160701061027250766382225528692331,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1042435 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1042435 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[964])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.4863804244201109578326018092846029278931186021866196441710931202773838244199","seed":4863804244201109578326018092846029278931186021866196441710931202773838244199,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  12591726 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  12591726 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1003])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.56010374798587808992938454790110312290032798970003240267218407156208541479836","seed":56010374798587808992938454790110312290032798970003240267218407156208541479836,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4526682 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4526682 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[928])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.22370745024810157632633584578011720843482287912609819817365846993344847143290","seed":22370745024810157632633584578011720843482287912609819817365846993344847143290,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3545185 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3545185 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.68007837140540053635560635795849272186149887949407383466989854927510420347092","seed":68007837140540053635560635795849272186149887949407383466989854927510420347092,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4205907 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4205907 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[956])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.30595753212198973414294176375526209483370947242489932795403885359088948021246","seed":30595753212198973414294176375526209483370947242489932795403885359088948021246,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1105642 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1105642 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[948])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.14924193003145442536427336437572210262854875074859817177834672356201472152185","seed":14924193003145442536427336437572210262854875074859817177834672356201472152185,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4621560 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4621560 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[983])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.43044573451410248125669581041224709353866348808702272687451229983330430534088","seed":43044573451410248125669581041224709353866348808702272687451229983330430534088,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    893382 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    893382 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.6322727528767907337768886798527116034768054926775786885335234911384288536916","seed":6322727528767907337768886798527116034768054926775786885335234911384288536916,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1653263 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1653263 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.21751666800189612516653893525998222206902855506940029985072853577418821278167","seed":21751666800189612516653893525998222206902855506940029985072853577418821278167,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1863482 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1863482 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[963])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.10259642802842843737696605057636225806823250469129572693135382331769377643942","seed":10259642802842843737696605057636225806823250469129572693135382331769377643942,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1197563 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbb7f19 [101110110111111100011001] vs 0x0 [0]) \n","UVM_ERROR @   1214563 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x71a05c [11100011010000001011100] vs 0x0 [0]) \n","UVM_ERROR @   1304563 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe7fd0 [111111100111111111010000] vs 0x0 [0]) \n","UVM_ERROR @   1322563 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc37d8f [110000110111110110001111] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_stress_all","qual_name":"23.spi_device_stress_all.24474349807923396085839789632608398999363259799886115629566889756926074842788","seed":24474349807923396085839789632608398999363259799886115629566889756926074842788,"line":155,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest/run.log","log_context":["tl_ul_fuzzy_flash_status_q[i] = 0x48d428\n","tl_ul_fuzzy_flash_status_q[i] = 0x4ba700\n","tl_ul_fuzzy_flash_status_q[i] = 0x4ba700\n","UVM_INFO @ 6213267774 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/14\n"]}]}},"passed":1129,"total":1151,"percent":98.08861859252823}