{"block":{"name":"uart","variant":null,"commit":"21f062eb67c8749fec263739cd0f1eea14560a15","commit_short":"21f062e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/21f062eb67c8749fec263739cd0f1eea14560a15","revision_info":"GitHub Revision: [`21f062e`](https://github.com/lowrisc/opentitan/tree/21f062eb67c8749fec263739cd0f1eea14560a15)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-23T11:52:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":19.68,"sim_time":5884.771051,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.44,"sim_time":1077.031241,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.99,"sim_time":48.751446,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.5,"sim_time":392.894362,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.15,"sim_time":31.514331,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.71,"sim_time":92.853364,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.99,"sim_time":48.751446,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.15,"sim_time":31.514331,"passed":5,"total":5,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":105,"total":105,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":227.62,"sim_time":302862.732064,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":19.68,"sim_time":5884.771051,"passed":50,"total":50,"percent":100.0},"uart_tx_rx":{"max_time":227.62,"sim_time":302862.732064,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":440.94,"sim_time":307972.005352,"passed":50,"total":50,"percent":100.0},"uart_rx_parity_err":{"max_time":315.7,"sim_time":151372.184467,"passed":49,"total":50,"percent":98.0}},"passed":99,"total":100,"percent":99.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":227.62,"sim_time":302862.732064,"passed":50,"total":50,"percent":100.0},"uart_intr":{"max_time":440.94,"sim_time":307972.005352,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":334.64,"sim_time":182194.136731,"passed":49,"total":50,"percent":98.0}},"passed":49,"total":50,"percent":98.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":447.29,"sim_time":307960.584719,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":373.94,"sim_time":324042.00202899997,"passed":299,"total":300,"percent":99.66666666666667}},"passed":299,"total":300,"percent":99.66666666666667},"rx_frame_err":{"tests":{"uart_intr":{"max_time":440.94,"sim_time":307972.005352,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":440.94,"sim_time":307972.005352,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":440.94,"sim_time":307972.005352,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":1106.87,"sim_time":32516.675393,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":28.85,"sim_time":10915.265415999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":28.85,"sim_time":10915.265415999998,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":65.89,"sim_time":33309.500025,"passed":10,"total":50,"percent":20.0}},"passed":10,"total":50,"percent":20.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":64.83,"sim_time":44310.264321,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":34.77,"sim_time":11926.242458,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":49.53,"sim_time":6609.629563,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":1061.35,"sim_time":143448.426271,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":2218.23,"sim_time":447568.927844,"passed":35,"total":50,"percent":70.0}},"passed":35,"total":50,"percent":70.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.94,"sim_time":14.14063,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.97,"sim_time":47.699245000000005,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.75,"sim_time":490.424031,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.75,"sim_time":490.424031,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.44,"sim_time":1077.031241,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.99,"sim_time":48.751446,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.15,"sim_time":31.514331,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.16,"sim_time":32.606397,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.44,"sim_time":1077.031241,"passed":5,"total":5,"percent":100.0},"uart_csr_rw":{"max_time":0.99,"sim_time":48.751446,"passed":20,"total":20,"percent":100.0},"uart_csr_aliasing":{"max_time":1.15,"sim_time":31.514331,"passed":5,"total":5,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.16,"sim_time":32.606397,"passed":20,"total":20,"percent":100.0}},"passed":50,"total":50,"percent":100.0}},"passed":1112,"total":1170,"percent":95.04273504273505},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.32,"sim_time":70.063945,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.8,"sim_time":104.190827,"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.8,"sim_time":104.190827,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":78.8,"sim_time":2822.368282,"passed":82,"total":100,"percent":82.0}},"passed":82,"total":100,"percent":82.0}},"passed":82,"total":100,"percent":82.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":91.55,"fsm":null},"assertion":98.85,"functional":99.53},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_fifo_full","qual_name":"0.uart_fifo_full.68106849039572852088989770252419783960493884366918296116219060683143675186117","seed":68106849039572852088989770252419783960493884366918296116219060683143675186117,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_fifo_full/latest/run.log","log_context":["UVM_INFO @ 65533243447 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 7/9\n","UVM_INFO @ 98792361023 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 8/9\n","UVM_INFO @ 107654415433 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_full_vseq] finished run 9/9\n","UVM_INFO @ 107768012658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"60.uart_stress_all_with_rand_reset.83641244387205026747273322148427875927875662081114506372475887173385572777120","seed":83641244387205026747273322148427875927875662081114506372475887173385572777120,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  28638012 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @  28718012 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 1/10\n"]},{"name":"uart_fifo_reset","qual_name":"206.uart_fifo_reset.9274103144856299914572482767925969517058588529245906750647184917493642468229","seed":9274103144856299914572482767925969517058588529245906750647184917493642468229,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/206.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 78759327577 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/9\n","UVM_INFO @ 79015079623 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/9\n","UVM_INFO @ 80282589763 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/9\n","UVM_INFO @ 81204138802 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/9\n"]}],"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.92610498338961080668662128175788248928132683851141346150751414700729908354795","seed":92610498338961080668662128175788248928132683851141346150751414700729908354795,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3014672640 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4160621080 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: RxWatermark\n","UVM_ERROR @ 4220454516 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (0 [0x0] vs 1 [0x1]) Interrupt: RxWatermark\n","UVM_ERROR @ 4240629229 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.107885312351694837595316496096616534571947628382940105638195225168788929031589","seed":107885312351694837595316496096616534571947628382940105638195225168788929031589,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 12623607245 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12623967245 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12624327245 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 12624687245 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.98097129001349573369880076560102846607723892276714927420210742139071548901905","seed":98097129001349573369880076560102846607723892276714927420210742139071548901905,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1982559819 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2064639819 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2064639819 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 2192039819 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.79846013272450485772278657571457084928746829434095337015310282330240035213403","seed":79846013272450485772278657571457084928746829434095337015310282330240035213403,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2264569923 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2266288728 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2267163756 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2267976282 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"11.uart_noise_filter.20679069951148908844209225626828597663539916904656608455094364391901795521497","seed":20679069951148908844209225626828597663539916904656608455094364391901795521497,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/11.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 300022733 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 439752323 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 443995562 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 444049616 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (84 [0x54] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"11.uart_stress_all.112012448900022958338471561228849416451732459478526652965972224662575038384625","seed":112012448900022958338471561228849416451732459478526652965972224662575038384625,"line":109,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/11.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 357970235516 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 358005647564 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 358005647564 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 358066236284 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all","qual_name":"12.uart_stress_all.74966404093154220715619600185061959744016786208261315734016424465968933261844","seed":74966404093154220715619600185061959744016786208261315734016424465968933261844,"line":90,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/12.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 137466154384 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 137467114384 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 137680634384 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 137680634384 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"15.uart_noise_filter.88084185562693232144122922890326913886225653379902298595350115906054413450783","seed":88084185562693232144122922890326913886225653379902298595350115906054413450783,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/15.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  28756795 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 854956795 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 863956795 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 865956795 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"17.uart_noise_filter.12376091519545245696382170355364103679230385525889275491473903191531301428393","seed":12376091519545245696382170355364103679230385525889275491473903191531301428393,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/17.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  20154247 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  20258722 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  20452747 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  20572147 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"18.uart_noise_filter.4169619388012706326856610138995074644479688967535827940349760174125686502062","seed":4169619388012706326856610138995074644479688967535827940349760174125686502062,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/18.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 8636804218 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8636804218 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 9336616408 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (1 [0x1] vs 0 [0x0]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 5\n","UVM_ERROR @ 9336673878 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (1 [0x1] vs 0 [0x0]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 5\n"]},{"name":"uart_noise_filter","qual_name":"19.uart_noise_filter.5500195032292462444879431622105260837872403271220022253798930787691717472149","seed":5500195032292462444879431622105260837872403271220022253798930787691717472149,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/19.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  72896327 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  76063000 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  92563033 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 116396414 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all","qual_name":"20.uart_stress_all.11292528189560529402392648731766781050384778416331854560288397296972985103909","seed":11292528189560529402392648731766781050384778416331854560288397296972985103909,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/20.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 8054554669 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8054992162 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8056304641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8056742134 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"23.uart_noise_filter.104870655723353711660715760449007472622988760555448922025164237865055915537404","seed":104870655723353711660715760449007472622988760555448922025164237865055915537404,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/23.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  26476897 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @  26476897 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  26680977 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @  26680977 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"26.uart_stress_all.82736684190883872369542173387062666605000451778138565560945410499824401171429","seed":82736684190883872369542173387062666605000451778138565560945410499824401171429,"line":95,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/26.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 71941088463 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71941248463 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71941448463 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71947608463 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"27.uart_noise_filter.16607214379366714816734971975050797974911475490546200495431573682026929355430","seed":16607214379366714816734971975050797974911475490546200495431573682026929355430,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/27.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 598534658 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1816099721 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1816099721 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3840292489 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"30.uart_noise_filter.55059641399739341706185878580443712932219684719088074233713964933995491751202","seed":55059641399739341706185878580443712932219684719088074233713964933995491751202,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/30.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  15258186 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  15402512 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 103771260 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 134120956 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"31.uart_noise_filter.8388022820516633549686933913166584611335953235277969173053126643148201358798","seed":8388022820516633549686933913166584611335953235277969173053126643148201358798,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/31.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  86989757 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  97401847 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 121112547 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 121112547 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"34.uart_noise_filter.112041587395185635133485761090121620569565385367885074135557642640836931997252","seed":112041587395185635133485761090121620569565385367885074135557642640836931997252,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/34.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 384313085 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 390353085 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 396443085 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 402473085 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"35.uart_noise_filter.104175289166282150144329903047818494908212405709224508393971641394839663032423","seed":104175289166282150144329903047818494908212405709224508393971641394839663032423,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/35.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1376956708 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1380211784 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1382344420 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1383364820 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"38.uart_noise_filter.63529195720918031641292472040382788208034059269430171885869028688044178831176","seed":63529195720918031641292472040382788208034059269430171885869028688044178831176,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/38.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @   6760868 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  14575090 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  18863634 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  19368775 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"39.uart_noise_filter.40798753965257373291078267042295891445608190467964311432095424912362419685453","seed":40798753965257373291078267042295891445608190467964311432095424912362419685453,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/39.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 9014106099 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 9271247818 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9271247818 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 9329559385 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3,                                 clk_pulses: 4\n"]},{"name":"uart_noise_filter","qual_name":"40.uart_noise_filter.53867819030547740417482254240700020024234076726992526939579450315384150954685","seed":53867819030547740417482254240700020024234076726992526939579450315384150954685,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18745664935 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18746581609 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18747248281 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18747831619 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all","qual_name":"40.uart_stress_all.102925943966940979764996969747158079331905162723322511958928943079783549737949","seed":102925943966940979764996969747158079331905162723322511958928943079783549737949,"line":94,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 48554905808 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 48554905808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 49004870192 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 6\n","UVM_ERROR @ 49004889800 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"41.uart_noise_filter.36451759282112943772829325250913168729968243495095841983823688488333099200251","seed":36451759282112943772829325250913168729968243495095841983823688488333099200251,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/41.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 7170537043 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 7252839837 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 7252839837 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 7271860319 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_stress_all","qual_name":"41.uart_stress_all.23115132332522806694560511977683848143334971985145109647897545995731092445314","seed":23115132332522806694560511977683848143334971985145109647897545995731092445314,"line":114,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/41.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 322013826453 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 322041786021 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 7/16\n","UVM_INFO @ 332758775304 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 8/16\n","UVM_INFO @ 334152874920 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 9/16\n"]},{"name":"uart_noise_filter","qual_name":"42.uart_noise_filter.37386197256248406567249370089533876466788990129372294589126037987339126856322","seed":37386197256248406567249370089533876466788990129372294589126037987339126856322,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3968005423 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4158062147 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 4158103383 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 4158113692 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"43.uart_stress_all.71852320645246529067599172255702152594389381667022720672797338650178314699310","seed":71852320645246529067599172255702152594389381667022720672797338650178314699310,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/43.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 19565504726 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 19667044726 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 19667074726 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n","UVM_ERROR @ 19667464726 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all","qual_name":"44.uart_stress_all.26107862357180672425371216984659839794058711373309895191367463946891700978460","seed":26107862357180672425371216984659839794058711373309895191367463946891700978460,"line":125,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 186110320472 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 186158830472 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 186158830472 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 186169310472 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"46.uart_noise_filter.97952497459438259692678707211119021147723675991916343738743082038604185807983","seed":97952497459438259692678707211119021147723675991916343738743082038604185807983,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/46.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 3406131598 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3407214940 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3408103836 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3408992732 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"48.uart_noise_filter.11264793507960276478700980694072536923249299628293856945138832122755951799945","seed":11264793507960276478700980694072536923249299628293856945138832122755951799945,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/48.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 282815788 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 386339934 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 386339934 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 431143451 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"49.uart_noise_filter.39480614297263376944137684046071795517426874826320182589510451066380568838287","seed":39480614297263376944137684046071795517426874826320182589510451066380568838287,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/49.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 49402718499 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 49402825641 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 49402932783 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 49403039925 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"51.uart_stress_all_with_rand_reset.14259810911104149696548470120592306628053295592767096078110954931027160079469","seed":14259810911104149696548470120592306628053295592767096078110954931027160079469,"line":119,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9307841412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9311841412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9313841412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9315841412 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"82.uart_stress_all_with_rand_reset.84233430902585990023947944844314393674745685930469623048108027037775587226849","seed":84233430902585990023947944844314393674745685930469623048108027037775587226849,"line":144,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10042719607 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 10148182411 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/893\n","UVM_INFO @ 10431531965 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/893\n","UVM_ERROR @ 10469917041 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 6\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"85.uart_stress_all_with_rand_reset.27644378612078907149147582626619799552818224407713256579014361631254391418936","seed":27644378612078907149147582626619799552818224407713256579014361631254391418936,"line":185,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3539473082 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3540603510 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3541733938 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3542864366 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"92.uart_stress_all_with_rand_reset.77600747789317544540530221129166383034106941607532375951094321061038606027733","seed":77600747789317544540530221129166383034106941607532375951094321061038606027733,"line":94,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1019915441 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 1023263247 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/171\n","UVM_INFO @ 1260305303 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/171\n","UVM_INFO @ 1651737737 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/171\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"96.uart_stress_all_with_rand_reset.28220878867693671442774988632235735684369377466808375313429172655833565167671","seed":28220878867693671442774988632235735684369377466808375313429172655833565167671,"line":92,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  92018042 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 120246757 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/993\n","UVM_ERROR @ 143079725 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 143079725 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n"]}],"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.19470088093894805507459770946215441528330802472600118625922594289109370336636","seed":19470088093894805507459770946215441528330802472600118625922594289109370336636,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 92208984481 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 92208984481 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 92212224481 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 11\n","UVM_ERROR @ 92212264481 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.32814473820918298529876626209958761402158888299036993813345369224957466836176","seed":32814473820918298529876626209958761402158888299036993813345369224957466836176,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1417283173 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1417283173 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1508575570 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 10\n","UVM_ERROR @ 1508617237 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"12.uart_noise_filter.46316992364520524512817363507162997233628066797554908759261805041582523590836","seed":46316992364520524512817363507162997233628066797554908759261805041582523590836,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/12.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 161529351 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 163918259 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 163918259 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 395086775 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"16.uart_noise_filter.371084276570113815154686961539863229538629429368569310570041281456110305438","seed":371084276570113815154686961539863229538629429368569310570041281456110305438,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 999801107 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1041238607 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 1405707357 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 1405707357 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n"]},{"name":"uart_noise_filter","qual_name":"21.uart_noise_filter.79086125755471565039621154657636868443682783868054598664406383559090150698029","seed":79086125755471565039621154657636868443682783868054598664406383559090150698029,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 11413505058 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 11413505058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 11517111372 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 11517575654 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (83 [0x53] vs 237 [0xed]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"22.uart_stress_all_with_rand_reset.50111208236239708114299282499799912952551400704280482899575842646577346491120","seed":50111208236239708114299282499799912952551400704280482899575842646577346491120,"line":144,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 19936353940 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19937853940 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 19937853940 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19939103940 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"24.uart_noise_filter.2299388607505853241452975712540735281963342538965269720110172835363496789770","seed":2299388607505853241452975712540735281963342538965269720110172835363496789770,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/24.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 14734305448 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 5,                                 clk_pulses: 0\n","UVM_ERROR @ 14734405448 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 14930885448 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 14930885448 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"32.uart_noise_filter.76366557475149571852868547915664178668125397252852633350218950785254654808111","seed":76366557475149571852868547915664178668125397252852633350218950785254654808111,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/32.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 14426868335 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 14426868335 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 14567497367 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 14567532251 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (65 [0x41] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"34.uart_stress_all.100156779673054131814167414076658069468077977157859620557662519436502297248920","seed":100156779673054131814167414076658069468077977157859620557662519436502297248920,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/34.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 115746893923 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 116341075147 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_INFO @ 124526728867 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 5/8\n","UVM_INFO @ 130288716139 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 6/8\n"]},{"name":"uart_noise_filter","qual_name":"36.uart_noise_filter.79933611744170528052438228400439848173901228663384347934531637762028234788176","seed":79933611744170528052438228400439848173901228663384347934531637762028234788176,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/36.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 59115900078 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 14,                                 clk_pulses: 0\n","UVM_ERROR @ 59116150076 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (202 [0xca] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 59116185790 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 59116471502 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (202 [0xca] vs 254 [0xfe]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"42.uart_stress_all.43944430151335264952281319720678734221234330049576637714491225324827026034654","seed":43944430151335264952281319720678734221234330049576637714491225324827026034654,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 1485376044 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1485376044 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1491272066 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 10\n","UVM_ERROR @ 1491282483 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"47.uart_noise_filter.70492522639850602586966065674101696396690794316793678989878665614734808554842","seed":70492522639850602586966065674101696396690794316793678989878665614734808554842,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/47.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2651946839 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2658905967 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 2658905967 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 2727231951 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.18779593243564624411469711530159485249256690004877689759906892382330804237623","seed":18779593243564624411469711530159485249256690004877689759906892382330804237623,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1605120498 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1605130599 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (10 [0xa] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1711403220 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 1711413321 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.76018853322593238394088080899188121734760961130816298959573933533199449802689","seed":76018853322593238394088080899188121734760961130816298959573933533199449802689,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18872335577 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 18872552967 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (233 [0xe9] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 18910987519 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0\n","UVM_ERROR @ 18911030997 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"10.uart_noise_filter.77532358713640675304875079382354798729286845053138375149873273665703960599025","seed":77532358713640675304875079382354798729286845053138375149873273665703960599025,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/10.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 44336664557 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 44336704557 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (66 [0x42] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 44361064557 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 44361064557 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"14.uart_stress_all_with_rand_reset.32748929645119100156349970593587503569590244753220691061031785219119119133562","seed":32748929645119100156349970593587503569590244753220691061031785219119119133562,"line":150,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2573859108 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2573899924 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 2583236584 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/537\n","UVM_INFO @ 2639756540 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/537\n"]},{"name":"uart_stress_all","qual_name":"18.uart_stress_all.69193990414852561808347849302772668276230229049883059453972240976820801869592","seed":69193990414852561808347849302772668276230229049883059453972240976820801869592,"line":95,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/18.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 47569260666 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 47569270666 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (243 [0xf3] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 47578620666 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 47578620666 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"20.uart_noise_filter.9079228311897485792261099666893423234520310805989149804980626287050041462755","seed":9079228311897485792261099666893423234520310805989149804980626287050041462755,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/20.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 25378893749 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 25378933749 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 25378973749 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 25379013749 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (208 [0xd0] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"21.uart_stress_all_with_rand_reset.28680166671659158875716788961377032183164513694835074781846504692284060605270","seed":28680166671659158875716788961377032183164513694835074781846504692284060605270,"line":180,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4426521891 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 4426561891 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 4426581891 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 4426681891 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"25.uart_stress_all.114603306437665814369469254434253632208138687690213418556215856047693543349372","seed":114603306437665814369469254434253632208138687690213418556215856047693543349372,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/25.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 43508387973 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 43508397973 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (202 [0xca] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 43508417973 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 43508427973 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"28.uart_noise_filter.109742724703964997978886863460090236163059596279951383038989000613842076670025","seed":109742724703964997978886863460090236163059596279951383038989000613842076670025,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/28.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 283972481 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 284088761 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 642486977 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 838860641 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"34.uart_stress_all_with_rand_reset.73427804345513408823737888038067963138881981211336513743124620891544996817671","seed":73427804345513408823737888038067963138881981211336513743124620891544996817671,"line":124,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6018600518 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 6018640518 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (93 [0x5d] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 6018680518 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 6018800518 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (93 [0x5d] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"37.uart_noise_filter.87035678835491021960028277382406716373224544071599251283943939471302174168826","seed":87035678835491021960028277382406716373224544071599251283943939471302174168826,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/37.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4762439536 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 4762449536 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 4762459536 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 4762539536 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"40.uart_stress_all_with_rand_reset.72216783309110787345598005505540655550227723157451786506123381376271714136494","seed":72216783309110787345598005505540655550227723157451786506123381376271714136494,"line":105,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 807932755 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 807985385 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 809311661 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 809311661 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"42.uart_stress_all_with_rand_reset.81416376287424241392673018353904241148437310028909638517013636238442100519447","seed":81416376287424241392673018353904241148437310028909638517013636238442100519447,"line":119,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1962138520 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1962201022 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 159 [0x9f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1962211439 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1962232273 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"43.uart_noise_filter.45158750852952468880591801044062803340353271689238676288167836891413263277405","seed":45158750852952468880591801044062803340353271689238676288167836891413263277405,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/43.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 8768222292 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 8768293720 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (155 [0x9b] vs 190 [0xbe]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 8768303924 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 8768385556 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (155 [0x9b] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"44.uart_noise_filter.18318413271099958230836160768332332268150107694885039532375093166398360694920","seed":18318413271099958230836160768332332268150107694885039532375093166398360694920,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/44.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 28581151390 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 28581161807 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (103 [0x67] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 28651091128 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 18,                                 clk_pulses: 0\n","UVM_ERROR @ 28651101545 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"45.uart_noise_filter.52315304313959120449233962438787480767015689999079690192111250520774764125996","seed":52315304313959120449233962438787480767015689999079690192111250520774764125996,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/45.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 8448117789 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 8448137991 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 8448148092 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 8448249102 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_stress_all","qual_name":"46.uart_stress_all.81523903879699032607170154915665024044506130950541040438437916442633355903732","seed":81523903879699032607170154915665024044506130950541040438437916442633355903732,"line":93,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/46.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 123594176193 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 123594819054 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (220 [0xdc] vs 247 [0xf7]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 123830963328 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 123830963328 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"64.uart_stress_all_with_rand_reset.29617647842984935464052158407931676373721366315833214944004933731592613856148","seed":29617647842984935464052158407931676373721366315833214944004933731592613856148,"line":148,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1920385785 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1920396202 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 125 [0x7d]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 1981721081 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/615\n","UVM_INFO @ 2029149682 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/615\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"66.uart_stress_all_with_rand_reset.71590246637384029037040446659530715888135470409424759185621173677430294297350","seed":71590246637384029037040446659530715888135470409424759185621173677430294297350,"line":161,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15098468946 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 15098531446 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (144 [0x90] vs 126 [0x7e]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 15098781446 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0\n","UVM_ERROR @ 15098968946 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxWatermark":[{"name":"uart_stress_all_with_rand_reset","qual_name":"9.uart_stress_all_with_rand_reset.72832609616360648164193029330158784121526865826021194110405476120330993237267","seed":72832609616360648164193029330158784121526865826021194110405476120330993237267,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  52647317 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark\n","UVM_ERROR @  52987317 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_ERROR @  52987317 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark\n","UVM_INFO @ 102777317 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/199\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all","qual_name":"10.uart_stress_all.51589610614675636967278265730415882916217909922100306573618100182699305039244","seed":51589610614675636967278265730415882916217909922100306573618100182699305039244,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/10.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 2254908987 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n","UVM_ERROR @ 2254908987 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr\n","UVM_ERROR @ 2261147076 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 2261147076 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"uart_rx_parity_err","qual_name":"18.uart_rx_parity_err.84143686515759181386363775331688138977408340625329024221910784126204074831362","seed":84143686515759181386363775331688138977408340625329024221910784126204074831362,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/18.uart_rx_parity_err/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1199) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"74.uart_stress_all_with_rand_reset.16365038009981166874638699080476530533457921536081047253161073145099478723542","seed":16365038009981166874638699080476530533457921536081047253161073145099478723542,"line":117,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1305577576 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 1305679616 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 3/10\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"89.uart_stress_all_with_rand_reset.38708471826355566043610245549861443112322623081413498777399922834064068068181","seed":38708471826355566043610245549861443112322623081413498777399922834064068068181,"line":96,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 12093926536 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 12094176536 ps: (cip_base_vseq.sv:1223) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Stress w/ reset is done for run 2/5\n"]}],"UVM_ERROR (cip_base_vseq.sv:1286) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"uart_stress_all_with_rand_reset","qual_name":"98.uart_stress_all_with_rand_reset.110603183048099471529361893498549417759657620403294565479908843198749592365768","seed":110603183048099471529361893498549417759657620403294565479908843198749592365768,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 599502236 ps: (cip_base_vseq.sv:1199) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 599502236 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 599504466 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2\n"]}]}},"passed":1244,"total":1320,"percent":94.24242424242425}