{"block":{"name":"uart","variant":null,"commit":"1bd5f9a0371f862b10968297092488568751b0ed","commit_short":"1bd5f9a","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed","revision_info":"GitHub Revision: [`1bd5f9a`](https://github.com/lowrisc/opentitan/tree/1bd5f9a0371f862b10968297092488568751b0ed)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-30T15:09:44Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":11.78,"sim_time":6079.77474,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":0.95,"sim_time":23.864219000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.98,"sim_time":148.112301,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":1.68,"sim_time":128.404935,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.09,"sim_time":54.381489,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.2,"sim_time":52.011131999999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.98,"sim_time":148.112301,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.09,"sim_time":54.381489,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":85.4,"sim_time":135806.13149200001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":11.78,"sim_time":6079.77474,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":85.4,"sim_time":135806.13149200001,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":173.92,"sim_time":239430.44136599998,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":268.31,"sim_time":175000.644841,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":85.4,"sim_time":135806.13149200001,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":173.92,"sim_time":239430.44136599998,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":201.38,"sim_time":111498.157626,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":177.5,"sim_time":79848.959137,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":513.68,"sim_time":220623.72318,"passed":198,"total":200,"percent":99.0}},"passed":198,"total":200,"percent":99.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":173.92,"sim_time":239430.44136599998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":173.92,"sim_time":239430.44136599998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":173.92,"sim_time":239430.44136599998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":710.18,"sim_time":20296.70952,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":21.02,"sim_time":8524.826487,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":21.02,"sim_time":8524.826487,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":104.26,"sim_time":65391.778505,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":9.37,"sim_time":4190.561142,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":12.2,"sim_time":6084.752168,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":48.66,"sim_time":6449.583834,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":566.36,"sim_time":91755.612083,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":1594.69,"sim_time":214679.05566100002,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.94,"sim_time":22.355923999999998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.96,"sim_time":14.668375,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.84,"sim_time":651.463617,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.84,"sim_time":651.463617,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.95,"sim_time":23.864219000000002,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.98,"sim_time":148.112301,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.09,"sim_time":54.381489,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.17,"sim_time":122.941881,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.95,"sim_time":23.864219000000002,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.98,"sim_time":148.112301,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.09,"sim_time":54.381489,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.17,"sim_time":122.941881,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":382,"total":397,"percent":96.22166246851386},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.35,"sim_time":166.623158,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.77,"sim_time":381.551365,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.77,"sim_time":381.551365,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":89.13,"sim_time":5854.284621000001,"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":91.55,"fsm":null},"assertion":98.85,"functional":99.3},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.22068855073839946792284176074817865800583310310411328280975556372431214437592","seed":22068855073839946792284176074817865800583310310411328280975556372431214437592,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4212487177 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 4212759907 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (213 [0xd5] vs 189 [0xbd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 4423762017 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 4423807472 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.10299313259023224440167689446051620185066303518816328188699706400782216503377","seed":10299313259023224440167689446051620185066303518816328188699706400782216503377,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19238231186 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 19238511186 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (173 [0xad] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 19596991186 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 19596991186 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.47634986267342671655659831442887976762281082089994805170333716550736276066029","seed":47634986267342671655659831442887976762281082089994805170333716550736276066029,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 48455040057 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 48455083535 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (25 [0x19] vs 253 [0xfd]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 48455170491 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 48455213969 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.52589424938805875129842470594550818295762500757656631536189608816143038594514","seed":52589424938805875129842470594550818295762500757656631536189608816143038594514,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2835514011 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2835555677 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (41 [0x29] vs 223 [0xdf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2835743174 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 2835764007 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.32062775956809277690059361817133240722572027031075842538572546794400599986433","seed":32062775956809277690059361817133240722572027031075842538572546794400599986433,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 359099370845 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 359100245845 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (29 [0x1d] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 360274120845 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 360274120845 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.37073603250306949859728159438839313883220981150821558887000289529921681589977","seed":37073603250306949859728159438839313883220981150821558887000289529921681589977,"line":84,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 19886562905 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 21593522905 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 21593522905 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 22739502905 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.71036815639198433347084223092770412399133504353431155900223158491167586243969","seed":71036815639198433347084223092770412399133504353431155900223158491167586243969,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 30124274611 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 31004753459 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 2\n","UVM_ERROR @ 31004763985 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 31004774511 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (71 [0x47] vs 9 [0x9]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.103824850659628462785563012022512319399620292244605641963521834294088138473257","seed":103824850659628462785563012022512319399620292244605641963521834294088138473257,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  12275817 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @  95706567 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 142377042 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 232434492 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.24693689767049285998747392095463661720979863102981809219180226475059530445518","seed":24693689767049285998747392095463661720979863102981809219180226475059530445518,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 103198505 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 1389708505 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1389708505 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 2572658505 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/19\n"]},{"name":"uart_stress_all","qual_name":"7.uart_stress_all.40382121929752316018937754070563573621813817761649192128246921916954520729382","seed":40382121929752316018937754070563573621813817761649192128246921916954520729382,"line":78,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 4998900280 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 5054591746 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n","UVM_ERROR @ 5177592976 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 5177592976 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.16992074589604182993008233194555195791553595452219137756475050488939728075357","seed":16992074589604182993008233194555195791553595452219137756475050488939728075357,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1765798112 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3001568869 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3001568869 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4206474480 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.26595270908864348229488340578944205084517679208529706268989369228114438686537","seed":26595270908864348229488340578944205084517679208529706268989369228114438686537,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  98695952 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 100415952 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 100695952 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 101335952 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"11.uart_stress_all_with_rand_reset.113354828188413190476349383885319513996371498228310141647448788086543174538976","seed":113354828188413190476349383885319513996371498228310141647448788086543174538976,"line":99,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 636961008 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 636961008 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 637191008 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 643081008 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"15.uart_stress_all_with_rand_reset.84701984009157973846936384786201627095800096888470850359512069576594341627910","seed":84701984009157973846936384786201627095800096888470850359512069576594341627910,"line":77,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @  62410371 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 1152266424 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/39\n","UVM_INFO @ 2758836246 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/39\n","UVM_INFO @ 3744692403 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/39\n"]}],"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.106852907297689396431469461282533240969270062552288321560739766693987070215368","seed":106852907297689396431469461282533240969270062552288321560739766693987070215368,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 29606335563 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 29606335563 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 29632515563 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 5\n","UVM_ERROR @ 29632525563 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_fifo_reset","qual_name":"46.uart_fifo_reset.1446077257863743393101424770342460669323853080031618284631859763841264687822","seed":1446077257863743393101424770342460669323853080031618284631859763841264687822,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/46.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 103373362020 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5\n","UVM_INFO @ 103887122020 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5\n","UVM_INFO @ 112603282020 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5\n","UVM_INFO @ 114183150010 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5\n"]},{"name":"uart_fifo_reset","qual_name":"129.uart_fifo_reset.43783422895928197707636314866377554429597223750542538727779624752775478141308","seed":43783422895928197707636314866377554429597223750542538727779624752775478141308,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/129.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @  47850958 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6\n","UVM_INFO @ 183953246 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6\n","UVM_INFO @ 330773246 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6\n","UVM_INFO @ 798483246 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6\n"]}]}},"passed":436,"total":453,"percent":96.24724061810154}