{"block":{"name":"spi_device","variant":"1r1w","commit":"2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7","commit_short":"2348eb2","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7","revision_info":"GitHub Revision: [`2348eb2`](https://github.com/lowrisc/opentitan/tree/2348eb2d2a78c1cb023cfd0db2dc7500b046cbf7)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-06-06T15:22:54Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":350.07,"sim_time":130323.621433,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.88,"sim_time":196.73027,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.89,"sim_time":672.5159470000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":10.15,"sim_time":716.84513,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":8.84,"sim_time":373.936225,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.61,"sim_time":920.651607,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.89,"sim_time":672.5159470000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.84,"sim_time":373.936225,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.91,"sim_time":32.92336,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.79,"sim_time":45.684650000000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.18,"sim_time":22.023776,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.07,"sim_time":1.122375,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":1.04,"sim_time":3.019455,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":8.47,"sim_time":3062.6127140000003,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":8.47,"sim_time":3062.6127140000003,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":26.1,"sim_time":35438.429336999994,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.14,"sim_time":70.976272,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":32.76,"sim_time":5718.5601639999995,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":50.02,"sim_time":15843.267657,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":36.29,"sim_time":44868.955259,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":36.29,"sim_time":44868.955259,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":24.14,"sim_time":3171.402419,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":24.14,"sim_time":3171.402419,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":24.14,"sim_time":3171.402419,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":24.14,"sim_time":3171.402419,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":24.14,"sim_time":3171.402419,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":24.52,"sim_time":37996.79496,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":128.44,"sim_time":70572.74158599999,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":128.44,"sim_time":70572.74158599999,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":128.44,"sim_time":70572.74158599999,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":60.52000000000001,"sim_time":6172.065591,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":10.22,"sim_time":4886.872503,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":128.44,"sim_time":70572.74158599999,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":306.92,"sim_time":45668.328574,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":12.06,"sim_time":1315.0448729999998,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":12.06,"sim_time":1315.0448729999998,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"flash_mode_ignore_cmds":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":388.11,"sim_time":64380.846167,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":350.07,"sim_time":130323.621433,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":580.21,"sim_time":75218.63044499999,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":587.87,"sim_time":161647.58286899998,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.09,"sim_time":19.840628000000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.16,"sim_time":60.528134,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":6.1,"sim_time":248.699817,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":6.1,"sim_time":248.699817,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.88,"sim_time":196.73027,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.89,"sim_time":672.5159470000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.84,"sim_time":373.936225,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.53,"sim_time":683.1891870000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.88,"sim_time":196.73027,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.89,"sim_time":672.5159470000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.84,"sim_time":373.936225,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.53,"sim_time":683.1891870000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":356,"total":378,"percent":94.17989417989418},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.56,"sim_time":136.48113899999998,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":26.1,"sim_time":13461.16763,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":26.1,"sim_time":13461.16763,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.9,"branch":98.3,"condition_expression":96.53,"toggle":83.54,"fsm":89.36},"assertion":95.51,"functional":99.16},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.109009361503434311129152155190217925954961968906765905715162446910702952178463","seed":109009361503434311129152155190217925954961968906765905715162446910702952178463,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2323363 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2323363 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.76276604103427728920683826966497818558289554683106394879857570606296535194417","seed":76276604103427728920683826966497818558289554683106394879857570606296535194417,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    915664 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    915664 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[990])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.113069448903918613210382945505767292113195660822154663582767453515671836733411","seed":113069448903918613210382945505767292113195660822154663582767453515671836733411,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    740783 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    740783 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.84625608496471855303974822593291572640916003623688064214986311396634182424750","seed":84625608496471855303974822593291572640916003623688064214986311396634182424750,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   7566641 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   7566641 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[935])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.28066176212536612920585932844721974614246057607800942227756069804662158126659","seed":28066176212536612920585932844721974614246057607800942227756069804662158126659,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1100756 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1100756 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[911])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.90648423082352575055413081172715505448151902546159229091453126353808817016717","seed":90648423082352575055413081172715505448151902546159229091453126353808817016717,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1330014 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1330014 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.8746271124888170998509890535025644788176964800961318282681091639595281794049","seed":8746271124888170998509890535025644788176964800961318282681091639595281794049,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    976772 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    976772 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[915])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.82324722844201859830821063323139760411154725286392792433251533917587033282648","seed":82324722844201859830821063323139760411154725286392792433251533917587033282648,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    841001 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    841001 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1007])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.104825057550360454632654803648712344475737310802368383956125757131993540851306","seed":104825057550360454632654803648712344475737310802368383956125757131993540851306,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4692575 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4692575 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.92965984127475523505367628244848774478801096879145251034747789265442686100775","seed":92965984127475523505367628244848774478801096879145251034747789265442686100775,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1304925 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1304925 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.55871246832575920905264896523259238068959171549683558161458197200407234771807","seed":55871246832575920905264896523259238068959171549683558161458197200407234771807,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1351819 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1351819 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[909])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.15377326671568908681502164391794921281995023014039170841304293535917564602896","seed":15377326671568908681502164391794921281995023014039170841304293535917564602896,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3936520 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3936520 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.39376712640173766120755121590718223586841606568822071699314406218873723173433","seed":39376712640173766120755121590718223586841606568822071699314406218873723173433,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4732349 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4732349 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.4767952558972071762539919267062910969554089954232550351049695300123393488172","seed":4767952558972071762539919267062910969554089954232550351049695300123393488172,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2785174 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2785174 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[969])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.27776043237604532915357643532517186427594342974977318048606847891988317316687","seed":27776043237604532915357643532517186427594342974977318048606847891988317316687,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2385192 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2385192 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.764339393216313901388136656541057823879729037938552489554677479754219740573","seed":764339393216313901388136656541057823879729037938552489554677479754219740573,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3144752 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3144752 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[909])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.34386598237922178824104195108451338330421391846416558989059824386984038997113","seed":34386598237922178824104195108451338330421391846416558989059824386984038997113,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3002301 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3002301 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.70896366865754755765700865358889090210374622838284988130989232724544195935751","seed":70896366865754755765700865358889090210374622838284988130989232724544195935751,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    920127 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    920127 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[962])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.32757413794766045017214481613667940473836565968858317005760015885733626707088","seed":32757413794766045017214481613667940473836565968858317005760015885733626707088,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1173480 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1173480 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[963])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.49891152800088335950536780240279702112730613079633703368916677964322659085223","seed":49891152800088335950536780240279702112730613079633703368916677964322659085223,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1962922 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1962922 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.84147025540841934460984958879544793560888377320727645147401706381500784790240","seed":84147025540841934460984958879544793560888377320727645147401706381500784790240,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @    770455 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7057bc [11100000101011110111100] vs 0x0 [0]) \n","UVM_ERROR @    781455 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xaec00 [10101110110000000000] vs 0x0 [0]) \n","UVM_ERROR @    859455 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb8de16 [101110001101111000010110] vs 0x0 [0]) \n","UVM_ERROR @    874455 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x576eef [10101110110111011101111] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *":[{"name":"spi_device_flash_mode_ignore_cmds","qual_name":"0.spi_device_flash_mode_ignore_cmds.3968573633482327266572426343884234135373733842091502107982903530464607219876","seed":3968573633482327266572426343884234135373733842091502107982903530464607219876,"line":87,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log","log_context":["tl_ul_fuzzy_flash_status_q[i] = 0x37a6c0\n","tl_ul_fuzzy_flash_status_q[i] = 0x117dc4\n","tl_ul_fuzzy_flash_status_q[i] = 0x1d495c\n","tl_ul_fuzzy_flash_status_q[i] = 0xfa8438\n"]}]}},"passed":394,"total":416,"percent":94.71153846153847}