{"block":{"name":"chip","variant":null,"commit":"1134d70f0985e32239b4616e6dbfdf01f71b146b","commit_short":"1134d70","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1134d70f0985e32239b4616e6dbfdf01f71b146b","revision_info":"GitHub Revision: [`1134d70`](https://github.com/lowrisc/opentitan/tree/1134d70f0985e32239b4616e6dbfdf01f71b146b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-06-27T02:42:03Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_flash":{"max_time":215.48,"sim_time":3054.2493990000003,"passed":3,"total":3,"percent":100.0},"chip_sw_example_rom":{"max_time":134.52,"sim_time":2809.183594,"passed":3,"total":3,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":191.06,"sim_time":3200.3088399999997,"passed":3,"total":3,"percent":100.0},"chip_sw_example_concurrency":{"max_time":247.07,"sim_time":3405.78306,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":414.5,"sim_time":7240.474284,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":615.3,"sim_time":6105.315281,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":802.05,"sim_time":8074.3238949999995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":4262.16,"sim_time":27721.827436,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":835.69,"sim_time":11419.005904,"passed":2,"total":5,"percent":40.0}},"passed":2,"total":5,"percent":40.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":4262.16,"sim_time":27721.827436,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":615.3,"sim_time":6105.315281,"passed":5,"total":5,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":9.87,"sim_time":198.444255,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":372.46,"sim_time":4348.952085,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":372.46,"sim_time":4348.952085,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":372.46,"sim_time":4348.952085,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":509.79999999999995,"sim_time":4593.553616,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":509.79999999999995,"sim_time":4593.553616,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":576.5,"sim_time":4981.3686179999995,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":532.84,"sim_time":4819.286730000001,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":505.06000000000006,"sim_time":4697.400019999999,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":2304.34,"sim_time":13365.479905,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":2152.65,"sim_time":13123.026708000001,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":1375.96,"sim_time":13192.529115,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":125,"total":128,"percent":97.65625},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":303.24,"sim_time":5008.356487999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":303.24,"sim_time":5008.356487999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":330.54,"sim_time":3984.38983,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":484.85999999999996,"sim_time":6880.96861,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":244.26999999999998,"sim_time":4041.5015439999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":1182.29,"sim_time":15338.040308,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":519.55,"sim_time":7132.338321,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":418.65,"sim_time":6406.906995,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1028.78,"sim_time":12618.321754,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":643.39,"sim_time":6043.212284,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":643.39,"sim_time":6043.212284,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":895.53,"sim_time":7487.627414,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":1875.56,"sim_time":13561.806551000001,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":472.74,"sim_time":4303.816699,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":737.35,"sim_time":5627.724345,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5119.36,"sim_time":19289.151213,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":199.33,"sim_time":2988.96735,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":851.64,"sim_time":7091.109052,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":258.1,"sim_time":3778.306126,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2004.82,"sim_time":12832.68594,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":255.26,"sim_time":3947.701512,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":571.25,"sim_time":5716.9083949999995,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":200.17,"sim_time":2693.261554,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":252.56,"sim_time":3376.288875,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":660.82,"sim_time":6012.653102,"passed":3,"total":5,"percent":60.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":367.1,"sim_time":5610.3416560000005,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":8,"percent":75.0},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":246.86,"sim_time":3563.519589,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":367.1,"sim_time":5610.3416560000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_smoketest":{"tests":{"chip_sw_flash_scrambling_smoketest":{"max_time":214.51,"sim_time":3045.103548,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_smoketest":{"max_time":237.06,"sim_time":3184.184188,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":264.53,"sim_time":3098.0836719999998,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":211.33,"sim_time":2864.515653,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":221.6,"sim_time":3167.1762590000003,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":1311.45,"sim_time":7728.524423999999,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":306.17,"sim_time":3966.8746269999997,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":328.13,"sim_time":3857.5833,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":291.24,"sim_time":3204.3585279999998,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":1204.96,"sim_time":7760.7555999999995,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":493.74000000000007,"sim_time":6232.608984,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":419.31,"sim_time":6872.27226,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":218.26,"sim_time":2991.5890010000003,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":275.56,"sim_time":3679.29696,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":221.92,"sim_time":2954.14033,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":203.83,"sim_time":3057.206345,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":253.70000000000002,"sim_time":2917.5871,"passed":3,"total":3,"percent":100.0}},"passed":51,"total":51,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":194.41,"sim_time":2972.213085,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":526.73,"sim_time":5487.84393,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":12992.62,"sim_time":62965.883306,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":4007.11,"sim_time":17077.32514,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":20.10724923806265,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":451.4,"sim_time":4302.380442,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":390.9,"sim_time":10793.203710000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":10918.31,"sim_time":55961.823695,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":11575.92,"sim_time":59223.338419,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":301.21,"sim_time":3204.097032,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":301.21,"sim_time":3204.097032,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":4262.16,"sim_time":27721.827436,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":3325.7,"sim_time":25296.595331999997,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":414.5,"sim_time":7240.474284,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":615.3,"sim_time":6105.315281,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":4262.16,"sim_time":27721.827436,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":3325.7,"sim_time":25296.595331999997,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":414.5,"sim_time":7240.474284,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":615.3,"sim_time":6105.315281,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":74.52,"sim_time":2322.553185,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":7.28,"sim_time":51.27911,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":79.87,"sim_time":9878.840887,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":88.23,"sim_time":5913.486359,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":45.73,"sim_time":596.882607,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":424.57,"sim_time":55903.568178999994,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":422.74,"sim_time":35153.321669,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":60.06000000000001,"sim_time":1388.35016,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":53.71,"sim_time":1376.013989,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":57.3,"sim_time":2057.01303,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":53.71,"sim_time":1376.013989,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":112.69,"sim_time":3334.258816,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":838.56,"sim_time":85398.702252,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":70.07,"sim_time":2227.318939,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":506.03,"sim_time":16585.012813999998,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":657.28,"sim_time":21288.926052000003,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":848.83,"sim_time":20291.156285999998,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":486.12,"sim_time":12877.714641,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":4007.11,"sim_time":17077.32514,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":3951.04,"sim_time":33907.705281,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":3966.86,"sim_time":15454.567005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":81.44191270298325,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":9.57143577793613,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":11.548356486018747,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":11.735792371211573,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":11.192732017021626,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":103.35305275488645,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":11.53786622802727,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":11.119797967839986,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":10.486277959076688,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":10.98933609505184,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":145.5106618029531,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":11.983204568037763,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":11.452955902088434,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":11.938672753050923,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":11.524114198051393,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":32.04,"sim_time":10.120001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":22.21,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":26.67,"sim_time":10.400001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":25.95,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":30.02,"sim_time":10.100001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":28.88,"sim_time":10.240001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":21.39,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":29.39,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":24.99,"sim_time":10.260001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":24.62,"sim_time":10.120001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":20.58,"sim_time":10.240001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":25.72,"sim_time":10.220001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":33.32,"sim_time":10.120001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":23.87,"sim_time":10.360001,"passed":0,"total":1,"percent":0.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":25.43,"sim_time":10.140001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":53.471895857015625,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_dev":{"max_time":11.790958390105516,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod":{"max_time":10.98834424908273,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_prod_end":{"max_time":11.472004920011386,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"rom_e2e_asm_init_rma":{"max_time":11.948801112128422,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":15,"percent":0.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":8094.05,"sim_time":29397.342258,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":7838.63,"sim_time":29619.380989999998,"passed":2,"total":3,"percent":66.66666666666667},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":8114.250000000001,"sim_time":28857.157769,"passed":3,"total":3,"percent":100.0}},"passed":8,"total":9,"percent":88.88888888888889},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":4300.15,"sim_time":15993.166564,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.171854915796,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.171854915796,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":292.4,"sim_time":3158.536675,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":199.33,"sim_time":2988.96735,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":229.25,"sim_time":3270.25262,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":230.55,"sim_time":3342.036284,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":1773.41,"sim_time":10545.18976,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":280.71,"sim_time":3263.9762680000003,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":543.84,"sim_time":6162.965306,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":746.92,"sim_time":5650.10804,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":413.9,"sim_time":4049.8855999999996,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":504.57,"sim_time":5038.265173000001,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":284.92,"sim_time":3406.909479,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1863.91,"sim_time":14843.000512,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":384.93,"sim_time":5388.301536,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":280.58,"sim_time":3331.7313820000004,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":14400.169950067066,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1453.24,"sim_time":8243.5538,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1360.72,"sim_time":7982.179016,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":1076.2,"sim_time":8456.674192,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":12875.47,"sim_time":255120.174276,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":347.83,"sim_time":4315.017441,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":493.74000000000007,"sim_time":6232.608984,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":347.83,"sim_time":4315.017441,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":579.57,"sim_time":8437.6975,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":579.57,"sim_time":8437.6975,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":468.32,"sim_time":7911.709636,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":515.61,"sim_time":5998.123782,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":768.43,"sim_time":6191.061315000001,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":230.55,"sim_time":3342.036284,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":290.9,"sim_time":3696.151194,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":234.71,"sim_time":3037.800145,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":493.19000000000005,"sim_time":5517.716207,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":386.99,"sim_time":4232.491448,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":331.43,"sim_time":3826.941705,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":427.56,"sim_time":4777.770996,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":1300.72,"sim_time":13863.054178999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":534.29,"sim_time":4290.76511,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":530.65,"sim_time":4732.265904,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":575.44,"sim_time":4562.883314000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":512.66,"sim_time":5472.804575,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":527.48,"sim_time":4102.24475,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":495.6600000000001,"sim_time":5131.334900000001,"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":895.53,"sim_time":7487.627414,"passed":3,"total":3,"percent":100.0}},"passed":21,"total":21,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":870.85,"sim_time":11122.045234,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":575.44,"sim_time":4562.883314000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":512.66,"sim_time":5472.804575,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":472.74,"sim_time":4303.816699,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":737.35,"sim_time":5627.724345,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5119.36,"sim_time":19289.151213,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":199.33,"sim_time":2988.96735,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":851.64,"sim_time":7091.109052,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":258.1,"sim_time":3778.306126,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2004.82,"sim_time":12832.68594,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":255.26,"sim_time":3947.701512,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":571.25,"sim_time":5716.9083949999995,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":200.17,"sim_time":2693.261554,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":209.46,"sim_time":2914.304415,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":499.71,"sim_time":4882.892196000001,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":819.29,"sim_time":7320.130132,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":5513.7,"sim_time":25142.436725000003,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":237.06,"sim_time":3762.26957,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":257.52,"sim_time":3381.187316,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":1442.73,"sim_time":12252.323965,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":304.67,"sim_time":3487.650254,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":471.28,"sim_time":5654.1558669999995,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1501.62,"sim_time":19565.029581,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":20851.84,"sim_time":135059.925677,"passed":3,"total":3,"percent":100.0}},"passed":33,"total":33,"percent":100.0},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":895.53,"sim_time":7487.627414,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":519.29,"sim_time":5501.877383999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":401.16,"sim_time":3658.308912,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1453.24,"sim_time":8243.5538,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3123.9,"sim_time":24598.788934999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":235.6,"sim_time":3754.689372,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":706.99,"sim_time":7834.508474,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":237.52,"sim_time":2980.88708,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":7398.75,"sim_time":29757.848061999997,"passed":10,"total":10,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":262.16,"sim_time":3508.06446,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":1143.16,"sim_time":8452.681936,"passed":3,"total":3,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":262.16,"sim_time":3508.06446,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3123.9,"sim_time":24598.788934999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":250.49000000000004,"sim_time":3480.49814,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init":{"tests":{"chip_sw_flash_init":{"max_time":1815.61,"sim_time":18399.665068,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_host_access":{"tests":{"chip_sw_flash_ctrl_access":{"max_time":808.33,"sim_time":5758.553904,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":737.35,"sim_time":5627.724345,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_ctrl_ops":{"tests":{"chip_sw_flash_ctrl_ops":{"max_time":456.88,"sim_time":5022.436696000001,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":472.74,"sim_time":4303.816699,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_rma_unlocked":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":5113.99,"sim_time":44743.497951,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_scramble":{"tests":{"chip_sw_flash_init":{"max_time":1815.61,"sim_time":18399.665068,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_idle_low_power":{"tests":{"chip_sw_flash_ctrl_idle_low_power":{"max_time":324.41,"sim_time":3765.2353420000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_keymgr_seeds":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_creator_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_creator_seed_wipe_on_rma":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":5113.99,"sim_time":44743.497951,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_owner_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_wr_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_seed_hw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_escalate_en":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_flash_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":199.79,"sim_time":6044.36693,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"tests":{"chip_sw_flash_ctrl_clock_freqs":{"max_time":781.26,"sim_time":6048.799795,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_escalation_reset":{"tests":{"chip_sw_flash_crash_alert":{"max_time":590.3,"sim_time":5069.648748,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"tests":{"chip_sw_flash_crash_alert":{"max_time":590.3,"sim_time":5069.648748,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":258.41,"sim_time":3775.491184,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":258.1,"sim_time":3778.306126,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":290.9,"sim_time":3696.151194,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":2003.4300000000003,"sim_time":11737.184653,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":2372.61,"sim_time":12018.670882999999,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":612.76,"sim_time":5879.101395,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":622.99,"sim_time":5580.90916,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":528.74,"sim_time":5410.315312,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":457.44,"sim_time":4426.309139999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2004.82,"sim_time":12832.68594,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"tests":{"chip_sw_keymgr_sideload_kmac":{"max_time":1366.42,"sim_time":8521.033172,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":1773.41,"sim_time":10545.18976,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"tests":{"chip_sw_keymgr_sideload_otbn":{"max_time":6706.16,"sim_time":20018.65612,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":239.24,"sim_time":3276.0964559999998,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":261.28,"sim_time":2829.636798,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":255.26,"sim_time":3947.701512,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":234.16,"sim_time":3179.017944,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":1731.47,"sim_time":10098.191111,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":234.71,"sim_time":3037.800145,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":543.84,"sim_time":6162.965306,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":1182.29,"sim_time":15338.040308,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":418.65,"sim_time":6406.906995,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1028.78,"sim_time":12618.321754,"passed":5,"total":5,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":210.47,"sim_time":3442.80034,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_key_derivation_prod":{"max_time":2008.8799999999999,"sim_time":12199.55418,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":256.59,"sim_time":3124.445278,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_rma_unlocked":{"max_time":5113.99,"sim_time":44743.497951,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":278.72,"sim_time":3857.106499,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":736.62,"sim_time":6631.845082000001,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":799.95,"sim_time":8539.26398,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":752.21,"sim_time":8448.064312999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":504.88000000000005,"sim_time":10033.135858,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":703.89,"sim_time":7579.4971239999995,"passed":3,"total":3,"percent":100.0},"chip_prim_tl_access":{"max_time":199.79,"sim_time":6044.36693,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":870.85,"sim_time":11122.045234,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":534.29,"sim_time":4290.76511,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":530.65,"sim_time":4732.265904,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":575.44,"sim_time":4562.883314000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":512.66,"sim_time":5472.804575,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":527.48,"sim_time":4102.24475,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":495.6600000000001,"sim_time":5131.334900000001,"passed":3,"total":3,"percent":100.0},"chip_tap_straps_dev":{"max_time":1182.29,"sim_time":15338.040308,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":418.65,"sim_time":6406.906995,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1028.78,"sim_time":12618.321754,"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":596.5,"sim_time":16656.779291,"passed":1,"total":3,"percent":33.333333333333336}},"passed":74,"total":84,"percent":88.0952380952381},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":202.95,"sim_time":3437.161458,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":93.39,"sim_time":2720.430486,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":101.48,"sim_time":3362.0435079999997,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":2338.06,"sim_time":26239.576919,"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":6,"percent":83.33333333333333},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":2461.07,"sim_time":35362.387448,"passed":3,"total":3,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":596.5,"sim_time":16656.779291,"passed":1,"total":3,"percent":33.333333333333336}},"passed":4,"total":6,"percent":66.66666666666667},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":1069.55,"sim_time":11454.447310000001,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":894.21,"sim_time":9656.47515,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":868.24,"sim_time":11386.106335,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":505.14000000000004,"sim_time":7671.257213000001,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":2461.07,"sim_time":35362.387448,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":15,"percent":40.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":98.27,"sim_time":2876.177891,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":108.28,"sim_time":2269.547515,"passed":3,"total":3,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":16.690994479926303,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":5,"total":9,"percent":55.55555555555556},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":5069.7,"sim_time":16986.941315,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5119.36,"sim_time":19289.151213,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":768.43,"sim_time":6191.061315000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":768.43,"sim_time":6191.061315000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":768.43,"sim_time":6191.061315000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":436.63,"sim_time":3949.406955,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_flash_init":{"max_time":1815.61,"sim_time":18399.665068,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":436.63,"sim_time":3949.406955,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":509.1700000000001,"sim_time":5518.666614,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":255.79000000000002,"sim_time":3456.3850070000003,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_flash_init":{"max_time":1815.61,"sim_time":18399.665068,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":436.63,"sim_time":3949.406955,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2150.19,"sim_time":13780.291319,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":509.1700000000001,"sim_time":5518.666614,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":255.79000000000002,"sim_time":3456.3850070000003,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":504.21,"sim_time":5050.916108,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":210.47,"sim_time":3442.80034,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":278.72,"sim_time":3857.106499,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":736.62,"sim_time":6631.845082000001,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":799.95,"sim_time":8539.26398,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":752.21,"sim_time":8448.064312999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":989.61,"sim_time":26740.604815000002,"passed":13,"total":15,"percent":86.66666666666667},"chip_prim_tl_access":{"max_time":199.79,"sim_time":6044.36693,"passed":3,"total":3,"percent":100.0}},"passed":25,"total":30,"percent":83.33333333333333},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":199.79,"sim_time":6044.36693,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":1156.08,"sim_time":7182.880878,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":288.78,"sim_time":5340.9019579999995,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1511.36,"sim_time":25408.521754999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":330.89,"sim_time":7599.219940000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":469.68,"sim_time":7607.404,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":724.39,"sim_time":8167.926080000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1370.28,"sim_time":24749.864982,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":1060.58,"sim_time":14437.305284,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":579.57,"sim_time":8437.6975,"passed":0,"total":3,"percent":0.0}},"passed":2,"total":6,"percent":33.333333333333336},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":1183.49,"sim_time":11961.742645,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":518.13,"sim_time":5228.844969,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_aon_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":288.78,"sim_time":5340.9019579999995,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":417.48,"sim_time":4526.163275000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":3387.25,"sim_time":37672.993405,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":365.79,"sim_time":7942.592222,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":221.86,"sim_time":3280.525848,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":2395.66,"sim_time":22845.326095,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1057.04,"sim_time":8975.29382,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1188.73,"sim_time":13561.00675,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":2647.37,"sim_time":32676.001399999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":199.01,"sim_time":2834.6690830000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":504.88000000000005,"sim_time":10033.135858,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":504.88000000000005,"sim_time":10033.135858,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1188.73,"sim_time":13561.00675,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":2395.66,"sim_time":22845.326095,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_pwrmgr_wdog_reset":{"max_time":518.13,"sim_time":5228.844969,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":493.74000000000007,"sim_time":6232.608984,"passed":3,"total":3,"percent":100.0}},"passed":11,"total":12,"percent":91.66666666666667},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":347.27,"sim_time":4749.600125,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":719.63,"sim_time":7012.84022,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":410.86,"sim_time":3851.023381,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1863.91,"sim_time":14843.000512,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":244.08000000000004,"sim_time":3468.33369,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1360.72,"sim_time":7982.179016,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":635.13,"sim_time":5210.762831,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":660.82,"sim_time":4530.6662240000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":256.62,"sim_time":3238.87236,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":255.79000000000002,"sim_time":3456.3850070000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":719.63,"sim_time":7012.84022,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":719.63,"sim_time":7012.84022,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_mcounteren_writable":{"tests":{"chip_sw_rv_core_ibex_mcounteren_writable":{"max_time":193.03,"sim_time":3033.24,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":1418.78,"sim_time":15986.964472,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":1218.04,"sim_time":13830.442836999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":347.27,"sim_time":4749.600125,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":270.56,"sim_time":2856.312045,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":423.83,"sim_time":7001.705475,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":418.65,"sim_time":6406.906995,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":596.5,"sim_time":16656.779291,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":746.92,"sim_time":5650.10804,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":413.9,"sim_time":4049.8855999999996,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":504.57,"sim_time":5038.265173000001,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":256.74,"sim_time":3847.7810600000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":239.92,"sim_time":3121.080278,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":4007.11,"sim_time":17077.32514,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":347.14,"sim_time":3786.198278,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":218.91,"sim_time":3350.6288,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":306.64,"sim_time":2984.629373,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":249.82000000000002,"sim_time":3095.65223,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":509.1700000000001,"sim_time":5518.666614,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":571.25,"sim_time":5716.9083949999995,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":662.38,"sim_time":8696.248099999999,"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":642.6,"sim_time":8088.706575,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":703.89,"sim_time":7579.4971239999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0},"chip_sw_data_integrity_escalation":{"max_time":643.39,"sim_time":6043.212284,"passed":6,"total":6,"percent":100.0}},"passed":98,"total":106,"percent":92.45283018867924},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1057.04,"sim_time":8975.29382,"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1378.68,"sim_time":24212.9325,"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":6,"percent":83.33333333333333},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":238.48,"sim_time":3271.053406,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":315.6,"sim_time":4090.369892,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":508.32,"sim_time":5061.167841,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1378.68,"sim_time":24212.9325,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1378.68,"sim_time":24212.9325,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3252.72,"sim_time":20441.638939,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3252.72,"sim_time":20441.638939,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":489.4599999999999,"sim_time":6418.299674,"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.171854915796,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":173.87,"sim_time":3482.933932,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":192.25,"sim_time":2601.917716,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":358.35,"sim_time":3973.59173,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":407.67,"sim_time":3795.1382940000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":1415.51,"sim_time":8615.847414000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":7064.0,"sim_time":31336.614282000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":2367.67,"sim_time":11868.4342,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":216.03,"sim_time":2775.15305,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1549,"total":1796,"percent":86.24721603563475},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":274.63,"sim_time":3187.8476650000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":217.68,"sim_time":3159.528226,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":6,"percent":83.33333333333333},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":16450.58,"sim_time":72141.02978499999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":1560.51,"sim_time":6502.7202800000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":281.96,"sim_time":4572.404168,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":281.0,"sim_time":3552.187332,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":279.92,"sim_time":4119.648101,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":93.54,"sim_time":1843.548236,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":107.97,"sim_time":2786.7308700000003,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":77.5,"sim_time":2599.180235,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":78.0162454599049,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":392.56,"sim_time":4003.4125010000007,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":451.47,"sim_time":3121.6986,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":1294.07,"sim_time":5756.013541,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":1718.0,"sim_time":9737.606210000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":330.68,"sim_time":3029.481796,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_memory_protection":{"tests":{"chip_sw_flash_ctrl_mem_protection":{"max_time":754.11,"sim_time":5882.407796,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":98.77,"sim_time":2252.1404789999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":184.08,"sim_time":3129.566432,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":445.59,"sim_time":7054.934298,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":475.36,"sim_time":5595.74834,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1188.73,"sim_time":13561.00675,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":281.96,"sim_time":4572.404168,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":281.0,"sim_time":3552.187332,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":279.92,"sim_time":4119.648101,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":501.4200000000001,"sim_time":5124.541716,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":650.51,"sim_time":6538.053324,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.173339761095,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.173339761095,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":220.44,"sim_time":3456.448944,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":509.79999999999995,"sim_time":4593.553616,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":3606.8899999999994,"sim_time":19245.70929,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":135,"total":159,"percent":84.90566037735849},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sival_flash_info_access":{"max_time":288.7,"sim_time":3096.3983,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":27.98,"sim_time":10.240001,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":8.72,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":224.56,"sim_time":3455.882084,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":296.72,"sim_time":3407.27198,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":331.32,"sim_time":4059.870258,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":10.709305208176374,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_ctrl_write_clear":{"max_time":288.75,"sim_time":3589.989038,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_flash_erase":{"max_time":895.74,"sim_time":10010.340001,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":9656.85,"sim_time":45746.049644,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_disjoint":{"max_time":10800.169883962953,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":18,"total":31,"percent":58.064516129032256}},"passed":18,"total":31,"percent":58.064516129032256}},"coverage":{"code":{"block":null,"line_statement":94.61,"branch":94.51,"condition_expression":92.89,"toggle":87.72,"fsm":57.14},"assertion":97.87,"functional":99.35},"cov_report_page":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.105130089822263625122905496771057619603073684306498806925821488036912591246254","seed":105130089822263625122905496771057619603073684306498806925821488036912591246254,"line":301,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.32192577053192346381403778136079371147744443405889038063409674828282199405039","seed":32192577053192346381403778136079371147744443405889038063409674828282199405039,"line":301,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.103753706019529439649034288800303267681822378059310528775065788272575577409619","seed":103753706019529439649034288800303267681822378059310528775065788272575577409619,"line":301,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.80498982785457852760647823593376670299404265220266077967069761569799343664809","seed":80498982785457852760647823593376670299404265220266077967069761569799343664809,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3358.119800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.14922281677075509210057758768983667098787882710797448572072970785766650699813","seed":14922281677075509210057758768983667098787882710797448572072970785766650699813,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3350.628800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.14770731506344957364872480272375825521488827250179870104843126816528805467352","seed":14770731506344957364872480272375825521488827250179870104843126816528805467352,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3232.396470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.8526363471399245787811587167265441281391888880471904728103429502675004965115","seed":8526363471399245787811587167265441281391888880471904728103429502675004965115,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 2674.322850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"1.chip_sw_flash_ctrl_lc_rw_en.110595250864954360624579436790786237009278804316504214524714655026631169065198","seed":110595250864954360624579436790786237009278804316504214524714655026631169065198,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3124.445278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"2.chip_sw_flash_ctrl_lc_rw_en.43779447509074596237219462774056349926796220341666510970830210073353810569693","seed":43779447509074596237219462774056349926796220341666510970830210073353810569693,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3384.471930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.25857037601117930546176576952600751865979627775579853274779492056769485408416","seed":25857037601117930546176576952600751865979627775579853274779492056769485408416,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 5916.363284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.105025454671712469647464582061867705074081249766188415843631910956155226662375","seed":105025454671712469647464582061867705074081249766188415843631910956155226662375,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 8448.064313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.71254993656919236636815646185641937403187441921927454930491556847446806396041","seed":71254993656919236636815646185641937403187441921927454930491556847446806396041,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7181.448852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.97967368693724011447774359256377878714439697878448511351837363894077884312634","seed":97967368693724011447774359256377878714439697878448511351837363894077884312634,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 3129.566432 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3129.566432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"0.chip_sw_csrng_fuse_en_sw_app_read_test.57823555164485382090286813656340156140591516735127386997461545027169948153984","seed":57823555164485382090286813656340156140591516735127386997461545027169948153984,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3754.689372 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3754.689372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.28303908268561029759930014198523502134722367587135034925412601157844912499859","seed":28303908268561029759930014198523502134722367587135034925412601157844912499859,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 2932.074498 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2932.074498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.101431289884588889548887423062751285365442466014160565403854388733812664334581","seed":101431289884588889548887423062751285365442466014160565403854388733812664334581,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 2956.649436 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2956.649436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"38.chip_sw_all_escalation_resets.48322302634610249622149478353135886324706805483236482065149139735688645793387","seed":48322302634610249622149478353135886324706805483236482065149139735688645793387,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2993.940978 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2993.940978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"48.chip_sw_all_escalation_resets.20516133567754075542672833096015800141169554073719491166075474224205431244134","seed":20516133567754075542672833096015800141169554073719491166075474224205431244134,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3124.330240 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3124.330240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.25565736998155565787255886199589768580386612918980383636574399962937419975679","seed":25565736998155565787255886199589768580386612918980383636574399962937419975679,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_transition","qual_name":"0.chip_sw_lc_ctrl_transition.66776699333689854412782265206254500605818787810095221489173071926316170076675","seed":66776699333689854412782265206254500605818787810095221489173071926316170076675,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 26740.604815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"7.chip_sw_lc_ctrl_transition.75097048331947633362397804354219541198045067755966646400626266352154240593518","seed":75097048331947633362397804354219541198045067755966646400626266352154240593518,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 27021.728178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.28155019273290916670775352222850165419082505750646387355685816787315304954262","seed":28155019273290916670775352222850165419082505750646387355685816787315304954262,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9249.046056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.92211142947365787514461133906224408629561238829843706441272989169482829002729","seed":92211142947365787514461133906224408629561238829843706441272989169482829002729,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 9656.475150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.100701798424241817640363950143744104038350595029625746344382488029531032719996","seed":100701798424241817640363950143744104038350595029625746344382488029531032719996,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 5346.644916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.38731353247082690362169414556220303401102190276682503493349248855024300835716","seed":38731353247082690362169414556220303401102190276682503493349248855024300835716,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9388.903330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.56511329397343373010431270692248640075405924535640268350662159826595376938082","seed":56511329397343373010431270692248640075405924535640268350662159826595376938082,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 10938.065200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.112339031423009539227624468441255379702494969562723853676177434273867229053122","seed":112339031423009539227624468441255379702494969562723853676177434273867229053122,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 5642.199052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.112080716930366552254503268295267761977093152305818290020238226902133833478131","seed":112080716930366552254503268295267761977093152305818290020238226902133833478131,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 11454.447310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.87992746687038373888539029099301129640743574707660350834831311354431105276466","seed":87992746687038373888539029099301129640743574707660350834831311354431105276466,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 11802.510066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.90965768962859001443843005986389854174963158662621465932923458706554948516453","seed":90965768962859001443843005986389854174963158662621465932923458706554948516453,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7671.257213 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.104039855730693542533814184465703089892989047355195211136868312575082780101794","seed":104039855730693542533814184465703089892989047355195211136868312575082780101794,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2255.686720 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2255.686720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.713327033531950510142397802538591388154033609933576437283192077117422649181","seed":713327033531950510142397802538591388154033609933576437283192077117422649181,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 5953.385848 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 5953.385848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.35554312538567508383889412541732077480229451181736904998284895061453343993637","seed":35554312538567508383889412541732077480229451181736904998284895061453343993637,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 5340.901958 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 5340.901958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.14449435032268574555267986318463137868311686461808740003543087274160609930417","seed":14449435032268574555267986318463137868311686461808740003543087274160609930417,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5699.439000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5699.439000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.36198595522446694186002596669085910811114326303619661737361115927276780498102","seed":36198595522446694186002596669085910811114326303619661737361115927276780498102,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10121.649500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10121.649500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.51933558152902154553344344829470436365944226863273604869575952318570774062551","seed":51933558152902154553344344829470436365944226863273604869575952318570774062551,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7607.404000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7607.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"0.chip_sw_sysrst_ctrl_reset.115475180868920428437095849806463099451059229510387675034316111946439944169636","seed":115475180868920428437095849806463099451059229510387675034316111946439944169636,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 24212.932500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 24212.932500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.9001749750443667913166205893988547978208348897780242169617211773677296608959","seed":9001749750443667913166205893988547978208348897780242169617211773677296608959,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8437.697500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8437.697500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.61811705575262821980426550942430654132914905591440097502568941201117287549760","seed":61811705575262821980426550942430654132914905591440097502568941201117287549760,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7664.501500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7664.501500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.60189366654002602820953579397512926011331867811467879253841720405928041673282","seed":60189366654002602820953579397512926011331867811467879253841720405928041673282,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8155.588000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8155.588000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_por_reset.18216474474414214954048727258483552215839712672984555197336228964816734795071","seed":18216474474414214954048727258483552215839712672984555197336228964816734795071,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 6780.624000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6780.624000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.104380230014978082086029130384910807054952835363918386738789005236332702369582","seed":104380230014978082086029130384910807054952835363918386738789005236332702369582,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 14011.691000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 14011.691000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.76168912160886119556446656738937038830347257446273068177514134941045261781214","seed":76168912160886119556446656738937038830347257446273068177514134941045261781214,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8083.569500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8083.569500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.65537008087872895697968497332508383423550770231421152174447393440205839381198","seed":65537008087872895697968497332508383423550770231421152174447393440205839381198,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2946.731032 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2946.731032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.94352066974080523923008830786105766839889437785571094241979879321041561152202","seed":94352066974080523923008830786105766839889437785571094241979879321041561152202,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2733.941537 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2733.941537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.14476949564992282939731796373008376497708829369881475260581217763141961390048","seed":14476949564992282939731796373008376497708829369881475260581217763141961390048,"line":434,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 26207.374796 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 26207.374796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.32765103568270124010730575995851244977115818631940399284283523500017921507375","seed":32765103568270124010730575995851244977115818631940399284283523500017921507375,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3280.525848 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3280.525848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.114430074117251122554471290126274798893899356594753052260849261025158678519913","seed":114430074117251122554471290126274798893899356594753052260849261025158678519913,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.85458898063139299312667946351205773672426913962623191412913272105487909496463","seed":85458898063139299312667946351205773672426913962623191412913272105487909496463,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.57463406778690894810430588911978006841452774111552202844691098555397978140925","seed":57463406778690894810430588911978006841452774111552202844691098555397978140925,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.113272971478310521896795229701815107197008007287133747265690251862104472425650","seed":113272971478310521896795229701815107197008007287133747265690251862104472425650,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.103793683363640312078399168099411977937945588531656964329610657599690793526456","seed":103793683363640312078399168099411977937945588531656964329610657599690793526456,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.91129457044926014986925855107301072709794994257745254765392458894454406164092","seed":91129457044926014986925855107301072709794994257745254765392458894454406164092,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.65844348058360504541723718298271514688951187105975154424367330598216165983313","seed":65844348058360504541723718298271514688951187105975154424367330598216165983313,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.1220811512884118708469009154644305859097326513844099490726655939908323220427","seed":1220811512884118708469009154644305859097326513844099490726655939908323220427,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.98097568665421740046398351366950206757288677712390421490418400963151955575295","seed":98097568665421740046398351366950206757288677712390421490418400963151955575295,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.36675047586296266905372105014432427175582535225841273547859820085491212298439","seed":36675047586296266905372105014432427175582535225841273547859820085491212298439,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.49998379996373710508646962335825183326933265809420738876801564080025523833302","seed":49998379996373710508646962335825183326933265809420738876801564080025523833302,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.103403579704399047453612677940088367897866757034116840644502349616909778132870","seed":103403579704399047453612677940088367897866757034116840644502349616909778132870,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.902433903647092468320721665568358443167362096608439810979341752858471612813","seed":902433903647092468320721665568358443167362096608439810979341752858471612813,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3263.976268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.34851399233620992629697681879980636338812619140863466478384113204616137235186","seed":34851399233620992629697681879980636338812619140863466478384113204616137235186,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3807.161001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.64258891195423843191715044172960552134364955106208830423377427864820111417792","seed":64258891195423843191715044172960552134364955106208830423377427864820111417792,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3005.963508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.21021233925681346625578656436076505223108274170814609119121528704863577133581","seed":21021233925681346625578656436076505223108274170814609119121528704863577133581,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3461.394430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.29660246070559331914127991969863536092986732441348522401458319778547132371648","seed":29660246070559331914127991969863536092986732441348522401458319778547132371648,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2623.073856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.37599350971125983583616663213307689105797227729864297932125685429991199744908","seed":37599350971125983583616663213307689105797227729864297932125685429991199744908,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2447.639718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.44219086573350426436116396449700183455602878404929223344948818749150537665726","seed":44219086573350426436116396449700183455602878404929223344948818749150537665726,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3273.513384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.40471515523944364484423606568968159545046876399652767990103523285144997315803","seed":40471515523944364484423606568968159545046876399652767990103523285144997315803,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3085.944198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.75896413339461045011267440597775988841337905269471386465764791162525049780015","seed":75896413339461045011267440597775988841337905269471386465764791162525049780015,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3107.679429 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.57508858802814003275048329152569861638005795623699413713281559201156836230437","seed":57508858802814003275048329152569861638005795623699413713281559201156836230437,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3770.769695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.19280180708975780319266065510871750728250317259280129884563498098401020563312","seed":19280180708975780319266065510871750728250317259280129884563498098401020563312,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3040.602560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.108873379086544838661259080018133867867665430684794912483993085446767970882377","seed":108873379086544838661259080018133867867665430684794912483993085446767970882377,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2614.801310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.115308891542393096569031792764139439627254229345672914019611243828833283658924","seed":115308891542393096569031792764139439627254229345672914019611243828833283658924,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3331.731382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.5384871612363679936961750527442990035346528300958296960494903633908938111004","seed":5384871612363679936961750527442990035346528300958296960494903633908938111004,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2532.275946 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.93092965097286974448951380392702991479773109222572942837137648380274155952571","seed":93092965097286974448951380392702991479773109222572942837137648380274155952571,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2409.228444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.53040013026589700933336489356669116515486346975895076754639596561271734408192","seed":53040013026589700933336489356669116515486346975895076754639596561271734408192,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3299.796560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.26208365417402119054518187476365886924842265634413182808916104795191518743957","seed":26208365417402119054518187476365886924842265634413182808916104795191518743957,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2198.730158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.14143313338626218420861282530136967225509239206968911240073720237306333442204","seed":14143313338626218420861282530136967225509239206968911240073720237306333442204,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3532.336240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.7516509486302478204773575635335826198837263965493150569194019756141799728553","seed":7516509486302478204773575635335826198837263965493150569194019756141799728553,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2494.452500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.60604819985379672037369133849792662423233545318338055017582752958364772262690","seed":60604819985379672037369133849792662423233545318338055017582752958364772262690,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2750.039985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.21515007302658433486529216583848230962466125186490771718907664917944104970441","seed":21515007302658433486529216583848230962466125186490771718907664917944104970441,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2605.193396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.7075494712899826334539804935726377074914832683125016540846146430964252292908","seed":7075494712899826334539804935726377074914832683125016540846146430964252292908,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3021.434248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.102633643593044361498545540940483663041834641250110639022077935306518514430633","seed":102633643593044361498545540940483663041834641250110639022077935306518514430633,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3101.146875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.10192125116755218763304341942322129137327780580020954109996995867788418942592","seed":10192125116755218763304341942322129137327780580020954109996995867788418942592,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3120.745404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.112232900881516142655731610127488316079367613772122791368694163536643855954712","seed":112232900881516142655731610127488316079367613772122791368694163536643855954712,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2626.812720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.65389866705019729069856109354934357958138968888931727165621951309021551495825","seed":65389866705019729069856109354934357958138968888931727165621951309021551495825,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3111.776033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.99376178181532472010142192117282995957314489422194931442546077471618816993504","seed":99376178181532472010142192117282995957314489422194931442546077471618816993504,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2147.937850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.70064096226744471017938567868850422771850062920602966249513924680626853015294","seed":70064096226744471017938567868850422771850062920602966249513924680626853015294,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3362.194601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.81079004186032905529097672283014902024754676889050772877564002244745914014248","seed":81079004186032905529097672283014902024754676889050772877564002244745914014248,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2712.925312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.106878664278671700133651830826371983132623525335578708182216356194303968994019","seed":106878664278671700133651830826371983132623525335578708182216356194303968994019,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2465.389056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.22548524710888902352115937085704876111802467781986407424631367643632132917159","seed":22548524710888902352115937085704876111802467781986407424631367643632132917159,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3170.847791 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.87761429007286605426554781468299949898955935100006215069565228761848639634766","seed":87761429007286605426554781468299949898955935100006215069565228761848639634766,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3778.003124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.76022186157297411247260212554736732996751893836539656075670068351030917754360","seed":76022186157297411247260212554736732996751893836539656075670068351030917754360,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3285.321852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.81880451104229056690331791557775249536120256035418210015334884344900950613889","seed":81880451104229056690331791557775249536120256035418210015334884344900950613889,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3693.522840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.101238827149494674812414865136948883921794054007866995755063737271335798639762","seed":101238827149494674812414865136948883921794054007866995755063737271335798639762,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3033.251742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1532917769205006961394870804279616756081939353696952304668796656817647632456","seed":1532917769205006961394870804279616756081939353696952304668796656817647632456,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3196.241692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.87726311278600476572775566671077543535699033865636972548685956790644708820970","seed":87726311278600476572775566671077543535699033865636972548685956790644708820970,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3220.778480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.44323074928300570022952106391237040422772527340266151155662902338459057573723","seed":44323074928300570022952106391237040422772527340266151155662902338459057573723,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2435.239334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.91013307416405252876065021945719935519750391773561292502718860614666961458531","seed":91013307416405252876065021945719935519750391773561292502718860614666961458531,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2954.003476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.75605154760694503701441930966986784843484951069820749120033543923009790351582","seed":75605154760694503701441930966986784843484951069820749120033543923009790351582,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2986.922278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.20195089240958276361592628778431960549220468226656108136579602852916467776380","seed":20195089240958276361592628778431960549220468226656108136579602852916467776380,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3071.304333 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.7819600731373310996363997904431703042249960300566520854534407730222256401286","seed":7819600731373310996363997904431703042249960300566520854534407730222256401286,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2579.531860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.86003374105222822695275064568673373446533516347125891230705364584320535100201","seed":86003374105222822695275064568673373446533516347125891230705364584320535100201,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2946.255240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.49148651376855584071139186655323864680395913313556396698992521115868986237314","seed":49148651376855584071139186655323864680395913313556396698992521115868986237314,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3643.098950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.92780170763300863479606357289216942140972176251770593042428172797318698937602","seed":92780170763300863479606357289216942140972176251770593042428172797318698937602,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3246.403895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.93293435387039634555482328332803506346990955125331043723889889077768793597819","seed":93293435387039634555482328332803506346990955125331043723889889077768793597819,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3328.855270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.39633778206204347479536694587393497557474709235297627395182558117348741732379","seed":39633778206204347479536694587393497557474709235297627395182558117348741732379,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3152.011510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.35077950862437247940989714532595822438233448501915409869513720551908642321884","seed":35077950862437247940989714532595822438233448501915409869513720551908642321884,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3133.015138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.5764709775511293219318827785353914044733613482030886775797424647361353930318","seed":5764709775511293219318827785353914044733613482030886775797424647361353930318,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3670.499716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.104335193468675473171769693283087332698427368342343728052665391473995753057124","seed":104335193468675473171769693283087332698427368342343728052665391473995753057124,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2674.248134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.26375703072725163023017539104514233712309984514038055579450288241341867082833","seed":26375703072725163023017539104514233712309984514038055579450288241341867082833,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2865.212972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.64272446837485774916078722984871393654155481793157941594781417246277616602499","seed":64272446837485774916078722984871393654155481793157941594781417246277616602499,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2641.305982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.65245649346283946346447093409260770920629853610879647544581579367125755926729","seed":65245649346283946346447093409260770920629853610879647544581579367125755926729,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3034.649455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.97746920441161699578445480014099135834254607184338850710354459215250135195092","seed":97746920441161699578445480014099135834254607184338850710354459215250135195092,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2974.094108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.92642099675230351792076945491927436144419702522022970853404931034987770010239","seed":92642099675230351792076945491927436144419702522022970853404931034987770010239,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2484.100318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.98301994087791100259363828403584547209518577824639362075987742092563216760546","seed":98301994087791100259363828403584547209518577824639362075987742092563216760546,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3005.536012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.50278817460127150057522057414153957312815843389743950305174651323212369362147","seed":50278817460127150057522057414153957312815843389743950305174651323212369362147,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3427.340750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.39988302358331071421144654439735426330044810091504931542822319126800920970946","seed":39988302358331071421144654439735426330044810091504931542822319126800920970946,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2255.759528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.8935251645571013557461472764573136859693569269301126454018076621411406306942","seed":8935251645571013557461472764573136859693569269301126454018076621411406306942,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2500.443584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.77808619050366153175105525474244735794547115039445909799590245700505264595287","seed":77808619050366153175105525474244735794547115039445909799590245700505264595287,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2732.153440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.57163381424607664809781511009753225995267244182732974655431321676095458282032","seed":57163381424607664809781511009753225995267244182732974655431321676095458282032,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3140.211075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.48408592551633219291070570403184082112355435100813152152348676166154658362096","seed":48408592551633219291070570403184082112355435100813152152348676166154658362096,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2783.782398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.5486337799425253298981397904557363659326432172218908841482368049689150979157","seed":5486337799425253298981397904557363659326432172218908841482368049689150979157,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2471.650148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.89452122679782176520386404498965087737566988084994313820234623668466702439479","seed":89452122679782176520386404498965087737566988084994313820234623668466702439479,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3045.980624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.56344461144420039738022853984908255373618538602090018939863889958956742438849","seed":56344461144420039738022853984908255373618538602090018939863889958956742438849,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2759.509978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.93554031965080255949205313063036185242228476420115198834292919186080177880905","seed":93554031965080255949205313063036185242228476420115198834292919186080177880905,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2830.046104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.91195800795782433987933910202421122232346272463088067982990954270038810640451","seed":91195800795782433987933910202421122232346272463088067982990954270038810640451,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2693.678674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.17216043454438039689516345959027186927545548419628372876803218900437434152736","seed":17216043454438039689516345959027186927545548419628372876803218900437434152736,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3028.383800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.37899023275503665748603225898403244885698330725796373038579949459390947688299","seed":37899023275503665748603225898403244885698330725796373038579949459390947688299,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3429.479314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.75908671593691974283653136606299884833169321907691493103802219356248398537804","seed":75908671593691974283653136606299884833169321907691493103802219356248398537804,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2518.509138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.18231970945020537089544157645085580401465186448438820032734667991967242618797","seed":18231970945020537089544157645085580401465186448438820032734667991967242618797,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2427.460936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.40585719127215807043980212125907311029990049355857859823384974103516083671162","seed":40585719127215807043980212125907311029990049355857859823384974103516083671162,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3330.842762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.55672681407974440716525679392297865435835925802314798077181274019555912389334","seed":55672681407974440716525679392297865435835925802314798077181274019555912389334,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2786.350500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.83639833925353827784172201407716753600116035058605760860182500971562597270550","seed":83639833925353827784172201407716753600116035058605760860182500971562597270550,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2366.718600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.9739550095134424982737751409566254245076473405246042198020642632174857106177","seed":9739550095134424982737751409566254245076473405246042198020642632174857106177,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3456.515660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.9969176401842187228235047274566614678939945371302559649017558512662399334341","seed":9969176401842187228235047274566614678939945371302559649017558512662399334341,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2907.507163 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.99203557417651582251500108661533386748213725918583375019187796530878150382816","seed":99203557417651582251500108661533386748213725918583375019187796530878150382816,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3292.507052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.55995829124457977392595427830621084343153319685843287672000178243450746687153","seed":55995829124457977392595427830621084343153319685843287672000178243450746687153,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3314.285571 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.22260530223970957985194904136546899614308328093515023840467986139152237688206","seed":22260530223970957985194904136546899614308328093515023840467986139152237688206,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2262.157742 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.17764693275288552551175893844115762265231194716873011006180804716853457489690","seed":17764693275288552551175893844115762265231194716873011006180804716853457489690,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3017.724800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.15178560186936675681066854644692873042952912683694991685108336447623786435354","seed":15178560186936675681066854644692873042952912683694991685108336447623786435354,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3879.426528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.10010763859290299287576486171130224350326249311945203700739280521789606133421","seed":10010763859290299287576486171130224350326249311945203700739280521789606133421,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2650.617396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.87322954552794476775680243451589902605661133843536247907273675777566522836980","seed":87322954552794476775680243451589902605661133843536247907273675777566522836980,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2860.969998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.50164902274283645515869610148253030736630802203742495018515006088101156839323","seed":50164902274283645515869610148253030736630802203742495018515006088101156839323,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3341.852362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.11061271049123277679118614066085261174545809879722409042220174837078500279949","seed":11061271049123277679118614066085261174545809879722409042220174837078500279949,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3011.821388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.49525157770627085000151146774039034233835918346298043415484363137106092823195","seed":49525157770627085000151146774039034233835918346298043415484363137106092823195,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2994.543082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.112666626633544854917319953942976354556029370183465577616800517567134560738593","seed":112666626633544854917319953942976354556029370183465577616800517567134560738593,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3009.879560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.96112406154612193455848487440539849460855084077206042627371081119773779652225","seed":96112406154612193455848487440539849460855084077206042627371081119773779652225,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3310.421904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.74762280232290339222315536809140598046039359871319021287810804930494607911847","seed":74762280232290339222315536809140598046039359871319021287810804930494607911847,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3148.485445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.87181676668095287515097700932693799871888720937401588860113910108303002072984","seed":87181676668095287515097700932693799871888720937401588860113910108303002072984,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2564.246530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.33554547928605141215185754259274208110060518394583558362827389734896115777439","seed":33554547928605141215185754259274208110060518394583558362827389734896115777439,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2516.654288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.69015588599312920637344882261637638078661362390346742409949846820756106059516","seed":69015588599312920637344882261637638078661362390346742409949846820756106059516,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12026.756101 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"0.chip_sw_keymgr_sideload_otbn.50208560369929730094487101364753244756220381068665947121021232369899730156292","seed":50208560369929730094487101364753244756220381068665947121021232369899730156292,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.739831 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.87859602417183621307075679565820547589982083732984821422018773334221630531187","seed":87859602417183621307075679565820547589982083732984821422018773334221630531187,"line":428,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.670883 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"1.chip_sw_keymgr_sideload_otbn.57444348268624711015944353835206416685545974646757438111822557904885775221919","seed":57444348268624711015944353835206416685545974646757438111822557904885775221919,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.656120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"2.chip_sw_hmac_multistream.63297407543321576898277261753650739881082314677529727914841533336093111711353","seed":63297407543321576898277261753650739881082314677529727914841533336093111711353,"line":345,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12026.444387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"2.chip_sw_keymgr_sideload_otbn.41878697430840321766242706511614071102427349072821762793514524467887878650701","seed":41878697430840321766242706511614071102427349072821762793514524467887878650701,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.551076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.64989092131281965376697144023801522294341520526160209701278928886505631713782","seed":64989092131281965376697144023801522294341520526160209701278928886505631713782,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@39536) { a_addr: 'h106e8  a_data: 'h72cdc0f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h18ad9  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2011.933509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.84061881686918198276270656191914666700478604484730223193216147792781800097113","seed":84061881686918198276270656191914666700478604484730223193216147792781800097113,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30768) { a_addr: 'h1064c  a_data: 'h7ff488de  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1ae79  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2683.748940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.54879975398297262061238019396339421154299549845010684065458163484697917432204","seed":54879975398297262061238019396339421154299549845010684065458163484697917432204,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31560) { a_addr: 'h1062c  a_data: 'h7b85ea1d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h19e34  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2384.637007 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"1.chip_csr_mem_rw_with_rand_reset.67020101880101641300378398797364904748961262246810840901203551813001255655822","seed":67020101880101641300378398797364904748961262246810840901203551813001255655822,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30934) { a_addr: 'h10700  a_data: 'hb7301b18  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h199c0  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2411.381750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.59261619902294097965892352453806364189427666649664109192760601461265276610592","seed":59261619902294097965892352453806364189427666649664109192760601461265276610592,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32642) { a_addr: 'h105fc  a_data: 'h1811a486  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h1aede  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2363.887950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.115326307435770905058619324643463339986673826620816673584767535327709373701914","seed":115326307435770905058619324643463339986673826620816673584767535327709373701914,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30530) { a_addr: 'h105a0  a_data: 'he8e4305c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h1bac9  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2834.905516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.109710138100563408587601914520099188926254964927054945501917583155191406953154","seed":109710138100563408587601914520099188926254964927054945501917583155191406953154,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31764) { a_addr: 'h10344  a_data: 'h78096255  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1aeae  d_param: 'h0  d_source: 'ha  d_data: 'hc51513  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd5b  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2323.782898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.87347344505919102750538654065057961158828095165803701166269716188320809851751","seed":87347344505919102750538654065057961158828095165803701166269716188320809851751,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30280) { a_addr: 'h1064c  a_data: 'h3555519e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1ae62  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1720.314807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.62043784359012999496538451394944759461133357468325975680468814043438916840305","seed":62043784359012999496538451394944759461133357468325975680468814043438916840305,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@41852) { a_addr: 'h106c0  a_data: 'hed7339a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h186e5  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2503.477190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.112371105065307889071607737073853756370721098448423259232458188119434162127661","seed":112371105065307889071607737073853756370721098448423259232458188119434162127661,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@43044) { a_addr: 'h1072c  a_data: 'h60c11d4f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h19929  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2389.431828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.58098745088649844320079625562098803061057365642459102889293734504352148212539","seed":58098745088649844320079625562098803061057365642459102889293734504352148212539,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30662) { a_addr: 'h105ec  a_data: 'ha009ee60  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h18a76  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2107.615880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.38947511479231768860735023281155776441369513308345565966258629626461258199911","seed":38947511479231768860735023281155776441369513308345565966258629626461258199911,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31290) { a_addr: 'h107e8  a_data: 'heeb6dd88  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18d86  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2512.755080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.11874543889926794440715189939373635856299486426153775411105092620242821841234","seed":11874543889926794440715189939373635856299486426153775411105092620242821841234,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30476) { a_addr: 'h104c4  a_data: 'h41998ef6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h18179  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2158.965120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.80093476303285533770285827124483964312083547532031246478064282785073156760145","seed":80093476303285533770285827124483964312083547532031246478064282785073156760145,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30342) { a_addr: 'h105a4  a_data: 'h8e11a27a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h1b63b  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2165.794764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.28693749639806544463001267754249975359079480605109142230013071662233633279259","seed":28693749639806544463001267754249975359079480605109142230013071662233633279259,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@39814) { a_addr: 'h1053c  a_data: 'h1df06dfc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1b6e3  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2151.231832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.50984425176504116325463987522386427134482954584202000633447492099402855940006","seed":50984425176504116325463987522386427134482954584202000633447492099402855940006,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31698) { a_addr: 'h10790  a_data: 'he24af22a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h18dcb  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2303.481488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.87661559515989455832281543035533756724235868012479732139494546665106661313079","seed":87661559515989455832281543035533756724235868012479732139494546665106661313079,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31704) { a_addr: 'h104f8  a_data: 'h895daa3d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h1a55f  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2407.571357 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.1935816650032356659537889124833224520740620881838838449492678873607731944571","seed":1935816650032356659537889124833224520740620881838838449492678873607731944571,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35964) { a_addr: 'h10408  a_data: 'h6dfa4e18  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h18165  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2393.324090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.2837025309944660774561254447223321819592791812199998770123708956818958615351","seed":2837025309944660774561254447223321819592791812199998770123708956818958615351,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33892) { a_addr: 'h106b0  a_data: 'hc43b2904  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h1922c  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2534.521152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.30028676846642526409358119395950532571873179646352236381841513426411577051922","seed":30028676846642526409358119395950532571873179646352236381841513426411577051922,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32634) { a_addr: 'h106d8  a_data: 'hd569f1e9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h1b6fb  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2401.349692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.94879036163646822261557742210027165256901069578459217079047073288099757686820","seed":94879036163646822261557742210027165256901069578459217079047073288099757686820,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30980) { a_addr: 'h106f8  a_data: 'h409dfc96  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1ae7f  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2486.176960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.396893665757667445745113288020424248555834507941831843287001771623209634952","seed":396893665757667445745113288020424248555834507941831843287001771623209634952,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33446) { a_addr: 'h106a0  a_data: 'h524e88ee  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1b6e5  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2440.211211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.79398263941102779342797440551662532911596821521463263820177977611302311839884","seed":79398263941102779342797440551662532911596821521463263820177977611302311839884,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33458) { a_addr: 'h104b4  a_data: 'h20a2346b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h195db  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2100.930688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.45892565834443992231631381710507134499504571596135285102124509032531055397110","seed":45892565834443992231631381710507134499504571596135285102124509032531055397110,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30436) { a_addr: 'h10748  a_data: 'h9754d538  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1a5b4  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2720.279169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.66854307926259813082974055241348891140957339162337221020326208533433833609710","seed":66854307926259813082974055241348891140957339162337221020326208533433833609710,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31538) { a_addr: 'h10734  a_data: 'hc6967163  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h1a93b  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1926.354217 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.44261795707747116041233148112387725432918015439648444455789630561819748736311","seed":44261795707747116041233148112387725432918015439648444455789630561819748736311,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33248) { a_addr: 'h1065c  a_data: 'hc3087f4a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18a8c  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2049.750380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.71432385442931724143005668738100599212040932332704570393129643734231274201753","seed":71432385442931724143005668738100599212040932332704570393129643734231274201753,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40384) { a_addr: 'h105a4  a_data: 'h63624f7c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1b67e  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2864.021629 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.79067215224467895031140318257507321468554274788839502386011027982075653133048","seed":79067215224467895031140318257507321468554274788839502386011027982075653133048,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31936) { a_addr: 'h1070c  a_data: 'h7a6daa66  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h181c6  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2506.626737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.65413215484267060949696124821709313672103746196873492441309762602935414266998","seed":65413215484267060949696124821709313672103746196873492441309762602935414266998,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36084) { a_addr: 'h10340  a_data: 'h65813584  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1a275  d_param: 'h0  d_source: 'h23  d_data: 'hc55513  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd33  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2180.680720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.77810977747993935599332925491230177137722087960681035262299272673222817319663","seed":77810977747993935599332925491230177137722087960681035262299272673222817319663,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32042) { a_addr: 'h104e0  a_data: 'hd9c09b59  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h19513  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2461.005376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.2128441239641506784463177100932984279128948671530265742950752455817288485989","seed":2128441239641506784463177100932984279128948671530265742950752455817288485989,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3598.715638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.2127329077347808709643870050476490724552929880008584941731349259940026922429","seed":2127329077347808709643870050476490724552929880008584941731349259940026922429,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3779.482944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.37024134175469248593223630017379117000992571634702150114716552314830985038162","seed":37024134175469248593223630017379117000992571634702150114716552314830985038162,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4003.412501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.49887874227410262269730882339614289131293090741063945079388826439471310914611","seed":49887874227410262269730882339614289131293090741063945079388826439471310914611,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.18220045823091566920828970664466075710519367952657824661645614350489028001820","seed":18220045823091566920828970664466075710519367952657824661645614350489028001820,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=261757) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=255774) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.84041325873093108090876632693032626172223281900067106803403770619127620479859","seed":84041325873093108090876632693032626172223281900067106803403770619127620479859,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.68244319982834864151612359720939999394149623306795557591678007172419457637305","seed":68244319982834864151612359720939999394149623306795557591678007172419457637305,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.90712648668463855761615404921278995972176296318674674765556758539780213452162","seed":90712648668463855761615404921278995972176296318674674765556758539780213452162,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.52840344179646419511275138070459285509823175535989197631801003632185655864472","seed":52840344179646419511275138070459285509823175535989197631801003632185655864472,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.25976434088764116352143882289149363573197640107204970829354601775164996823055","seed":25976434088764116352143882289149363573197640107204970829354601775164996823055,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["Another command (pid=279962) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=271642) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=261316) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.47763873361085448058523692871908489132538002309440224900967973152444440647692","seed":47763873361085448058523692871908489132538002309440224900967973152444440647692,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.82532333999560223660757501333830736352832755640713145130639637502068684591642","seed":82532333999560223660757501333830736352832755640713145130639637502068684591642,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.17152399982957833834675220659159452484937421194673363755979832602254192344185","seed":17152399982957833834675220659159452484937421194673363755979832602254192344185,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.34890833535463728795870663638742469832258079230369414436717258525937487824562","seed":34890833535463728795870663638742469832258079230369414436717258525937487824562,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.80803519679008989134496137972622103300222830397599429253459319341648655841030","seed":80803519679008989134496137972622103300222830397599429253459319341648655841030,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=292221) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=288068) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=301530) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.11002017186914635376275738109177038665093976516932139414541729775381773911720","seed":11002017186914635376275738109177038665093976516932139414541729775381773911720,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.22858376476498174081646231700754491142994403775358230255371612577397190353502","seed":22858376476498174081646231700754491142994403775358230255371612577397190353502,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.97165928407458125546762725013411816279999431693077530998347611923763360255196","seed":97165928407458125546762725013411816279999431693077530998347611923763360255196,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.51059547858267892944618254584618316063664379254053378127139808418804634988391","seed":51059547858267892944618254584618316063664379254053378127139808418804634988391,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.27929987821133693668794182666362081117292813065520168855491322473238244119173","seed":27929987821133693668794182666362081117292813065520168855491322473238244119173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=255353) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.75742672045117823607399832604803855367469811570561577850775884141628148674914","seed":75742672045117823607399832604803855367469811570561577850775884141628148674914,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.71009259709435942970539351316109651108419013077896440135790259246536314145150","seed":71009259709435942970539351316109651108419013077896440135790259246536314145150,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.6928568443440743482459773443089634874924201947932198127542103567306823165944","seed":6928568443440743482459773443089634874924201947932198127542103567306823165944,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.62363215281812589898695469087132087951972658934100406725373483629652348836436","seed":62363215281812589898695469087132087951972658934100406725373483629652348836436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.109405880343965366001145655506030001937429976106225325375491168963731702438155","seed":109405880343965366001145655506030001937429976106225325375491168963731702438155,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=289245) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=258313) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=289860) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.62873145079689905096286014968666628732525160346190965589030929572010077730905","seed":62873145079689905096286014968666628732525160346190965589030929572010077730905,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=280619) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.43197283101063521777868642613526130190205789915507089366451595480239571915823","seed":43197283101063521777868642613526130190205789915507089366451595480239571915823,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=261316) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=262559) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=281173) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.39272546136067098026074237180499959511283020684165083111891260664485426872111","seed":39272546136067098026074237180499959511283020684165083111891260664485426872111,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=4165580) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.33576091460937145281672086212666015325515102132283944130939042594920673437699","seed":33576091460937145281672086212666015325515102132283944130939042594920673437699,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=303515) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=284093) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=291652) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.76244387995198494626186886608612987232736049360290389936928541066093737849501","seed":76244387995198494626186886608612987232736049360290389936928541066093737849501,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.106006651045594427170666437123473234867841896486074634793218803875639576820004","seed":106006651045594427170666437123473234867841896486074634793218803875639576820004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.113397153062163870314019506693469292282138509997111430512156547724601507473487","seed":113397153062163870314019506693469292282138509997111430512156547724601507473487,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.41124913186955868357071608127258105800720549169545219889548421985722786760838","seed":41124913186955868357071608127258105800720549169545219889548421985722786760838,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.98931495685336973597718678479451360552492985372031793263161488712406307752994","seed":98931495685336973597718678479451360552492985372031793263161488712406307752994,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=309416) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=307696) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.45934087280553774382794856372585526637232740734055970052924634637525265756283","seed":45934087280553774382794856372585526637232740734055970052924634637525265756283,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=313280) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=302054) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=317018) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.46253444044752505121776258977522317074732072810907429273107664354259267177486","seed":46253444044752505121776258977522317074732072810907429273107664354259267177486,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=289257) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=295288) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=300310) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.18827069667897814218766707222962223111673455599859579119501694577815113984353","seed":18827069667897814218766707222962223111673455599859579119501694577815113984353,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=913540) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.42883172214933380593756717321507924028432852744566433829109910806376659844561","seed":42883172214933380593756717321507924028432852744566433829109910806376659844561,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=337222) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=338993) is running. Waiting for it to complete on the server (server_pid=255361)...\n","Another command (pid=339467) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.107057733506510915268103148395098930186167777879791887812061195221631861387051","seed":107057733506510915268103148395098930186167777879791887812061195221631861387051,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.40687173967767595360620145044697224041820286970146524882167395892366546039635","seed":40687173967767595360620145044697224041820286970146524882167395892366546039635,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.80411244301060647863057214055038111135785940083370622465664113160836769813234","seed":80411244301060647863057214055038111135785940083370622465664113160836769813234,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.14881721362316232082111678751853399671770487279468891298187244214379153127","seed":14881721362316232082111678751853399671770487279468891298187244214379153127,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.19014169768017065258338636558200074826051221709239015895312599255757403633866","seed":19014169768017065258338636558200074826051221709239015895312599255757403633866,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.81491700614420178308724177120142110752539249525713534320761552403216311471020","seed":81491700614420178308724177120142110752539249525713534320761552403216311471020,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.30193745066177311726874889343481203985730050985822316269469949103236614513329","seed":30193745066177311726874889343481203985730050985822316269469949103236614513329,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=353013) is running. Waiting for it to complete on the server (server_pid=255361)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.21354871320215323399468359272672624069919453489510339480311317808961917985731","seed":21354871320215323399468359272672624069919453489510339480311317808961917985731,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.101734520371797159943053896383194018308387107509513664376891445190331995287978","seed":101734520371797159943053896383194018308387107509513664376891445190331995287978,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.30340164822421223848039936215799064750273689638623617102750178904483504095726","seed":30340164822421223848039936215799064750273689638623617102750178904483504095726,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.102141260265975555099001266719533146164204527608570749000666774012881404318960","seed":102141260265975555099001266719533146164204527608570749000666774012881404318960,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.54639089102266659685976711016696532545661492110645607015258068052316442560295","seed":54639089102266659685976711016696532545661492110645607015258068052316442560295,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.6738521659515885843928253869728695019561014307584893847882977788394656302278","seed":6738521659515885843928253869728695019561014307584893847882977788394656302278,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.67847477849322919087097497704694189417230472713321903823472706569953472909472","seed":67847477849322919087097497704694189417230472713321903823472706569953472909472,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.12832060347924100301850815114917565170802481634620914888125563725127107132039","seed":12832060347924100301850815114917565170802481634620914888125563725127107132039,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.73247879535325666134147278468705765289180447037119166209598074003529293333159","seed":73247879535325666134147278468705765289180447037119166209598074003529293333159,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.31885000849472921244140084315170347145583117346840648979835162027076402148893","seed":31885000849472921244140084315170347145583117346840648979835162027076402148893,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11111.647034 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.113652587407048510875412596292971414586109281050223706946028593339937381889328","seed":113652587407048510875412596292971414586109281050223706946028593339937381889328,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 12611.116828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.90645528656743965522344934817576335624064247693926014915899726196961072029258","seed":90645528656743965522344934817576335624064247693926014915899726196961072029258,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 13561.806551 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.55913666618526539786498896682819124300810079981071804409037054423862146399230","seed":55913666618526539786498896682819124300810079981071804409037054423862146399230,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.14624996747810996022114524296115042576432203330039473098713326508368782370750","seed":14624996747810996022114524296115042576432203330039473098713326508368782370750,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.15854600813677460144199302511529818530830096584676045544158334912782711686879","seed":15854600813677460144199302511529818530830096584676045544158334912782711686879,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.112673623240035358793928806606801944653883971712164895161658667989851481371612","seed":112673623240035358793928806606801944653883971712164895161658667989851481371612,"line":362,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.60152141995065325354543876909376927325994860236335160831051834033736493820426","seed":60152141995065325354543876909376927325994860236335160831051834033736493820426,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.23674599041062281106741029103060527448922535915479477734120250028623584872054","seed":23674599041062281106741029103060527448922535915479477734120250028623584872054,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.24938851225948330266777627733679769719239806911165257611807359350082192155605","seed":24938851225948330266777627733679769719239806911165257611807359350082192155605,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.102264793453848364480409181218056556679147346178489828592441161051761544738767","seed":102264793453848364480409181218056556679147346178489828592441161051761544738767,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.48282427579274229257947064421626334163871369174012091048464062633915512291931","seed":48282427579274229257947064421626334163871369174012091048464062633915512291931,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.19522335246926868625423777580148082657927243977302678232561538536680217322300","seed":19522335246926868625423777580148082657927243977302678232561538536680217322300,"line":367,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.111606239983502579991958422063828557484500175925125143341223890657102082101","seed":111606239983502579991958422063828557484500175925125143341223890657102082101,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.50250694986394972602128574483552760923178155432112606449364274328984311905794","seed":50250694986394972602128574483552760923178155432112606449364274328984311905794,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.82450892620203794700630991467396108735320295898458260418726674284306492700135","seed":82450892620203794700630991467396108735320295898458260418726674284306492700135,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.37592740696726824514036371300513695048070968831229029191987905395681783652509","seed":37592740696726824514036371300513695048070968831229029191987905395681783652509,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.64782344902859357255844151506240315975557885051724395796166814017590400578349","seed":64782344902859357255844151506240315975557885051724395796166814017590400578349,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.64521057642329053110735146679408976865292858598727848414967390936619073277936","seed":64521057642329053110735146679408976865292858598727848414967390936619073277936,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.98364559411159951031232208636273897135627297075593506543467169455711999402947","seed":98364559411159951031232208636273897135627297075593506543467169455711999402947,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.89302899204630386514210467471999036008959330057384156714087261385771576925126","seed":89302899204630386514210467471999036008959330057384156714087261385771576925126,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.103274870438621469185460921097369158873456720871647437853844800187133695739474","seed":103274870438621469185460921097369158873456720871647437853844800187133695739474,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 17989.495760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.69719358462273365147841570312623574222022345815585175062559050885593312685573","seed":69719358462273365147841570312623574222022345815585175062559050885593312685573,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5487.843930 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5487.843930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.13089346265522558275571448716161773258138727279511935342808402356844218068782","seed":13089346265522558275571448716161773258138727279511935342808402356844218068782,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4947.960880 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4947.960880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.108110138293203336481891742259832004442466467282683476038677778508635466173860","seed":108110138293203336481891742259832004442466467282683476038677778508635466173860,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5124.781698 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5124.781698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration.":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock.14883735581803908704136002190245005437652338388510836455980468202469714134061","seed":14883735581803908704136002190245005437652338388510836455980468202469714134061,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 3086.054900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:387)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.22996897475902261051783664801694575257226460316013832038936480770093955042707","seed":22996897475902261051783664801694575257226460316013832038936480770093955042707,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2935.120600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(reset_cause == HwReq)'":[{"name":"chip_sw_sensor_ctrl_alert","qual_name":"1.chip_sw_sensor_ctrl_alert.69444113240855319422712407687305189592972853026531772418343062968991342591380","seed":69444113240855319422712407687305189592972853026531772418343062968991342591380,"line":346,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sensor_ctrl_alert/latest/run.log","log_context":["UVM_ERROR @ 5025.113628 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A\n","UVM_INFO @ 5025.113628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sensor_ctrl_alert","qual_name":"2.chip_sw_sensor_ctrl_alert.114445878616820986674624533986543425353925542952539120455938542206434449732596","seed":114445878616820986674624533986543425353925542952539120455938542206434449732596,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sensor_ctrl_alert/latest/run.log","log_context":["UVM_ERROR @ 3139.067554 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A\n","UVM_INFO @ 3139.067554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.107604384720081897175378276405531109885396820343977889214054915985000271667001","seed":107604384720081897175378276405531109885396820343977889214054915985000271667001,"line":238,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 6018.550200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.70392501466949022827943244787825674288023609951856617236289417573196590422257","seed":70392501466949022827943244787825674288023609951856617236289417573196590422257,"line":215,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 2440.324992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"2.chip_sw_lc_ctrl_rand_to_scrap.109329385395133491397951871154114559967879688117088951880957872198212356291446","seed":109329385395133491397951871154114559967879688117088951880957872198212356291446,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_INFO @ 26239.576919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:297)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.105648691346794076715037141271471264663546772543604894658182771166482500620381","seed":105648691346794076715037141271471264663546772543604894658182771166482500620381,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2843.785334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"2.chip_sw_rv_core_ibex_lockstep_glitch.48997801035301238227603445268529109790998951721671910201946012740001603595809","seed":48997801035301238227603445268529109790998951721671910201946012740001603595809,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 3159.528226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"9.chip_sw_all_escalation_resets.36842693277546892313505444509391683992566821893447786758128568260777614193941","seed":36842693277546892313505444509391683992566821893447786758128568260777614193941,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2768.062294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"98.chip_sw_all_escalation_resets.85684330429820621375438758924508714949421837250092015469851816546560332215187","seed":85684330429820621375438758924508714949421837250092015469851816546560332215187,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/98.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3894.224936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"11.chip_sw_all_escalation_resets.105377791014562290476997098893650029675318835072769199850647400083829593696772","seed":105377791014562290476997098893650029675318835072769199850647400083829593696772,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3249.129576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"17.chip_sw_all_escalation_resets.87514032311605994329047262992200127179861553362448370292347883826477676247350","seed":87514032311605994329047262992200127179861553362448370292347883826477676247350,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3266.738448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"89.chip_sw_all_escalation_resets.56440191852684466069672012705473891350076416321338105725864706599368081258362","seed":56440191852684466069672012705473891350076416321338105725864706599368081258362,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2531.504980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"94.chip_sw_all_escalation_resets.101446431857250539229473111360350385419698000533212578323687363337792899894552","seed":101446431857250539229473111360350385419698000533212578323687363337792899894552,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3461.869516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1725,"total":2005,"percent":86.0349127182045}