{"block":{"name":"uart","variant":null,"commit":"1134d70f0985e32239b4616e6dbfdf01f71b146b","commit_short":"1134d70","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/1134d70f0985e32239b4616e6dbfdf01f71b146b","revision_info":"GitHub Revision: [`1134d70`](https://github.com/lowrisc/opentitan/tree/1134d70f0985e32239b4616e6dbfdf01f71b146b)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-06-27T02:42:03Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":19.43,"sim_time":5826.485398,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":1.07,"sim_time":1067.594586,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.95,"sim_time":18.170718,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":1.74,"sim_time":272.23184100000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":1.02,"sim_time":41.335937,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.56,"sim_time":97.97066000000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.95,"sim_time":18.170718,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":41.335937,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":209.71,"sim_time":104537.122983,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":19.43,"sim_time":5826.485398,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":209.71,"sim_time":104537.122983,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":380.26,"sim_time":319681.18688700005,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":171.44,"sim_time":164177.557797,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":209.71,"sim_time":104537.122983,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":380.26,"sim_time":319681.18688700005,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":216.97,"sim_time":224504.088594,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":139.9,"sim_time":104652.38795399999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":417.61,"sim_time":148321.647365,"passed":199,"total":200,"percent":99.5}},"passed":199,"total":200,"percent":99.5},"rx_frame_err":{"tests":{"uart_intr":{"max_time":380.26,"sim_time":319681.18688700005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":380.26,"sim_time":319681.18688700005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":380.26,"sim_time":319681.18688700005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":527.47,"sim_time":17610.957725,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":18.64,"sim_time":9149.42937,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":18.64,"sim_time":9149.42937,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":164.95,"sim_time":102160.35289200001,"passed":1,"total":10,"percent":10.0}},"passed":1,"total":10,"percent":10.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":40.6,"sim_time":43333.092748,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":19.09,"sim_time":7259.054129,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":26.66,"sim_time":4229.92179,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":1011.56,"sim_time":141577.716662,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":977.51,"sim_time":261513.41332699996,"passed":8,"total":10,"percent":80.0}},"passed":8,"total":10,"percent":80.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.91,"sim_time":26.5841,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.95,"sim_time":29.6655,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.94,"sim_time":501.228656,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.94,"sim_time":501.228656,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.07,"sim_time":1067.594586,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.95,"sim_time":18.170718,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":41.335937,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.15,"sim_time":161.437238,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":1.07,"sim_time":1067.594586,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.95,"sim_time":18.170718,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":1.02,"sim_time":41.335937,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.15,"sim_time":161.437238,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":385,"total":397,"percent":96.97732997481108},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.26,"sim_time":83.581179,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.81,"sim_time":378.645403,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.81,"sim_time":378.645403,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":82.07,"sim_time":12545.156562,"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"passed":18,"total":20,"percent":90.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":91.55,"fsm":null},"assertion":98.27,"functional":99.37},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.36002053630536737009223403571499627750546301790773597353750095485005002385720","seed":36002053630536737009223403571499627750546301790773597353750095485005002385720,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 6054971520 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6054971520 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 6063991520 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 9\n","UVM_ERROR @ 6064031520 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"1.uart_stress_all.27231345950538103612938508458115212551772534797322789983980810821258855524662","seed":27231345950538103612938508458115212551772534797322789983980810821258855524662,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 71812372469 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 71812372469 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 72191316677 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 72191316677 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n"]},{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.30095872628468735423159234684227637512239796831026420665228697135240844289597","seed":30095872628468735423159234684227637512239796831026420665228697135240844289597,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18629514316 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 18629514316 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 19133234316 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (146 [0x92] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_INFO @ 19133294316 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/8\n"]}],"UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.37834620826752698816807412477156419366375469266920090039751915923097845859110","seed":37834620826752698816807412477156419366375469266920090039751915923097845859110,"line":140,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 253782133051 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 253782175155 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (13 [0xd] vs 127 [0x7f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 253834047283 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 253834047283 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.68734853479046713205360203905396577919739831166847275947885561944300726727629","seed":68734853479046713205360203905396577919739831166847275947885561944300726727629,"line":76,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 10129734686 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10131534686 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (56 [0x38] vs 249 [0xf9]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 10131934686 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 10133334686 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (56 [0x38] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.58075812954067085984792451769441397425560089463417787572862872898351743694760","seed":58075812954067085984792451769441397425560089463417787572862872898351743694760,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2361053025 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2361063442 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (131 [0x83] vs 191 [0xbf]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 2361084276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 2361188446 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (131 [0x83] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.51967180107187277393615569145064879551067113856215236797714588961081800885400","seed":51967180107187277393615569145064879551067113856215236797714588961081800885400,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 737469061 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 743162893 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 748122037 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 750887321 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.63418394291300469465214191928548853819932197565234228266175386785397898465471","seed":63418394291300469465214191928548853819932197565234228266175386785397898465471,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 63142488877 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 63143561013 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 63148839221 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 63151591724 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.79471116484378454045800947160051610882062001183010944445411639704305515422353","seed":79471116484378454045800947160051610882062001183010944445411639704305515422353,"line":75,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 9436093103 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 9436093103 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 9445926397 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 9445926397 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.35772324531324304035021419651554782427238093348440479462885579219902990766165","seed":35772324531324304035021419651554782427238093348440479462885579219902990766165,"line":79,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 8205911846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8216711846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 8440431846 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 8440431846 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"13.uart_stress_all_with_rand_reset.69016409882996737395981745840032034414661404995673699053860913892853088715223","seed":69016409882996737395981745840032034414661404995673699053860913892853088715223,"line":158,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1737025654 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_INFO @ 1769821310 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/836\n","UVM_ERROR @ 1785943630 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1801861870 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.68182630217896814937981757596389235827573892138875488510577369186341610007058","seed":68182630217896814937981757596389235827573892138875488510577369186341610007058,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 190477379 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 381807651 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 381807651 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 474285338 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]}],"UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty":[{"name":"uart_stress_all_with_rand_reset","qual_name":"8.uart_stress_all_with_rand_reset.104391777726335491994674291352476289842158748778435986487886394932560530779578","seed":104391777726335491994674291352476289842158748778435986487886394932560530779578,"line":117,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1113763411 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/165\n","UVM_INFO @ 1168525580 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/165\n","UVM_INFO @ 1218370925 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/165\n","UVM_INFO @ 1285435571 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/165\n"]},{"name":"uart_fifo_reset","qual_name":"59.uart_fifo_reset.51923900926518127561810413808953817887592438375339368015619631593392069579565","seed":51923900926518127561810413808953817887592438375339368015619631593392069579565,"line":74,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/59.uart_fifo_reset/latest/run.log","log_context":["UVM_INFO @ 2166290663 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/7\n","UVM_INFO @ 4827292561 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/7\n","UVM_INFO @ 4891111616 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/7\n","UVM_INFO @ 5740448074 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/7\n"]}]}},"passed":439,"total":453,"percent":96.90949227373068}