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---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.22876909123358030628795481613681235678299797694197046599021130414265135675420","seed":22876909123358030628795481613681235678299797694197046599021130414265135675420,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3224.180368 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3224.180368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"2.chip_sw_csrng_fuse_en_sw_app_read_test.14390560802671540104765558886843959596998371882556018933084995403320803988937","seed":14390560802671540104765558886843959596998371882556018933084995403320803988937,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3225.141096 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3225.141096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.49146219242323060536329764092371858998560216425627303677441801184216589969862","seed":49146219242323060536329764092371858998560216425627303677441801184216589969862,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.26132012450872820585066115960434714479644267517652071830007983231999236062671","seed":26132012450872820585066115960434714479644267517652071830007983231999236062671,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 11202.507684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.58756642135622686876927966518252391574181103884975368735526688842693491818261","seed":58756642135622686876927966518252391574181103884975368735526688842693491818261,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 10461.711960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.15731864134083007442502348215075138879881967549327044012850924880895493828368","seed":15731864134083007442502348215075138879881967549327044012850924880895493828368,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 4942.151550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.75293651642985491984005462674219383907339581419618199095171252889861242688129","seed":75293651642985491984005462674219383907339581419618199095171252889861242688129,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9382.512688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.27641107041628607076145923401591157581547713436357188015843861252070247668965","seed":27641107041628607076145923401591157581547713436357188015843861252070247668965,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 9100.574664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.110455339196261258851380512579294813322108722559280747714920463788361654438749","seed":110455339196261258851380512579294813322108722559280747714920463788361654438749,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9514.260296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.86916335686817574242167070614509303427354384492897525433592502542398283153788","seed":86916335686817574242167070614509303427354384492897525433592502542398283153788,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 8410.120350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.44997917558159856023689435231819228341235330091817630092041290911410032775694","seed":44997917558159856023689435231819228341235330091817630092041290911410032775694,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 6338.529760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.75151153108176028567362071616907523916642346320871631773471953784158148409858","seed":75151153108176028567362071616907523916642346320871631773471953784158148409858,"line":393,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["UVM_INFO @ 38063.468084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.100448262535732455028374278257088259564044591092798186082818571417560442611839","seed":100448262535732455028374278257088259564044591092798186082818571417560442611839,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2420.045079 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2420.045079 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.71961786942331805451701751779565406929296392697226503337065526091661618525378","seed":71961786942331805451701751779565406929296392697226503337065526091661618525378,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2522.030036 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2522.030036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.64754544363014447976949259478409864867572901945822571154351893097376657174737","seed":64754544363014447976949259478409864867572901945822571154351893097376657174737,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 5170.463415 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 5170.463415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.49398845122106571403813247204396170022015396507318947447957908838390131359611","seed":49398845122106571403813247204396170022015396507318947447957908838390131359611,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 12709.505000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 12709.505000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.28745565171132785724791757817358084760342158247321062023659224781127960775092","seed":28745565171132785724791757817358084760342158247321062023659224781127960775092,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6389.400500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6389.400500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.10689083562368890164145618825827975489580980183941847843959551306590136053973","seed":10689083562368890164145618825827975489580980183941847843959551306590136053973,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7496.002000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7496.002000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.84543009109482352874242310294703238297366068693447753556922087135949704861820","seed":84543009109482352874242310294703238297366068693447753556922087135949704861820,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8345.342000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8345.342000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.56767032511891443935803591948415636685480831230594967233934500639552041759013","seed":56767032511891443935803591948415636685480831230594967233934500639552041759013,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 11991.128500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 11991.128500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.89633581698580085633828954433230668396194768097877694477889273832910946385806","seed":89633581698580085633828954433230668396194768097877694477889273832910946385806,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6342.328000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6342.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.63941973683034040083807441496774226227877627711087195606687851225905495481684","seed":63941973683034040083807441496774226227877627711087195606687851225905495481684,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7141.338500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7141.338500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.52671638940687588274779719679283478007744631212766819824889749984065722226454","seed":52671638940687588274779719679283478007744631212766819824889749984065722226454,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 12435.884000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 12435.884000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.5536493971747769290894117806244583820664901053220258984017579492955829781802","seed":5536493971747769290894117806244583820664901053220258984017579492955829781802,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5901.342500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5901.342500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3884999136228299174766403791796791223623516889381744655135401498942756364998","seed":3884999136228299174766403791796791223623516889381744655135401498942756364998,"line":417,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 31972.028000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 31972.028000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.46311228442845708546670705315931113410491002611131526460137782672550760243510","seed":46311228442845708546670705315931113410491002611131526460137782672550760243510,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8500.514000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8500.514000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.55321953513042565282214721358596528937621009125677810182484103918778830353859","seed":55321953513042565282214721358596528937621009125677810182484103918778830353859,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2796.275826 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2796.275826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.113505573441374023050443065440090118914031412958643354788709573095821916184378","seed":113505573441374023050443065440090118914031412958643354788709573095821916184378,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2946.267811 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2946.267811 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.89099648884325709915787543456706308305385996645003292448730756840074847314784","seed":89099648884325709915787543456706308305385996645003292448730756840074847314784,"line":366,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 13210.412040 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 13210.412040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.86350948898459407924131071107158985719091762043357168239270812667172991891808","seed":86350948898459407924131071107158985719091762043357168239270812667172991891808,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3025.196360 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3025.196360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * 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ROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:357)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.111099653903300499909246621901662516142703514267632012171119357787327616406187","seed":111099653903300499909246621901662516142703514267632012171119357787327616406187,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3802.479418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.78694591267867903406451524151717300077248851910248564582450978384042147263483","seed":78694591267867903406451524151717300077248851910248564582450978384042147263483,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3345.550852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.92574861558446591245442503494286608841327296441384065784296906678870931241770","seed":92574861558446591245442503494286608841327296441384065784296906678870931241770,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2485.889558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.95435381460012138641086067355319011257654271874476914919528393261313937310102","seed":95435381460012138641086067355319011257654271874476914919528393261313937310102,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2746.595928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.22938846752184845483139445745082677218623356765456915485503893370378251912525","seed":22938846752184845483139445745082677218623356765456915485503893370378251912525,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2732.813380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.35079362982158914186698446519102164828200754467518500229445165493382648016766","seed":35079362982158914186698446519102164828200754467518500229445165493382648016766,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2700.800868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.18911031802479059691957424251352032784940478034663418787540854708293383656220","seed":18911031802479059691957424251352032784940478034663418787540854708293383656220,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3073.938304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2140548283659559160224791286341504277841675342622302408724234237277739241775","seed":2140548283659559160224791286341504277841675342622302408724234237277739241775,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2872.289428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.75731456688168138143743121072063033000518606408905591366194610083161364336430","seed":75731456688168138143743121072063033000518606408905591366194610083161364336430,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2697.265272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.47076143586617552740300389937633297812534535263299044760427396188062144794424","seed":47076143586617552740300389937633297812534535263299044760427396188062144794424,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2914.024640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.59033127997877199928490141048621878809056707398813226796427770201163270073414","seed":59033127997877199928490141048621878809056707398813226796427770201163270073414,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2930.771820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.9357243038327844173064839740538565770117300064674301878909789314264143272631","seed":9357243038327844173064839740538565770117300064674301878909789314264143272631,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2816.241629 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.41954429950729603732140944494114517106869320417015429672418385037266924990295","seed":41954429950729603732140944494114517106869320417015429672418385037266924990295,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2364.559690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.105325249421724135142442299309474236545783906142222379877560354762349389457369","seed":105325249421724135142442299309474236545783906142222379877560354762349389457369,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2934.375200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.48217977474705432446928641726830586870273553572869303556631572616712925208417","seed":48217977474705432446928641726830586870273553572869303556631572616712925208417,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2708.429496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.65715841263183228515397706280908333441883570288049107736198876614576632748290","seed":65715841263183228515397706280908333441883570288049107736198876614576632748290,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2700.941832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1050932111856409995620162957493407388601493631760985837758788889574131646564","seed":1050932111856409995620162957493407388601493631760985837758788889574131646564,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2477.092308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.64769251894298701705430172471103958853671792679725841593435043446054715798794","seed":64769251894298701705430172471103958853671792679725841593435043446054715798794,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2874.774978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.94959644995471769530093043056221931437002940855747534324834886080548103210548","seed":94959644995471769530093043056221931437002940855747534324834886080548103210548,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3816.131155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.18898334236452953930267187373533695657168307734177486482315154257206258208978","seed":18898334236452953930267187373533695657168307734177486482315154257206258208978,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3271.003770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.29340692596579363741386845187220236309745763819168170262089481465140456944653","seed":29340692596579363741386845187220236309745763819168170262089481465140456944653,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3000.827469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.9885716697829724316295462200332171739441336977156710823668271821826293057350","seed":9885716697829724316295462200332171739441336977156710823668271821826293057350,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3252.208648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.67375964450056930741923369951642041201764491277325338764800975643137873137555","seed":67375964450056930741923369951642041201764491277325338764800975643137873137555,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2980.310154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.101366973405531850626318874875829193203024072789218828954696675365742450889891","seed":101366973405531850626318874875829193203024072789218828954696675365742450889891,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2579.412923 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.28734994329183175565766116183685522650330040352688923618137372017766950582797","seed":28734994329183175565766116183685522650330040352688923618137372017766950582797,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2987.707200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.50091498854052522702775776746063893998805848945920894231744265417544993555011","seed":50091498854052522702775776746063893998805848945920894231744265417544993555011,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2559.456315 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.26155123759838879121544768787827647762629092731647461597118977159384392511217","seed":26155123759838879121544768787827647762629092731647461597118977159384392511217,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2851.589171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.106598460708991617737500579556367544043726710351746778067416235536731231708101","seed":106598460708991617737500579556367544043726710351746778067416235536731231708101,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2686.827960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.68971606202999129088128175263721676202921193154463763508477332753999275891186","seed":68971606202999129088128175263721676202921193154463763508477332753999275891186,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3131.875312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.39081707674050270400743467384536101037236320332653415786788358850085632018920","seed":39081707674050270400743467384536101037236320332653415786788358850085632018920,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3527.933551 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.111235371707096566863131983044627970516139692950386260900548954127202151079694","seed":111235371707096566863131983044627970516139692950386260900548954127202151079694,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3443.217464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.64722517053358062741789831662102152745038078771776574694726875660672692887630","seed":64722517053358062741789831662102152745038078771776574694726875660672692887630,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3001.476866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.24392526718068183522967574576570654232580335201063370507832590109834838353954","seed":24392526718068183522967574576570654232580335201063370507832590109834838353954,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3448.595980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.91414314441112114147053683491691353809509590353386244857857092479570145199285","seed":91414314441112114147053683491691353809509590353386244857857092479570145199285,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3293.095987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.47530901161055220802799648641681525051070435908384755202815146468653540306859","seed":47530901161055220802799648641681525051070435908384755202815146468653540306859,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3016.830016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.64894957119822461705707171199437776474888724589843424021472069364474863096812","seed":64894957119822461705707171199437776474888724589843424021472069364474863096812,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3638.502376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.5262570849346146865142984903648101849639449279335054150076576489195077340898","seed":5262570849346146865142984903648101849639449279335054150076576489195077340898,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3535.380469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.12029243812534934793137163383158481757394055533677831469305030751371229651258","seed":12029243812534934793137163383158481757394055533677831469305030751371229651258,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3512.775987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.19981085941817696935324609284289736184013162676592242086864640928107682328661","seed":19981085941817696935324609284289736184013162676592242086864640928107682328661,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2913.672768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.47478854199747940228834354941277431722637767649512980852880496808859236294906","seed":47478854199747940228834354941277431722637767649512980852880496808859236294906,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2880.848805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.345124846977294833749665268805579370380334868840675868644092810981260999537","seed":345124846977294833749665268805579370380334868840675868644092810981260999537,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3295.113178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.18164769963134643292486872651979437159528013116763946316245579141373043090051","seed":18164769963134643292486872651979437159528013116763946316245579141373043090051,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2877.196715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.67858701884373643961207161089186927010430704944780743104627443821021175219965","seed":67858701884373643961207161089186927010430704944780743104627443821021175219965,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3642.586008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.92353432986799898751575196432777510691585286761903126743443342593856539832997","seed":92353432986799898751575196432777510691585286761903126743443342593856539832997,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3837.893130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.53917106643559522895012141731539823608335900184860722947924805098237850144966","seed":53917106643559522895012141731539823608335900184860722947924805098237850144966,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3115.418576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.16097559752203250614633689325825397885311573776122926210357117679157965895425","seed":16097559752203250614633689325825397885311573776122926210357117679157965895425,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2792.135300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.77986877171027298946116023354057953728605775339611209859462463448132822473856","seed":77986877171027298946116023354057953728605775339611209859462463448132822473856,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3481.949514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.101088696428521303425052694887859115313472783989702539588306655992119623958930","seed":101088696428521303425052694887859115313472783989702539588306655992119623958930,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2934.983096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.75527807659417890257434244458414778018782002019931596018948261357763367376718","seed":75527807659417890257434244458414778018782002019931596018948261357763367376718,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2822.725880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.95461247686391656296431230572366004968299824190759945119042909816413499731273","seed":95461247686391656296431230572366004968299824190759945119042909816413499731273,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2532.521160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.73726058188523067583702696140313983399241830337209131042963576489038578089578","seed":73726058188523067583702696140313983399241830337209131042963576489038578089578,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3497.053136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.112010323696963802773489590104728201552696586124858701068351049169024689004039","seed":112010323696963802773489590104728201552696586124858701068351049169024689004039,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3346.106384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.47899764305892487851194481560985339287907692233091608095648019991869250973167","seed":47899764305892487851194481560985339287907692233091608095648019991869250973167,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3308.117192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.16119425928694559271882451055786548291336245330659478353915308596764871771168","seed":16119425928694559271882451055786548291336245330659478353915308596764871771168,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2740.387132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.34172146984912835350348121911455097196610678601474739463639937190228279289694","seed":34172146984912835350348121911455097196610678601474739463639937190228279289694,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2452.009850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.84994731882784272618198544577351697081380785371376539810198249593201240161694","seed":84994731882784272618198544577351697081380785371376539810198249593201240161694,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2651.225577 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.19110643040856974180373561239254067504504534787462743202538944109807087606074","seed":19110643040856974180373561239254067504504534787462743202538944109807087606074,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3130.249528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.37892850936841755831747783501900333584143869223269758857913343295308807985122","seed":37892850936841755831747783501900333584143869223269758857913343295308807985122,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2428.789736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.50083767566638782035075534522086285870608941798250207195247119089575690650544","seed":50083767566638782035075534522086285870608941798250207195247119089575690650544,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3371.046888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.65804225833087417811856828839800679313878221922851411904829061038392884367037","seed":65804225833087417811856828839800679313878221922851411904829061038392884367037,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3268.455784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.87603294749725370218081831099970826718399252535873909901008555608498321179365","seed":87603294749725370218081831099970826718399252535873909901008555608498321179365,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2583.543300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.10553396009792217082175695288531312990128024647602715549655694245314313928877","seed":10553396009792217082175695288531312990128024647602715549655694245314313928877,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2796.172387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.6442810617070840147631000219665487587800219010147663599184688332710425042617","seed":6442810617070840147631000219665487587800219010147663599184688332710425042617,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3449.717955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.70166606856931475124257621847707631244134369100781397881719966058380921896492","seed":70166606856931475124257621847707631244134369100781397881719966058380921896492,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2610.485465 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.6785545797274267581369098376149019131760242689933698387802793393959385072542","seed":6785545797274267581369098376149019131760242689933698387802793393959385072542,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2787.390186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.71826319585432864114002982699461980724835519895184357306692859377067532262677","seed":71826319585432864114002982699461980724835519895184357306692859377067532262677,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2225.555357 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.102997570253907525325655228168991944568227833253825578564018945804696394154273","seed":102997570253907525325655228168991944568227833253825578564018945804696394154273,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2875.170193 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.32338565254373365104693551541250539671248323850485551692203039496031298117222","seed":32338565254373365104693551541250539671248323850485551692203039496031298117222,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3443.299736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.71984071085965119172031358057515444260144509488290846099685654966699161354424","seed":71984071085965119172031358057515444260144509488290846099685654966699161354424,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2551.733046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.37902474011981653845051640416578300703006237734120812909664426401114419316197","seed":37902474011981653845051640416578300703006237734120812909664426401114419316197,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2731.727350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.73484503199752172760350720599360912287857803538268455322137700573668484100313","seed":73484503199752172760350720599360912287857803538268455322137700573668484100313,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3333.084796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.52403423813221779512787246663983033421842472257140130129648537178529587094010","seed":52403423813221779512787246663983033421842472257140130129648537178529587094010,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2765.952275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.45014025396301411093993994989958824458552955846501581842106324854311488632090","seed":45014025396301411093993994989958824458552955846501581842106324854311488632090,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3128.696778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.111737640322001741445818890420214416564035795141953640042703968517201006984350","seed":111737640322001741445818890420214416564035795141953640042703968517201006984350,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2436.180984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.49500527969323727733404320851396645774407121938867345620721326549033041892631","seed":49500527969323727733404320851396645774407121938867345620721326549033041892631,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2850.345061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.86283532511524679602234284576130051567032209181683702580642501784368368283846","seed":86283532511524679602234284576130051567032209181683702580642501784368368283846,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3239.526760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.109666369454075946836034811637681298485315433194461858810651955707267803278646","seed":109666369454075946836034811637681298485315433194461858810651955707267803278646,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2722.254008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.99528935381705095616485413373822807557304939875223240353244939142906176161423","seed":99528935381705095616485413373822807557304939875223240353244939142906176161423,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3034.149480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.47216519205918542213350461955896418483774676759172921455709423987847720113017","seed":47216519205918542213350461955896418483774676759172921455709423987847720113017,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3520.635364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.67234405690216675030535699346229809322306126144435640598981681933035024428661","seed":67234405690216675030535699346229809322306126144435640598981681933035024428661,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2467.610516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.44540432842569191070125488919590680177568902305773599640193382356838253713358","seed":44540432842569191070125488919590680177568902305773599640193382356838253713358,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2904.012166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.80887601893614971627009027094962386710892542633144825215280286170658695390439","seed":80887601893614971627009027094962386710892542633144825215280286170658695390439,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2569.889326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.27575006196328717878673134216206869622130429637249361832954977785565522698003","seed":27575006196328717878673134216206869622130429637249361832954977785565522698003,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2991.422952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.29309529156742025508438623824647671537380983286510938721916696802199621731340","seed":29309529156742025508438623824647671537380983286510938721916696802199621731340,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3156.936785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.81557602559900731160365484045579888431827852052025339364764279073251639644248","seed":81557602559900731160365484045579888431827852052025339364764279073251639644248,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2470.717464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.22631100694079488446959020132749170372494588044102603376451342209933278970631","seed":22631100694079488446959020132749170372494588044102603376451342209933278970631,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2137.731307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.104591667034815829503807313979745161563469216141553633124883312651783845784962","seed":104591667034815829503807313979745161563469216141553633124883312651783845784962,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2431.405936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.13822008624483862086579168380712988265893347355293924405818279309432560990593","seed":13822008624483862086579168380712988265893347355293924405818279309432560990593,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2992.411230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.39548008608032603534861655980557648159663549583963164620088881944716178122640","seed":39548008608032603534861655980557648159663549583963164620088881944716178122640,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2508.501340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.71624160043640478650184879311154748125737364272799845305426001139734203393480","seed":71624160043640478650184879311154748125737364272799845305426001139734203393480,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3358.934270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.81816337555325424842026771259579649024898748687052927281560540229074570665798","seed":81816337555325424842026771259579649024898748687052927281560540229074570665798,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3561.852152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.92163304715943138542669619928035120485075552563090312378019181826130649709757","seed":92163304715943138542669619928035120485075552563090312378019181826130649709757,"line":418,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12026.850340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"0.chip_sw_keymgr_sideload_otbn.70130509634625320008253347388041911424274677139880418771577028438297260313981","seed":70130509634625320008253347388041911424274677139880418771577028438297260313981,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.816826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.15751417877099342016825542439037165629590109261536089784621619230279866619897","seed":15751417877099342016825542439037165629590109261536089784621619230279866619897,"line":366,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.401756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"1.chip_sw_keymgr_sideload_otbn.110589802350852507510195095285943938176965435116619074563503554756578357027341","seed":110589802350852507510195095285943938176965435116619074563503554756578357027341,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.975964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"2.chip_sw_hmac_multistream.2385308198754001860843824380792452805606916129140978688230659181318191692858","seed":2385308198754001860843824380792452805606916129140978688230659181318191692858,"line":385,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12026.972374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"2.chip_sw_keymgr_sideload_otbn.30069241029038639217831777066303892300113206947098825751694629994114301264522","seed":30069241029038639217831777066303892300113206947098825751694629994114301264522,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.443551 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.114936720844179978975397275460895187305644326645093178257612107802205278946632","seed":114936720844179978975397275460895187305644326645093178257612107802205278946632,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35286) { a_addr: 'h10348  a_data: 'h4cd03e95  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h1b6cb  d_param: 'h0  d_source: 'hc  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2399.795230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.78972848890319782462733300403115805270095317376745180260858735835666031272729","seed":78972848890319782462733300403115805270095317376745180260858735835666031272729,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@131172) { a_addr: 'h10494  a_data: 'h330169d0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h18d07  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2557.967154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"1.chip_csr_mem_rw_with_rand_reset.36444417575321410714733913805543180855834007366954556778084091270567988974204","seed":36444417575321410714733913805543180855834007366954556778084091270567988974204,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30148) { a_addr: 'h104d0  a_data: 'h6b40b3d6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h6  a_opcode: 'h4  a_user: 'h1a96b  d_param: 'h0  d_source: 'h6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2600.503648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.111570942386684170464542024331849012016174176197684214301798370499345154294367","seed":111570942386684170464542024331849012016174176197684214301798370499345154294367,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@38562) { a_addr: 'h105d4  a_data: 'haef74cf0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a2fe  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2479.269916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.109124162196299332970314820081874959957610263643638076051972561687988669748752","seed":109124162196299332970314820081874959957610263643638076051972561687988669748752,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30148) { a_addr: 'h10544  a_data: 'h18973cf4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h1b6e8  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1978.104512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.17962747574532605327371872370969681942192102194182004713711743310253540400043","seed":17962747574532605327371872370969681942192102194182004713711743310253540400043,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31766) { a_addr: 'h10488  a_data: 'hd43f5d16  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1b1cc  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2970.053368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.60421721080385914818227192456677770567622162892106449238469274489794107777564","seed":60421721080385914818227192456677770567622162892106449238469274489794107777564,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33282) { a_addr: 'h10558  a_data: 'ha9aabc1b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18a4e  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2333.251220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.23096613291747271814947093840964925669562535631264558676018971772025909201282","seed":23096613291747271814947093840964925669562535631264558676018971772025909201282,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@39858) { a_addr: 'h106a8  a_data: 'h542cb95f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1a25f  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2776.226545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.72527713229232614663844778018058298865414130352311054556687643584025213805736","seed":72527713229232614663844778018058298865414130352311054556687643584025213805736,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31072) { a_addr: 'h10650  a_data: 'h762796a6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h19298  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1759.157772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.96818442712210530377884818138401332832487061988558947713009131840201705410313","seed":96818442712210530377884818138401332832487061988558947713009131840201705410313,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31230) { a_addr: 'h10760  a_data: 'h989270a2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1a9aa  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2969.079516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.104699159679683713190098283512417092421364294973442911374173219117114242618146","seed":104699159679683713190098283512417092421364294973442911374173219117114242618146,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31104) { a_addr: 'h1051c  a_data: 'hd9928205  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1ae52  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1878.670922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.47432361254622867198771241760064433355313364432952902560685306608295539641012","seed":47432361254622867198771241760064433355313364432952902560685306608295539641012,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31338) { a_addr: 'h10460  a_data: 'h2702711e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h1a5c2  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1963.867748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.109503272415987851397405317819169640508985951810290104527469227769830789764407","seed":109503272415987851397405317819169640508985951810290104527469227769830789764407,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@37688) { a_addr: 'h1064c  a_data: 'h80c8969b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h1ae14  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2618.855880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.77279106143048478817313531508912423085341241992191768631811445182848492657456","seed":77279106143048478817313531508912423085341241992191768631811445182848492657456,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33942) { a_addr: 'h106a8  a_data: 'hc8d897d0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1a230  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1695.572945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.106237872135531849320911307925042016115199767572566262960058609341902614858616","seed":106237872135531849320911307925042016115199767572566262960058609341902614858616,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36356) { a_addr: 'h106b0  a_data: 'h60c7e79e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h19258  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2366.722016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.96832740848170667108242827573787413695103248759979532849061176202371878616532","seed":96832740848170667108242827573787413695103248759979532849061176202371878616532,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30222) { a_addr: 'h107b0  a_data: 'h2be21cfe  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h19564  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2258.689010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.46309970281351604980786653546808442815905624938976391731345388556841986594936","seed":46309970281351604980786653546808442815905624938976391731345388556841986594936,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30390) { a_addr: 'h105f8  a_data: 'hfea86692  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h1a26f  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2128.900864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.79241033937174723609509697915757337449813609612004837608523259999494673703587","seed":79241033937174723609509697915757337449813609612004837608523259999494673703587,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31796) { a_addr: 'h10380  a_data: 'hee26d54b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1ba54  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2334.459512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.30583564478081730478627406162124275904891950815540595318064799355721820920858","seed":30583564478081730478627406162124275904891950815540595318064799355721820920858,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30746) { a_addr: 'h107dc  a_data: 'h5667c03c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h1bd3f  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2094.579776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.56097280323821836533460673597115985226400874171525883824041610070017253382225","seed":56097280323821836533460673597115985226400874171525883824041610070017253382225,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34806) { a_addr: 'h1055c  a_data: 'h69fca3f1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h186e9  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2649.530942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.48049369980049219430985954060123628843769362947087854964441801025019315027656","seed":48049369980049219430985954060123628843769362947087854964441801025019315027656,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30656) { a_addr: 'h10490  a_data: 'hc136618a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h18194  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2244.766215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.18553881191110126221981711795208705024177616684755334475911559877631032157646","seed":18553881191110126221981711795208705024177616684755334475911559877631032157646,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30806) { a_addr: 'h10550  a_data: 'hf553c984  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h19ea9  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2855.220620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.105713841008873628363640257306388410594786611583019492071071098589806730625256","seed":105713841008873628363640257306388410594786611583019492071071098589806730625256,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32604) { a_addr: 'h10534  a_data: 'h289f8ae0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1a240  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2650.819893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.13299351323804938051145716595991130068427993849536523543873984327028836201953","seed":13299351323804938051145716595991130068427993849536523543873984327028836201953,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@43918) { a_addr: 'h10594  a_data: 'h26dd9a09  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h18a66  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2499.833992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.42323056547841088187065082129584078545843038754758971323501852588429675792638","seed":42323056547841088187065082129584078545843038754758971323501852588429675792638,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30898) { a_addr: 'h10400  a_data: 'hbba10acf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h195ad  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2527.802504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.89866188064115086834763799799527485157022534764172443053904221599906001928677","seed":89866188064115086834763799799527485157022534764172443053904221599906001928677,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30862) { a_addr: 'h1048c  a_data: 'hd713d14c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1bd6d  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2314.156209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.63858298964247936349980274285835843647724332231137546945842619221400140327442","seed":63858298964247936349980274285835843647724332231137546945842619221400140327442,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33344) { a_addr: 'h10374  a_data: 'h3c578199  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h192b5  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2279.911245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.72686307400992018159302179751014452574499918659939201391908469418039969941000","seed":72686307400992018159302179751014452574499918659939201391908469418039969941000,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30890) { a_addr: 'h106bc  a_data: 'h4ae2d70  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h18a28  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1868.034001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.93165261669999682133426533165061013836560428340490909338226572168252102579314","seed":93165261669999682133426533165061013836560428340490909338226572168252102579314,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36886) { a_addr: 'h104ac  a_data: 'hfca5e410  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h1a5c4  d_param: 'h0  d_source: 'h26  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2393.608706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.48622219565993069568532726914073029034977956041083636236602101215383351362387","seed":48622219565993069568532726914073029034977956041083636236602101215383351362387,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3533.855203 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.103145936756904639893182026966875775374149282883603299443608560821003653142817","seed":103145936756904639893182026966875775374149282883603299443608560821003653142817,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4288.020254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.9778504754048657288138200921192792935407130936065859440542491575835803459334","seed":9778504754048657288138200921192792935407130936065859440542491575835803459334,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3710.130099 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.92512857182119428410618960413115735964979825981697567585592064542614601829383","seed":92512857182119428410618960413115735964979825981697567585592064542614601829383,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.60403741822928875768134363346381194369522370565290463772163818829139497925530","seed":60403741822928875768134363346381194369522370565290463772163818829139497925530,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=261495) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3699457637520567984316310178656826296735591611762560447265067294648678091280","seed":3699457637520567984316310178656826296735591611762560447265067294648678091280,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.60231145200469084330785671854085674495231269422185022877056122438432249239959","seed":60231145200469084330785671854085674495231269422185022877056122438432249239959,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.94409376449451541048861784905840192003003398521622639661890586385693434073427","seed":94409376449451541048861784905840192003003398521622639661890586385693434073427,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.21543524492742528797079442397249480169491028024994593339806990187464765446319","seed":21543524492742528797079442397249480169491028024994593339806990187464765446319,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.82824099595958324620145760500870755336319165957491995505676907410430248700794","seed":82824099595958324620145760500870755336319165957491995505676907410430248700794,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=261495) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.29471345446705012544616074163858838652372980416813411980285498859553400224239","seed":29471345446705012544616074163858838652372980416813411980285498859553400224239,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.58718142385203206475315651416499861574127450761409811415675714186277285991432","seed":58718142385203206475315651416499861574127450761409811415675714186277285991432,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.51818756655152384378772213893287202901777602309744797915678118930793326766632","seed":51818756655152384378772213893287202901777602309744797915678118930793326766632,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.96400048386956274391286131158554787558547633251029902517869010914071120684342","seed":96400048386956274391286131158554787558547633251029902517869010914071120684342,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.85152054077812329517622625221846994613363999818022663347860834658273336170036","seed":85152054077812329517622625221846994613363999818022663347860834658273336170036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=278444) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=290030) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=282008) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.147363924013355936382105379729550840458014631698307488444617848327265098491","seed":147363924013355936382105379729550840458014631698307488444617848327265098491,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.109920903316473732630292214382978125279801524051365286483284615925904269008064","seed":109920903316473732630292214382978125279801524051365286483284615925904269008064,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44821609727920211444239225724190051771584488450087785594746774133884548632841","seed":44821609727920211444239225724190051771584488450087785594746774133884548632841,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.56829299788940760301093405272283267226101666157766026635808915835093888989222","seed":56829299788940760301093405272283267226101666157766026635808915835093888989222,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.60462261953051128702652572118785568117485495864969080785658453613284969934443","seed":60462261953051128702652572118785568117485495864969080785658453613284969934443,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=255075) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=255087) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.50324995577040556284196402002078342819846132567210580019155005721088123326869","seed":50324995577040556284196402002078342819846132567210580019155005721088123326869,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.32659615122279053315096433464726716146236347474919288020158746696416921140012","seed":32659615122279053315096433464726716146236347474919288020158746696416921140012,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.14778176526896944314969981288569360756380334533173916584754041097172172450196","seed":14778176526896944314969981288569360756380334533173916584754041097172172450196,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.108532176478067223275910449762348322083142722540042308535922553576110218475866","seed":108532176478067223275910449762348322083142722540042308535922553576110218475866,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.82135710704546419066686369651553593075916583855133953211112696978553439425891","seed":82135710704546419066686369651553593075916583855133953211112696978553439425891,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=287025) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=288035) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.3289516847445270325747472859763024009159935947723754660231592204144061876840","seed":3289516847445270325747472859763024009159935947723754660231592204144061876840,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=311426) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=308182) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=305081) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.87278445292283987934226310014033499767048641018569762701124451293534350712361","seed":87278445292283987934226310014033499767048641018569762701124451293534350712361,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=279777) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=262139) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=258000) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.52987698524349635985453639390051915812164937426333934625378522384791299226878","seed":52987698524349635985453639390051915812164937426333934625378522384791299226878,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=4166898) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.15489597325675230034137253731404389616430798554149184691157071382521762234261","seed":15489597325675230034137253731404389616430798554149184691157071382521762234261,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=290030) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=282008) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.52788206220330085443354002909139341759030832782913783201132869911936589205800","seed":52788206220330085443354002909139341759030832782913783201132869911936589205800,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.84513990880898855265138965316720108951042082144047417849393008272027978502751","seed":84513990880898855265138965316720108951042082144047417849393008272027978502751,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.51945895076188664979068329511396316369841950954354584621503049058122195778199","seed":51945895076188664979068329511396316369841950954354584621503049058122195778199,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.11323147857247640620347190886939407759384050105917014783871732656797056554060","seed":11323147857247640620347190886939407759384050105917014783871732656797056554060,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.86289412252564006014136704757911967232906356498008338451105485162215674567369","seed":86289412252564006014136704757911967232906356498008338451105485162215674567369,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=285183) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=284548) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=303124) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.45100306737274294699453471198007315497843496088870833212648332842726151066933","seed":45100306737274294699453471198007315497843496088870833212648332842726151066933,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=292315) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=298141) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=300099) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.39449439412116615416636127014423688786623400327715998933176018802150912195563","seed":39449439412116615416636127014423688786623400327715998933176018802150912195563,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=282008) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=293618) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=290730) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.63520049984342120612001079004996630469413178596572214676109651329089795552727","seed":63520049984342120612001079004996630469413178596572214676109651329089795552727,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=936815) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=936545) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.90066205919561022307881106281591637163914914715230719545087360621908823677807","seed":90066205919561022307881106281591637163914914715230719545087360621908823677807,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=305081) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=291183) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=313925) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.100069972056629099465892897185623742070462283369968106296479313694933090573868","seed":100069972056629099465892897185623742070462283369968106296479313694933090573868,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.19315537539205858300300962003471756287178545045815103435639225619323109699245","seed":19315537539205858300300962003471756287178545045815103435639225619323109699245,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.107233365220677442634821830857247751722972511889649701519257209958510341220851","seed":107233365220677442634821830857247751722972511889649701519257209958510341220851,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.81042718204394593607035849228869359406536836844564396963869750608674563342133","seed":81042718204394593607035849228869359406536836844564396963869750608674563342133,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.108400386385513255204973882648690709138129688279140745364437522888111517874802","seed":108400386385513255204973882648690709138129688279140745364437522888111517874802,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=311221) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=305081) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=291183) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.75489219019208708604228577172655000835144523472842679247769149598336890472806","seed":75489219019208708604228577172655000835144523472842679247769149598336890472806,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=315027) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=322476) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=319984) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.75353595258087145385996404047378777996593904316192315447779768080076796281047","seed":75353595258087145385996404047378777996593904316192315447779768080076796281047,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=284548) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=303124) is running. Waiting for it to complete on the server (server_pid=255103)...\n","Another command (pid=302861) is running. Waiting for it to complete on the server (server_pid=255103)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *":[{"name":"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up","qual_name":"0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.83302186998289740907384672895734575710466807916868842091946194229241837363194","seed":83302186998289740907384672895734575710466807916868842091946194229241837363194,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log","log_context":["UVM_INFO @ 6279.262327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up","qual_name":"1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.80710111815608021107599178611319820824440663651312426833291641994892305175100","seed":80710111815608021107599178611319820824440663651312426833291641994892305175100,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log","log_context":["UVM_INFO @ 5985.903575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.39384302573025990110923829576723775130228498438978523361510646796412484881626","seed":39384302573025990110923829576723775130228498438978523361510646796412484881626,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.46454836914765363499154622211910954498416146208032093329277954996086932601028","seed":46454836914765363499154622211910954498416146208032093329277954996086932601028,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.24116312300520747319729251470210751326855178148239157876332558454484316857726","seed":24116312300520747319729251470210751326855178148239157876332558454484316857726,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.33534845504855711501027800571048845228323615644250211803420082020961621186185","seed":33534845504855711501027800571048845228323615644250211803420082020961621186185,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.19965356001913155532807322718148343712089104020870626040573543406803615131639","seed":19965356001913155532807322718148343712089104020870626040573543406803615131639,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.40519085516262638779829928903465300072310360524225442105429905316497308270131","seed":40519085516262638779829928903465300072310360524225442105429905316497308270131,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.114337288113685217088455046394328673856751666620549174359959039644104890832174","seed":114337288113685217088455046394328673856751666620549174359959039644104890832174,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.94100389198091338726542655184707637974007240168947546802280817509706055922156","seed":94100389198091338726542655184707637974007240168947546802280817509706055922156,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.":[{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.109972894610987474664660527586724853548013667125224284451589477601626240202688","seed":109972894610987474664660527586724853548013667125224284451589477601626240202688,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 12839.393041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.104831551400379108787732693347711525348480706073829137123017995960756225337377","seed":104831551400379108787732693347711525348480706073829137123017995960756225337377,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 13781.706760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.94488731237356200801920569022143784572036780412659794437629893768254840479815","seed":94488731237356200801920569022143784572036780412659794437629893768254840479815,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 13547.131561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.60114266715577623090245440085165650850252849798291840639958036509420646911123","seed":60114266715577623090245440085165650850252849798291840639958036509420646911123,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 14891.813536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"1.chip_sw_power_idle_load.22991240543241619285409246310641922946746004815639382434901482227235965692017","seed":22991240543241619285409246310641922946746004815639382434901482227235965692017,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15611.382110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"2.chip_sw_power_idle_load.11647683721857502148567091865883014494218495090347152293710506523215100893860","seed":11647683721857502148567091865883014494218495090347152293710506523215100893860,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15171.428436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.11314467518769093720166214907379462062312195336012911636260592544890384341008","seed":11314467518769093720166214907379462062312195336012911636260592544890384341008,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 14965.253676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"1.chip_sw_power_sleep_load.20763333828371790350087572897551797946426244052044420291635617565363903815454","seed":20763333828371790350087572897551797946426244052044420291635617565363903815454,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 14777.372978 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.27637383796646868930516383337326872331037053203396567681382261646701342596300","seed":27637383796646868930516383337326872331037053203396567681382261646701342596300,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 14891.986150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.37423555201498117757131343528845646270780019674141981445008799416789785945339","seed":37423555201498117757131343528845646270780019674141981445008799416789785945339,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11003.834445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.42906600085878143718836494980472053869270479616703165200223439065102089063797","seed":42906600085878143718836494980472053869270479616703165200223439065102089063797,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 13913.853244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.67860119894347240220782648036761705128943155374577035674080887320327197125348","seed":67860119894347240220782648036761705128943155374577035674080887320327197125348,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 15225.357844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.2309502627710194463594990990499163083580544704890957524456133047224600449616","seed":2309502627710194463594990990499163083580544704890957524456133047224600449616,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.15757583944606723350400292651343917362047411370605369514800266167072540472760","seed":15757583944606723350400292651343917362047411370605369514800266167072540472760,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.61599760863511626889636509640533718462945653696663996272708550405799192866682","seed":61599760863511626889636509640533718462945653696663996272708550405799192866682,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed \"OpenTitan:*-*-*":[{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.45040463297265996496135132586050876817960269749803670456261600931003981173825","seed":45040463297265996496135132586050876817960269749803670456261600931003981173825,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 7308.619449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"1.rom_e2e_shutdown_exception_c.82209490321454932365189459929602421971997180145462174115817654125779933089165","seed":82209490321454932365189459929602421971997180145462174115817654125779933089165,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 5121.693885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"2.rom_e2e_shutdown_exception_c.34157241024595034913194319936599983567960053276804138763200275370362721314676","seed":34157241024595034913194319936599983567960053276804138763200275370362721314676,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 5630.529821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed \"OpenTitan:*-*-*":[{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.18981313299889827928936266327792846125235556457494100983469799072392332940240","seed":18981313299889827928936266327792846125235556457494100983469799072392332940240,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 6104.790593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"1.rom_e2e_shutdown_output.56979823988548907025826891667395204970439981934001996834758825239162589668159","seed":56979823988548907025826891667395204970439981934001996834758825239162589668159,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 9158.926987 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"2.rom_e2e_shutdown_output.92042736986429039938415364014523976224306389464113789534176477658896723664500","seed":92042736986429039938415364014523976224306389464113789534176477658896723664500,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 7711.798059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.60728010716595472083692003819960927658145261174018719590967108507396191157768","seed":60728010716595472083692003819960927658145261174018719590967108507396191157768,"line":365,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.22956052245622205994803621331888865843968343844635115019447656794239364891445","seed":22956052245622205994803621331888865843968343844635115019447656794239364891445,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.65024874095800723723888319296900506453967267747875605075117273253543189703133","seed":65024874095800723723888319296900506453967267747875605075117273253543189703133,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.94856394388364974191620470081005142592287499770674562533659174347570501306023","seed":94856394388364974191620470081005142592287499770674562533659174347570501306023,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.75938533527262675734336853453319024096250644209432332134263176473655349134725","seed":75938533527262675734336853453319024096250644209432332134263176473655349134725,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.22254137051399823484378554728868205675649303954790920960411249703024792128283","seed":22254137051399823484378554728868205675649303954790920960411249703024792128283,"line":366,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.73521509969137694168031655323762919928152632341178333550829792447640817458582","seed":73521509969137694168031655323762919928152632341178333550829792447640817458582,"line":367,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.98252841513133364652757901535478481717618581029434152153497798417750419391140","seed":98252841513133364652757901535478481717618581029434152153497798417750419391140,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.35453366668316028411224473366947806606584986064948200370141332616134610107818","seed":35453366668316028411224473366947806606584986064948200370141332616134610107818,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.69402360311729170120668230767675682150441524298144892958914075381146064390542","seed":69402360311729170120668230767675682150441524298144892958914075381146064390542,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.26089439244787148020251990652233081777786742826618865911522069790455262313766","seed":26089439244787148020251990652233081777786742826618865911522069790455262313766,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.104534841145372716811638467641588940806806301843863256938227111457772164252095","seed":104534841145372716811638467641588940806806301843863256938227111457772164252095,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.72759440083263477479455471873318954919754474625622024362057548391625803811280","seed":72759440083263477479455471873318954919754474625622024362057548391625803811280,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.76678241393573007376609636334966253771007088880038487081354957559684222424227","seed":76678241393573007376609636334966253771007088880038487081354957559684222424227,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.82543569392627777179640088279872563479808463623585512697613719697269186242024","seed":82543569392627777179640088279872563479808463623585512697613719697269186242024,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.114730703236828374865730985741321419355378487799675911255269643164687184415708","seed":114730703236828374865730985741321419355378487799675911255269643164687184415708,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 17382.964866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_no_meas.75961248216562848436232648949838988163661805893989015834297073532348441870730","seed":75961248216562848436232648949838988163661805893989015834297073532348441870730,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 16265.005232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_no_meas.69312244977497813413974126931269519246398971961528597762011136919743480863342","seed":69312244977497813413974126931269519246398971961528597762011136919743480863342,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 15832.361000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_no_meas.87791383263036108454398836932594855269757276594868221831961385528331248149006","seed":87791383263036108454398836932594855269757276594868221831961385528331248149006,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_INFO @ 16212.734710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.88762404955607622511227978121703849857787444831725866071766200808276789510312","seed":88762404955607622511227978121703849857787444831725866071766200808276789510312,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4403.616186 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4403.616186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.41624296674146691357896521184651166542720338750694566326761550752764608693650","seed":41624296674146691357896521184651166542720338750694566326761550752764608693650,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4430.714019 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4430.714019 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.84074099431901292778139123964009840488326694398025828906883508253060059014336","seed":84074099431901292778139123964009840488326694398025828906883508253060059014336,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 4489.750399 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 4489.750399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$isunknown(pin_wkup_req_o))'":[{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.59280293283325893769336362819221335908598235216223112106726361578793720990399","seed":59280293283325893769336362819221335908598235216223112106726361578793720990399,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_ERROR @ 2150.620000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A\n","UVM_INFO @ 2150.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.105356757013895498262026048355064587172785663273890713795722335970614653037514","seed":105356757013895498262026048355064587172785663273890713795722335970614653037514,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 26277.194087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.112280926469017244583341655019912062267298155127259985296640508149916150839821","seed":112280926469017244583341655019912062267298155127259985296640508149916150839821,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3156.827366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()":[{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"1.chip_sw_pwrmgr_lowpower_cancel.86839234958472507570453521117003235641147612700929828595150944601015346972350","seed":86839234958472507570453521117003235641147612700929828595150944601015346972350,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 2668.139022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.20844562081831546203604348638382033443812342131019102889685935481192487800955","seed":20844562081831546203604348638382033443812342131019102889685935481192487800955,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3453.235980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.61233553406659333035433049230561008365094886268934951000231925320212251530371","seed":61233553406659333035433049230561008365094886268934951000231925320212251530371,"line":236,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 3915.778950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"2.chip_sw_rv_core_ibex_lockstep_glitch.60178258146813003585834920890594058257693309521374081818552757031903871146783","seed":60178258146813003585834920890594058257693309521374081818552757031903871146783,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 2411.593660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_invalid_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_invalid_meas.16591200757606891779203267527395223593763841549283075264613803254271814331042","seed":16591200757606891779203267527395223593763841549283075264613803254271814331042,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log","log_context":["UVM_INFO @ 16331.828364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"21.chip_sw_all_escalation_resets.70782898960956191756415480877829970783686570188020581056910379819243315357156","seed":70782898960956191756415480877829970783686570188020581056910379819243315357156,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2808.741944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"36.chip_sw_all_escalation_resets.92574248084848853131398680694086293674607248336906970515529202340388988094595","seed":92574248084848853131398680694086293674607248336906970515529202340388988094595,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2696.560292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"50.chip_sw_all_escalation_resets.79735780695212080589549444726427588547851105030165589428124647865370387365145","seed":79735780695212080589549444726427588547851105030165589428124647865370387365145,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3177.257412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"54.chip_sw_all_escalation_resets.1166744512594869614859985125399096990575757691806196587541524669478990707756","seed":1166744512594869614859985125399096990575757691806196587541524669478990707756,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3755.491689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"69.chip_sw_all_escalation_resets.37266380210223698909970430124169304336794322627006429217033971663685487197091","seed":37266380210223698909970430124169304336794322627006429217033971663685487197091,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3118.484749 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1713,"total":2005,"percent":85.43640897755611}