{"block":{"name":"sram_ctrl","variant":"ret","commit":"98a020b74d02c316fc2cc682bb212214b5c27e0e","commit_short":"98a020b","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/98a020b74d02c316fc2cc682bb212214b5c27e0e","revision_info":"GitHub Revision: [`98a020b`](https://github.com/lowrisc/opentitan/tree/98a020b74d02c316fc2cc682bb212214b5c27e0e)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-07-04T02:41:51Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sram_ctrl_ret/data/sram_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sram_ctrl_smoke":{"max_time":3.0,"sim_time":404.745194,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"csr_hw_reset":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":26.819467,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":14.620092000000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sram_ctrl_csr_bit_bash":{"max_time":3.0,"sim_time":57.919837,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":17.960945,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sram_ctrl_csr_mem_rw_with_rand_reset":{"max_time":7.0,"sim_time":10093.339218000001,"passed":3,"total":5,"percent":60.0}},"passed":3,"total":5,"percent":60.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":14.620092000000001,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":17.960945,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"sram_ctrl_mem_walk":{"max_time":13.0,"sim_time":1439.5352169999999,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"mem_partial_access":{"tests":{"sram_ctrl_mem_partial_access":{"max_time":6.0,"sim_time":197.048168,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"passed":35,"total":37,"percent":94.5945945945946},"V2":{"testpoints":{"multiple_keys":{"tests":{"sram_ctrl_multiple_keys":{"max_time":17.0,"sim_time":1373.508575,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"stress_pipeline":{"tests":{"sram_ctrl_stress_pipeline":{"max_time":163.0,"sim_time":11486.067304,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"bijection":{"tests":{"sram_ctrl_bijection":{"max_time":10.0,"sim_time":1551.569564,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"access_during_key_req":{"tests":{"sram_ctrl_access_during_key_req":{"max_time":24.0,"sim_time":4128.1237710000005,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"lc_escalation":{"tests":{"sram_ctrl_lc_escalation":{"max_time":8.0,"sim_time":590.402324,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"executable":{"tests":{"sram_ctrl_executable":{"max_time":17.0,"sim_time":7538.810247,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"partial_access":{"tests":{"sram_ctrl_partial_access":{"max_time":3.0,"sim_time":60.591775999999996,"passed":8,"total":8,"percent":100.0},"sram_ctrl_partial_access_b2b":{"max_time":417.0,"sim_time":268113.940843,"passed":8,"total":8,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"max_throughput":{"tests":{"sram_ctrl_max_throughput":{"max_time":2.0,"sim_time":52.872227,"passed":0,"total":8,"percent":0.0},"sram_ctrl_throughput_w_partial_write":{"max_time":2.0,"sim_time":131.75057999999999,"passed":0,"total":8,"percent":0.0},"sram_ctrl_throughput_w_readback":{"max_time":2.0,"sim_time":30.982263,"passed":0,"total":8,"percent":0.0}},"passed":0,"total":24,"percent":0.0},"regwen":{"tests":{"sram_ctrl_regwen":{"max_time":12.0,"sim_time":444.715018,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"ram_cfg":{"tests":{"sram_ctrl_ram_cfg":{"max_time":2.0,"sim_time":207.79755300000002,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"stress_all":{"tests":{"sram_ctrl_stress_all":{"max_time":45.0,"sim_time":17353.485865,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"alert_test":{"tests":{"sram_ctrl_alert_test":{"max_time":2.0,"sim_time":12.973201999999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":6.0,"sim_time":562.128224,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sram_ctrl_tl_errors":{"max_time":6.0,"sim_time":562.128224,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":26.819467,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":14.620092000000001,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":17.960945,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":24.011941,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sram_ctrl_csr_hw_reset":{"max_time":2.0,"sim_time":26.819467,"passed":1,"total":1,"percent":100.0},"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":14.620092000000001,"passed":5,"total":5,"percent":100.0},"sram_ctrl_csr_aliasing":{"max_time":1.0,"sim_time":17.960945,"passed":1,"total":1,"percent":100.0},"sram_ctrl_same_csr_outstanding":{"max_time":2.0,"sim_time":24.011941,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":135,"total":159,"percent":84.90566037735849},"V2S":{"testpoints":{"passthru_mem_tl_intg_err":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.0,"sim_time":464.985402,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_intg_err":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0},"sram_ctrl_tl_intg_err":{"max_time":3.0,"sim_time":765.205512,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"prim_count_check":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sram_ctrl_tl_intg_err":{"max_time":3.0,"sim_time":765.205512,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sec_cm_ctrl_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":12.0,"sim_time":444.715018,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_readback_config_regwen":{"tests":{"sram_ctrl_regwen":{"max_time":12.0,"sim_time":444.715018,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_exec_config_regwen":{"tests":{"sram_ctrl_csr_rw":{"max_time":2.0,"sim_time":14.620092000000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_exec_config_mubi":{"tests":{"sram_ctrl_executable":{"max_time":17.0,"sim_time":7538.810247,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_exec_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":17.0,"sim_time":7538.810247,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_lc_hw_debug_en_intersig_mubi":{"tests":{"sram_ctrl_executable":{"max_time":17.0,"sim_time":7538.810247,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_lc_escalate_en_intersig_mubi":{"tests":{"sram_ctrl_lc_escalation":{"max_time":8.0,"sim_time":590.402324,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_prim_ram_ctrl_mubi":{"tests":{"sram_ctrl_mubi_enc_err":{"max_time":2.0,"sim_time":55.471193,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_mem_integrity":{"tests":{"sram_ctrl_passthru_mem_tl_intg_err":{"max_time":4.0,"sim_time":464.985402,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_mem_readback":{"tests":{"sram_ctrl_readback_err":{"max_time":2.0,"sim_time":39.676324,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_mem_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":3.0,"sim_time":404.745194,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_addr_scramble":{"tests":{"sram_ctrl_smoke":{"max_time":3.0,"sim_time":404.745194,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_instr_bus_lc_gated":{"tests":{"sram_ctrl_executable":{"max_time":17.0,"sim_time":7538.810247,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_ram_tl_lc_gate_fsm_sparse":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_key_global_esc":{"tests":{"sram_ctrl_lc_escalation":{"max_time":8.0,"sim_time":590.402324,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_key_local_esc":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_init_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"sec_cm_scramble_key_sideload":{"tests":{"sram_ctrl_smoke":{"max_time":3.0,"sim_time":404.745194,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"sec_cm_tlul_fifo_ctr_redun":{"tests":{"sram_ctrl_sec_cm":{"max_time":5.0,"sim_time":379.63536700000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":88,"total":88,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sram_ctrl_stress_all_with_rand_reset":{"max_time":117.0,"sim_time":2662.481931,"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"passed":8,"total":8,"percent":100.0}},"coverage":{"code":{"block":94.03,"line_statement":95.21,"branch":89.83,"condition_expression":null,"toggle":78.31,"fsm":66.67},"assertion":98.08,"functional":96.8},"cov_report_page":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*])":[{"name":"sram_ctrl_max_throughput","qual_name":"0.sram_ctrl_max_throughput.62305340684536549246823761116958484226879496770062212216005136132194080820367","seed":62305340684536549246823761116958484226879496770062212216005136132194080820367,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  28679449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"0.sram_ctrl_throughput_w_partial_write.110922229293760911945770464083319666535397178969688793652527919704562132187421","seed":110922229293760911945770464083319666535397178969688793652527919704562132187421,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 131750580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"1.sram_ctrl_max_throughput.24146158499534292972447427138728446829818973980406886484875273273857477611601","seed":24146158499534292972447427138728446829818973980406886484875273273857477611601,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  52872227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"1.sram_ctrl_throughput_w_partial_write.60321207691915997033972788740504527877735027152773884098635954474977407718073","seed":60321207691915997033972788740504527877735027152773884098635954474977407718073,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 103952061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"2.sram_ctrl_max_throughput.99283501865076320405144427155050773388773247669733505044460998579517610472186","seed":99283501865076320405144427155050773388773247669733505044460998579517610472186,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  55198775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"2.sram_ctrl_throughput_w_partial_write.54608342469806598831224823166454773343184894569448842703658924346287964557793","seed":54608342469806598831224823166454773343184894569448842703658924346287964557793,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 108686148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"3.sram_ctrl_max_throughput.36304489642966366236833578336649204142550419074408698052593695793283228485343","seed":36304489642966366236833578336649204142550419074408698052593695793283228485343,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  50898212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"3.sram_ctrl_throughput_w_partial_write.16589874413503757856471382728779424762396249516284965794421707033519364922073","seed":16589874413503757856471382728779424762396249516284965794421707033519364922073,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 113537515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"4.sram_ctrl_max_throughput.62691950253324433463925708026290076984253238795601356849316391453870761646303","seed":62691950253324433463925708026290076984253238795601356849316391453870761646303,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @  54229404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"4.sram_ctrl_throughput_w_partial_write.70952194192569995503065269384991700148379326428970575049704527060661767524387","seed":70952194192569995503065269384991700148379326428970575049704527060661767524387,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @ 100238302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"5.sram_ctrl_max_throughput.68390325097747919445945990178263510376261505795316272648209176556362175117813","seed":68390325097747919445945990178263510376261505795316272648209176556362175117813,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 492208867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"5.sram_ctrl_throughput_w_partial_write.59325757135258204844348678752559000338855456206346415773314103910000267421355","seed":59325757135258204844348678752559000338855456206346415773314103910000267421355,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @  48044802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"6.sram_ctrl_max_throughput.6691225920647974997541523547591289461116152878288152935193474126874122508607","seed":6691225920647974997541523547591289461116152878288152935193474126874122508607,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 101681518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"6.sram_ctrl_throughput_w_partial_write.75650243039687202728775141562461897914898359531947332308972121873980279094509","seed":75650243039687202728775141562461897914898359531947332308972121873980279094509,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @  91764830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_max_throughput","qual_name":"7.sram_ctrl_max_throughput.30414786957168491499909434631289732963222813140105639896539698044311285196171","seed":30414786957168491499909434631289732963222813140105639896539698044311285196171,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_max_throughput/latest/run.log","log_context":["UVM_INFO @ 104635413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_partial_write","qual_name":"7.sram_ctrl_throughput_w_partial_write.92406858685789587782872745324063908651207277553383894653893624614916727944099","seed":92406858685789587782872745324063908651207277553383894653893624614916727944099,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest/run.log","log_context":["UVM_INFO @  58945932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.14343276459540748175439192859889419875494846847265300862208819365537412158913","seed":14343276459540748175439192859889419875494846847265300862208819365537412158913,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  30982263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.57915625069975691663896643552759736870458371286797985079676025941020482173053","seed":57915625069975691663896643552759736870458371286797985079676025941020482173053,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  32447559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.92986575367399489054610745633567359870283773075201881277680851518417724556151","seed":92986575367399489054610745633567359870283773075201881277680851518417724556151,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 114268778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.56661626568809603886050350002260300350354136109084235967038834023775412035895","seed":56661626568809603886050350002260300350354136109084235967038834023775412035895,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  41018197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.33528100798458418320054285128888178743971207277030965296332082311212728955960","seed":33528100798458418320054285128888178743971207277030965296332082311212728955960,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 116809060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.102414671737919916340646607481278302341533288454560524549303393522423634269426","seed":102414671737919916340646607481278302341533288454560524549303393522423634269426,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  29063474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.47769482186934538904509547255327621964303256538512667758253694286642404919635","seed":47769482186934538904509547255327621964303256538512667758253694286642404919635,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 130272133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.85561186198038312040177651226541775570984264942496742746494612178877964710634","seed":85561186198038312040177651226541775570984264942496742746494612178877964710634,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  55395297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"0.sram_ctrl_csr_mem_rw_with_rand_reset.32845245809910091631322305587641821749996611925199774414025961054680353515597","seed":32845245809910091631322305587641821749996611925199774414025961054680353515597,"line":88,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 467431060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:465) [sram_ctrl_common_vseq] wait timeout occurred!":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"1.sram_ctrl_csr_mem_rw_with_rand_reset.92684500229395406098449625429370833381581595562687894569553995154994039094342","seed":92684500229395406098449625429370833381581595562687894569553995154994039094342,"line":98,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 10093339218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":222,"total":248,"percent":89.51612903225806}