{"block":{"name":"sysrst_ctrl","variant":null,"commit":"58f8fdd5396817b775d2c69af9a6322ac7a84e5a","commit_short":"58f8fdd","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/58f8fdd5396817b775d2c69af9a6322ac7a84e5a","revision_info":"GitHub Revision: [`58f8fdd`](https://github.com/lowrisc/opentitan/tree/58f8fdd5396817b775d2c69af9a6322ac7a84e5a)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-07-11T02:34:57Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":7.28,"sim_time":2112.542268,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":7.4,"sim_time":2460.079444,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":7.46,"sim_time":2154.220409,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":7.34,"sim_time":2520.653205,"passed":4,"total":5,"percent":80.0}},"passed":4,"total":5,"percent":80.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.16,"sim_time":6055.006149,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.26,"sim_time":2034.8585090000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":88.04,"sim_time":39056.851663,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":8.19,"sim_time":3180.486535,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":7.44,"sim_time":2050.375642,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.26,"sim_time":2034.8585090000001,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":8.19,"sim_time":3180.486535,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":42,"total":43,"percent":97.67441860465117},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":312.54,"sim_time":157560.433317,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":382.22,"sim_time":174052.85231000002,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":208.89,"sim_time":109154.728046,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":551.1,"sim_time":930891.1516,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":8.09,"sim_time":2513.852918,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":7.29,"sim_time":2248.171457,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":10.83,"sim_time":4819.722341,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":9.29,"sim_time":2610.4280129999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":685.75,"sim_time":4883221.481632,"passed":22,"total":25,"percent":88.0}},"passed":22,"total":25,"percent":88.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":87.06,"sim_time":35092.649072,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":136.83,"sim_time":72725.418976,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":4.77,"sim_time":2014.6954240000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.44,"sim_time":2010.0875500000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.58,"sim_time":2041.7468809999998,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.58,"sim_time":2041.7468809999998,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.16,"sim_time":6055.006149,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.26,"sim_time":2034.8585090000001,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":8.19,"sim_time":3180.486535,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.31,"sim_time":4840.913614,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.16,"sim_time":6055.006149,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.26,"sim_time":2034.8585090000001,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":8.19,"sim_time":3180.486535,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.31,"sim_time":4840.913614,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":317,"total":334,"percent":94.91017964071857},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":80.49,"sim_time":42010.943434,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":102.12,"sim_time":42378.412813,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":102.12,"sim_time":42378.412813,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":14.18,"sim_time":4705.683103,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.92,"branch":99.0,"condition_expression":98.01,"toggle":100.0,"fsm":92.95},"assertion":98.47,"functional":90.57},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: *":[{"name":"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond","qual_name":"1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.23902220935526262293899646827292195591628604500568567393896109371417124091948","seed":23902220935526262293899646827292195591628604500568567393896109371417124091948,"line":657,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 2507308492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_stress_all","qual_name":"3.sysrst_ctrl_stress_all.20940243554513867011640658364277660178213463938886633415739810555580375536235","seed":20940243554513867011640658364277660178213463938886633415739810555580375536235,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 10694489571 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 11784489571 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 11791696699 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq\n","UVM_INFO @ 13789636699 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:76) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Starting the body from auto_blk_key_output_vseq\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.32134866855914496708692223158321660377911623448782012385457760302094628750703","seed":32134866855914496708692223158321660377911623448782012385457760302094628750703,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2484225259 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 6384225259 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 6420857540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"15.sysrst_ctrl_ultra_low_pwr.57242765326778230706669160738935024780989141505544138045713577557965960902400","seed":57242765326778230706669160738935024780989141505544138045713577557965960902400,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2405339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 4965339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 7495339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 10395339784 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"19.sysrst_ctrl_ultra_low_pwr.114270592287210281477953757890458852348174852423559997309015924412828379840302","seed":114270592287210281477953757890458852348174852423559997309015924412828379840302,"line":656,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 5661374427 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 6306374427 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 6322214335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"10.sysrst_ctrl_combo_detect_with_pre_cond.52735912541919501314060222802423432562020810112621083194433280901140673977309","seed":52735912541919501314060222802423432562020810112621083194433280901140673977309,"line":757,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 120953903350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x18\n","UVM_INFO @ 120953933350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x19\n","UVM_INFO @ 121398393350 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2\n","UVM_INFO @ 121413282202 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 17\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"74.sysrst_ctrl_combo_detect_with_pre_cond.44106757701270445342764158741304307985804779082948551324019477626464970800268","seed":44106757701270445342764158741304307985804779082948551324019477626464970800268,"line":700,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 51377776581 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 51377776581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"85.sysrst_ctrl_combo_detect_with_pre_cond.28579720877585915390680928364818060944020337701001665125700598986136258965489","seed":28579720877585915390680928364818060944020337701001665125700598986136258965489,"line":686,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 63329488381 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 63329488381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"18.sysrst_ctrl_combo_detect_with_pre_cond.77189910904508313456082326140822667811517257436812748971896522808219070848475","seed":77189910904508313456082326140822667811517257436812748971896522808219070848475,"line":707,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 56816789612 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 56816789612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"83.sysrst_ctrl_combo_detect_with_pre_cond.99170544889853410243967077572035652954839864203460047610049872556453094489766","seed":99170544889853410243967077572035652954839864203460047610049872556453094489766,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13805872215 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8]) \n","UVM_INFO @ 13805872215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"27.sysrst_ctrl_combo_detect_with_pre_cond.100298746620692904425867979309969464864658480676271924134390061527973671473926","seed":100298746620692904425867979309969464864658480676271924134390061527973671473926,"line":724,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 77403548900 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 77403548900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"38.sysrst_ctrl_combo_detect_with_pre_cond.90690511911555267842825044703438540142514753458423300248646649369332646298209","seed":90690511911555267842825044703438540142514753458423300248646649369332646298209,"line":716,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 66024294851 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 66024294851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"47.sysrst_ctrl_combo_detect_with_pre_cond.69776266329176396231955965142686557419086863710488568812858647473114752693649","seed":69776266329176396231955965142686557419086863710488568812858647473114752693649,"line":710,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 63539292721 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 63559292721 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 73721602409 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x21\n","UVM_INFO @ 73721855033 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x21\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"62.sysrst_ctrl_combo_detect_with_pre_cond.12930717018555794865632628622300111425459146537813065257624188586171555142756","seed":12930717018555794865632628622300111425459146537813065257624188586171555142756,"line":676,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 26249867344 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 26249867344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"95.sysrst_ctrl_combo_detect_with_pre_cond.84698459973937875750736755302580827774150438654030226521753670253702180176333","seed":84698459973937875750736755302580827774150438654030226521753670253702180176333,"line":704,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 85799277665 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 85799277665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"28.sysrst_ctrl_combo_detect_with_pre_cond.83695195611180923247551630378977931579011001867515439449074255877413996097243","seed":83695195611180923247551630378977931579011001867515439449074255877413996097243,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 17585509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0\n","UVM_INFO @ 17790509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 17810509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 19950509353 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:139) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] pulse_width_l = 45\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"58.sysrst_ctrl_combo_detect_with_pre_cond.101673275770188270271844164512800275146805814496998732892980804352555342091556","seed":101673275770188270271844164512800275146805814496998732892980804352555342091556,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 14346075102 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4 \n","UVM_INFO @ 14346075102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"64.sysrst_ctrl_combo_detect_with_pre_cond.101106611428592982726569851612505563723863727694577688892127938104767083966711","seed":101106611428592982726569851612505563723863727694577688892127938104767083966711,"line":694,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 17883732835 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o \n","UVM_INFO @ 17883732835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":392,"total":410,"percent":95.60975609756098}