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expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.68005244765256478552722488590998648248540713550243921182174748591467671180929","seed":68005244765256478552722488590998648248540713550243921182174748591467671180929,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3167.315928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"1.chip_sw_flash_ctrl_lc_rw_en.31007954204889542839220950377763447289866161939302511321658668092397740213558","seed":31007954204889542839220950377763447289866161939302511321658668092397740213558,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 4037.286612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"2.chip_sw_flash_ctrl_lc_rw_en.60466590042593434396621861687149144083439535183060215262261693153972200745736","seed":60466590042593434396621861687149144083439535183060215262261693153972200745736,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 2884.310824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.14216575236706361893431381663835371933206112514806959411798962263426338317777","seed":14216575236706361893431381663835371933206112514806959411798962263426338317777,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 8788.536906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.28479735611035929361039502762439353309806702860719038660044144860620561058087","seed":28479735611035929361039502762439353309806702860719038660044144860620561058087,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 9879.914560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.115513388511748847430519368951083723788745223018559662510976134899245895743920","seed":115513388511748847430519368951083723788745223018559662510976134899245895743920,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7404.191843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.14398399018530712273783515241446375614127239991448886347972159028326633489424","seed":14398399018530712273783515241446375614127239991448886347972159028326633489424,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 4112.095518 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 4112.095518 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.75155637647175986232460705233304129987459389515582961453299017998565236954662","seed":75155637647175986232460705233304129987459389515582961453299017998565236954662,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.50694482913698306156723807543695155285393940905574263983636262438233704934191","seed":50694482913698306156723807543695155285393940905574263983636262438233704934191,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 12544.699969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.96321311156525606969629766926112313084668284681197435176179989919039206678833","seed":96321311156525606969629766926112313084668284681197435176179989919039206678833,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 13507.392368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.86866795726502040074434074046232548556102738514419651616646214789823202349903","seed":86866795726502040074434074046232548556102738514419651616646214789823202349903,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 9569.575473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.90706614166172706781414524305886039685566903317056667567151771922465785049296","seed":90706614166172706781414524305886039685566903317056667567151771922465785049296,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 9050.692803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.74123367653126898009724237431176340524596351089036891693975532993402173047420","seed":74123367653126898009724237431176340524596351089036891693975532993402173047420,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 12085.346081 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.52534643714086956669059572840250688495515935316898559260580948471583229497379","seed":52534643714086956669059572840250688495515935316898559260580948471583229497379,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7091.707108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.105149552010648669412016899843508534730769094486920039107901655901424937241477","seed":105149552010648669412016899843508534730769094486920039107901655901424937241477,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 13129.569080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.64887653890547050018937608082308663233162440895526123193372445187206778385692","seed":64887653890547050018937608082308663233162440895526123193372445187206778385692,"line":369,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 13572.023036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.22168206926937053508463125857264213521391865693151556557384290289230170235585","seed":22168206926937053508463125857264213521391865693151556557384290289230170235585,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 6492.732905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.13077977999240401310627416766039200164131748250756442590800777278723848740241","seed":13077977999240401310627416766039200164131748250756442590800777278723848740241,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 3177.841432 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 3177.841432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.69973122601666537051304143712272755140583204009698168346583233234377005779053","seed":69973122601666537051304143712272755140583204009698168346583233234377005779053,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2180.142886 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2180.142886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.53590933174539001968432078619251805770456776786004429425635360999340924328746","seed":53590933174539001968432078619251805770456776786004429425635360999340924328746,"line":303,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2365.073643 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2365.073643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.111997810540294285207307420108019618572472283757051531724936973087463983909736","seed":111997810540294285207307420108019618572472283757051531724936973087463983909736,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5786.317000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5786.317000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.51335009988857544971321055660257790662354606334738746521617465815758754887631","seed":51335009988857544971321055660257790662354606334738746521617465815758754887631,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10533.748000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10533.748000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.33046779627712886358397472455227289537157412436354308673279897190344932357236","seed":33046779627712886358397472455227289537157412436354308673279897190344932357236,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 7638.484000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7638.484000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"0.chip_sw_sysrst_ctrl_reset.102375127287646105017455238625418759034547203076274566450607221404312841167754","seed":102375127287646105017455238625418759034547203076274566450607221404312841167754,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 25716.708500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 25716.708500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.102116814971323673390199425782572427876781152431012139262858729025104804007959","seed":102116814971323673390199425782572427876781152431012139262858729025104804007959,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8511.435000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8511.435000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.82290348661451944384267226041175555353900491464496807179873107672185955697917","seed":82290348661451944384267226041175555353900491464496807179873107672185955697917,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 5774.086500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 5774.086500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.89433918882196105912106289950101514062420496767944415337481325136645838514201","seed":89433918882196105912106289950101514062420496767944415337481325136645838514201,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10215.942500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10215.942500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.52392000173858723764239902014476152730887092456316165691455512560152619065100","seed":52392000173858723764239902014476152730887092456316165691455512560152619065100,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 9279.270000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9279.270000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"1.chip_sw_sysrst_ctrl_reset.101861450465940070792371082714177957692623958988109248840632771685280368544150","seed":101861450465940070792371082714177957692623958988109248840632771685280368544150,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 22664.837500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 22664.837500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.109049580060599032875969323077574266498285181266069885059944389973382073318231","seed":109049580060599032875969323077574266498285181266069885059944389973382073318231,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7875.766000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7875.766000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.57243810010825696823624877671985698664262723594421635588720656409478334751422","seed":57243810010825696823624877671985698664262723594421635588720656409478334751422,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 12993.978000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 12993.978000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.77954391038892046500849237818824349274355824236586377277283906772288152124908","seed":77954391038892046500849237818824349274355824236586377277283906772288152124908,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6585.536000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6585.536000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_por_reset.72787629169003678146034672530177800923291120525007175899734257955072722598160","seed":72787629169003678146034672530177800923291120525007175899734257955072722598160,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 9078.271000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9078.271000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.31464289933326135775616915999728051936244296127783982272900609653007983490323","seed":31464289933326135775616915999728051936244296127783982272900609653007983490323,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 11003.040000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 11003.040000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"2.chip_sw_sysrst_ctrl_reset.16881079519029654005580792132664567280337895813188727343328493573473584490267","seed":16881079519029654005580792132664567280337895813188727343328493573473584490267,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 24067.122500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 24067.122500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.8893252423149388163826717985730516471408454450961602537370982659110499698068","seed":8893252423149388163826717985730516471408454450961602537370982659110499698068,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7422.540000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7422.540000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.108899362396408104274003878827284116726160444237479142051302434313425285018168","seed":108899362396408104274003878827284116726160444237479142051302434313425285018168,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3438.434900 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3438.434900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.47567684909907822929370471627604002215758330518230496172021133287470305008636","seed":47567684909907822929370471627604002215758330518230496172021133287470305008636,"line":341,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 13005.753010 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 13005.753010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.11894041912488582647658867265589548386338891276582918861312089825443042038575","seed":11894041912488582647658867265589548386338891276582918861312089825443042038575,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3142.885561 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3142.885561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.94798836338373321226771631575538965091981351455503540815604282948921288428862","seed":94798836338373321226771631575538965091981351455503540815604282948921288428862,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 4297.873549 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 4297.873549 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.26113345685231511694817886501696234038756805909048481952156950569115453834064","seed":26113345685231511694817886501696234038756805909048481952156950569115453834064,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3320.503788 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3320.503788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.5224316612421953161337841437081951739456639808578497039041054212286405554496","seed":5224316612421953161337841437081951739456639808578497039041054212286405554496,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.15694706143513926905335096371646413982083865790664867435112513805846872712974","seed":15694706143513926905335096371646413982083865790664867435112513805846872712974,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.59885720307148655392252618663803167537895290664910608133084425826763446513749","seed":59885720307148655392252618663803167537895290664910608133084425826763446513749,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.26792402445183884534801043278577828908999729895684722364954580140041280519909","seed":26792402445183884534801043278577828908999729895684722364954580140041280519909,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.1826113644489924039354135351662985466962409727465033076240070573690486201555","seed":1826113644489924039354135351662985466962409727465033076240070573690486201555,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.42509955212871400347300025492474424037844806389834613713180909436783488394144","seed":42509955212871400347300025492474424037844806389834613713180909436783488394144,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.75477200632506116363033220443220448172335660542847189548627599450938874312135","seed":75477200632506116363033220443220448172335660542847189548627599450938874312135,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.46510053157191923718623868641339596416431511306234233008637818706605214804436","seed":46510053157191923718623868641339596416431511306234233008637818706605214804436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.110936250228233166924062488503868354504327352293342943480337886689932694255894","seed":110936250228233166924062488503868354504327352293342943480337886689932694255894,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.49614363135979714743503011665882470319923370140769152012799666184946101767161","seed":49614363135979714743503011665882470319923370140769152012799666184946101767161,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.29473467072832911157812380235284202831993160940822917074670191346656093684236","seed":29473467072832911157812380235284202831993160940822917074670191346656093684236,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.87392682330263352501329339228719525000622226957763449154148698549434265878294","seed":87392682330263352501329339228719525000622226957763449154148698549434265878294,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.69420949562798295603369779863886045708907114255126590393752820320566064776236","seed":69420949562798295603369779863886045708907114255126590393752820320566064776236,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 4190.692190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.9625429197521725845625809959003270097599303804437279568241950835577824254339","seed":9625429197521725845625809959003270097599303804437279568241950835577824254339,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3622.221624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.33580859158746194888306116281567747480289506661565319023289729588486020131281","seed":33580859158746194888306116281567747480289506661565319023289729588486020131281,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3580.888712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.15603577116017542889249426173804650677990638954251358311930559247609417761375","seed":15603577116017542889249426173804650677990638954251358311930559247609417761375,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3001.699116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.51031483810729953516422052642328161499787568887729572711777060980461207045406","seed":51031483810729953516422052642328161499787568887729572711777060980461207045406,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3718.280000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.110766422585803675207376935609355484281604099766368817459861084960094285025571","seed":110766422585803675207376935609355484281604099766368817459861084960094285025571,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3588.368965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.65496755202116009812707674985547008303351894504609175657134478856149559072102","seed":65496755202116009812707674985547008303351894504609175657134478856149559072102,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3439.592703 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.50412712701745973725248714076606463376369372691685235366665300654578903237241","seed":50412712701745973725248714076606463376369372691685235366665300654578903237241,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3977.019592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.19158405276656726677129391973484146792197204552793510103058760140301472024242","seed":19158405276656726677129391973484146792197204552793510103058760140301472024242,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3389.829364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2056763352411811263993598005392500279593525549219103137667225629743842786733","seed":2056763352411811263993598005392500279593525549219103137667225629743842786733,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3720.330054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.79558914509696691064589655006139127640344510910238694545276254362274902459196","seed":79558914509696691064589655006139127640344510910238694545276254362274902459196,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3541.793361 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.55599480102343236035482588713278693758898774017777107833670478568232302062008","seed":55599480102343236035482588713278693758898774017777107833670478568232302062008,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3213.483149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.36961033256540697897935183865715100825533367853064407255380781687934493652507","seed":36961033256540697897935183865715100825533367853064407255380781687934493652507,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3655.486504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.11883606838066826726280145950369338695799095358772890599696900385163334440832","seed":11883606838066826726280145950369338695799095358772890599696900385163334440832,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2507.928792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.65361468220146530625255294654877202175899647528053837092555721112285867515044","seed":65361468220146530625255294654877202175899647528053837092555721112285867515044,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2855.485547 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.101855076261229611173090615772018866586730400369151803755177422253650193906793","seed":101855076261229611173090615772018866586730400369151803755177422253650193906793,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2351.901298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.23159129770998037097459269849357777363163637156068661274890122890454581109003","seed":23159129770998037097459269849357777363163637156068661274890122890454581109003,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3783.799076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.110661209995490016613393684909633404843177930412222580771915309797857645394345","seed":110661209995490016613393684909633404843177930412222580771915309797857645394345,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4121.091050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.93292470229069447334896217708504085454005406199993385896514261336489157896229","seed":93292470229069447334896217708504085454005406199993385896514261336489157896229,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3253.719170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.70767773390336425410265781539466583858285890205498730698929775699411862235537","seed":70767773390336425410265781539466583858285890205498730698929775699411862235537,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3208.912272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.46931421639394442880412993634303698946734542250882186056531365101274208665769","seed":46931421639394442880412993634303698946734542250882186056531365101274208665769,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2793.951698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.42610124838624002533285305669024335353423762477204769442667380236092707041999","seed":42610124838624002533285305669024335353423762477204769442667380236092707041999,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3638.738798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.94684027715692563179047926852435501269114863318336776805226627888640326276878","seed":94684027715692563179047926852435501269114863318336776805226627888640326276878,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3888.805785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.8812103261478533837834895465661526312679685911699582575692646964347761003313","seed":8812103261478533837834895465661526312679685911699582575692646964347761003313,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3169.701484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.35126066155326954471261513823388402015721924277894848154395263481763861127422","seed":35126066155326954471261513823388402015721924277894848154395263481763861127422,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3702.895840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.44916975347672434244820518019210667819216808500097478714546763537703450993996","seed":44916975347672434244820518019210667819216808500097478714546763537703450993996,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2720.666777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.32842467185978883857443270354244370522007050968353837057209177002120037874107","seed":32842467185978883857443270354244370522007050968353837057209177002120037874107,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3135.377289 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.108402181906027031323128830523221633276054061739059713443176349702423914936289","seed":108402181906027031323128830523221633276054061739059713443176349702423914936289,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3860.613856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.97077143512476066454236533725864754056885900348632353226478255828011070374444","seed":97077143512476066454236533725864754056885900348632353226478255828011070374444,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3922.165550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.6639775072183869126160162613776057188693541727996436279655654391434681368635","seed":6639775072183869126160162613776057188693541727996436279655654391434681368635,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2837.357648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.64878262948599304240015397164276842289836178696968471414855393407841203439425","seed":64878262948599304240015397164276842289836178696968471414855393407841203439425,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3794.339154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.68605671318166019586683767792615045386375446495898685788736149863024294986175","seed":68605671318166019586683767792615045386375446495898685788736149863024294986175,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3785.075352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.63697176758329706665070862313244211886030209715540259990156704591818226361691","seed":63697176758329706665070862313244211886030209715540259990156704591818226361691,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3033.991100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.13354067209071686593871009948691261943225509099264881573394138919447716078990","seed":13354067209071686593871009948691261943225509099264881573394138919447716078990,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3759.807292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.89342475624869055842906758697400009974598552335013727411416153724450189182411","seed":89342475624869055842906758697400009974598552335013727411416153724450189182411,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3308.478882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.107505509680154716795571680444943510952333475191695535358248221489411409010509","seed":107505509680154716795571680444943510952333475191695535358248221489411409010509,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3497.850125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.64504364620777041357791527484483221535240932299587344729179101281214121412592","seed":64504364620777041357791527484483221535240932299587344729179101281214121412592,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3059.343008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.20102100840240040550481240740955209176924578935399122707684818619212227779838","seed":20102100840240040550481240740955209176924578935399122707684818619212227779838,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3186.651526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.63594513411855886436896376822016676473572961001088516169697656068232653574965","seed":63594513411855886436896376822016676473572961001088516169697656068232653574965,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3360.754602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.109851593717225883623520294106460494371107057739780334195020004196492318145995","seed":109851593717225883623520294106460494371107057739780334195020004196492318145995,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2980.588543 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.99269287690882531435501373355252098911358296856288334753587828079535050841533","seed":99269287690882531435501373355252098911358296856288334753587828079535050841533,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3479.551460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.100216005797480078820438344602003075827541501060783590347836784346797687608068","seed":100216005797480078820438344602003075827541501060783590347836784346797687608068,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4006.228355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.10037576146280093536076822890666372938117088335787423290515261359136520113919","seed":10037576146280093536076822890666372938117088335787423290515261359136520113919,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3750.178550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663787466904747463590075555956374893560684635902768161641053359552724150787","seed":3663787466904747463590075555956374893560684635902768161641053359552724150787,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2445.858420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3594580028602908857359189689516774500159695008501506453854757723869273600024","seed":3594580028602908857359189689516774500159695008501506453854757723869273600024,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3481.751036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.57513627513148020153845608661604076569125350430243692206200377709490724061652","seed":57513627513148020153845608661604076569125350430243692206200377709490724061652,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3305.423790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.93917095238366103464906594958024929138193050979033041044769050218189046461605","seed":93917095238366103464906594958024929138193050979033041044769050218189046461605,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3195.779688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.47739203633338219217248769728318788091298741901681717786694329651877773302087","seed":47739203633338219217248769728318788091298741901681717786694329651877773302087,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2919.427040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.69674434929730437223153746415586097809987035361383654285100497418242453816353","seed":69674434929730437223153746415586097809987035361383654285100497418242453816353,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3422.773084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.290015774053198792383039046351622509092700940759678591938298659007398195372","seed":290015774053198792383039046351622509092700940759678591938298659007398195372,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3037.867507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.57216797006446051307635184115277146074729507880647682669278428698447871460150","seed":57216797006446051307635184115277146074729507880647682669278428698447871460150,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3610.080888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.38004868089273932568569741982572896400563726074694272185636125611532122325911","seed":38004868089273932568569741982572896400563726074694272185636125611532122325911,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3461.488346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.15023340343583608911965853422710030200303674422756544132257638560286009234259","seed":15023340343583608911965853422710030200303674422756544132257638560286009234259,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2804.215264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.72704337071676252717425807748273094885488645096638265999290442490278875018424","seed":72704337071676252717425807748273094885488645096638265999290442490278875018424,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4215.653317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.57706226770156759673567652410582080830919375564359427002593022274365134484334","seed":57706226770156759673567652410582080830919375564359427002593022274365134484334,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2697.059592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.112428787552977103104058419724865814177456584402766408067809246727147800239200","seed":112428787552977103104058419724865814177456584402766408067809246727147800239200,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3778.716760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.62579257349901061123597847627820884839557233309301243989986662864380702635067","seed":62579257349901061123597847627820884839557233309301243989986662864380702635067,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3787.047630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.110902564683207719745158485831286634777950331515967165417974139880999078605151","seed":110902564683207719745158485831286634777950331515967165417974139880999078605151,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3111.642172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.21900036659386538987051650162776488995353318920765778545194973882135294101190","seed":21900036659386538987051650162776488995353318920765778545194973882135294101190,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3332.670285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.31996738661086790091844923542031940831390386832711908918015135894200611906475","seed":31996738661086790091844923542031940831390386832711908918015135894200611906475,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3124.407999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.107758028544216083295708235774092329196925742620340773478613438215446857854995","seed":107758028544216083295708235774092329196925742620340773478613438215446857854995,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3886.485432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.78556305558323403646469869483406193816365303139196657588784831144276159082640","seed":78556305558323403646469869483406193816365303139196657588784831144276159082640,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3866.607071 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.26411361567382277871238605861887577354288845852809338652388918906026167701178","seed":26411361567382277871238605861887577354288845852809338652388918906026167701178,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3438.534626 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.102824319806244085281877948772744423056334285920660112062351584101281840718833","seed":102824319806244085281877948772744423056334285920660112062351584101281840718833,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3068.405532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.31657473061731607275813156049270154906946770002639268686344596016060610286718","seed":31657473061731607275813156049270154906946770002639268686344596016060610286718,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3740.158124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.79631347275500791482246889434960319511210924597878092856513012196975149919014","seed":79631347275500791482246889434960319511210924597878092856513012196975149919014,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3832.590880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.92331573916907748791321778040915691108421483695082887894634044224297521282947","seed":92331573916907748791321778040915691108421483695082887894634044224297521282947,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4048.034543 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.106633124335428343697732457123179441804260254707312237688719043796625871333337","seed":106633124335428343697732457123179441804260254707312237688719043796625871333337,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3774.132984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.82538576276766439758563148265296124741331655632231942212124628854361692064252","seed":82538576276766439758563148265296124741331655632231942212124628854361692064252,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3776.201184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.15090152273232761831649545670398451915759998182830530854516398408485748196881","seed":15090152273232761831649545670398451915759998182830530854516398408485748196881,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3235.775110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.90268839549336672001754712430853874544071176665103821091183686113098786663089","seed":90268839549336672001754712430853874544071176665103821091183686113098786663089,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3162.045695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.86420611566833788434221521149078535658016330479559266360047556996162055682872","seed":86420611566833788434221521149078535658016330479559266360047556996162055682872,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3066.370776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.15474969419683716323768451447705295318177508011112149937610591477137563790636","seed":15474969419683716323768451447705295318177508011112149937610591477137563790636,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3550.821730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.10582857424990054235861253365253171055344656636792292535860039540934593242527","seed":10582857424990054235861253365253171055344656636792292535860039540934593242527,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3635.400480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.103035347376098260405718460051180407872757498260191867960917264939106896651403","seed":103035347376098260405718460051180407872757498260191867960917264939106896651403,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2893.934748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.31601511972756500422498497099118795010399333210357316568532887638193831144583","seed":31601511972756500422498497099118795010399333210357316568532887638193831144583,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4088.946059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.44137275409459036120466756516735817313712773983930054866697943190575744584404","seed":44137275409459036120466756516735817313712773983930054866697943190575744584404,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3146.207177 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.44003231408333852586890968363239088646305174441356654103107815484602277329816","seed":44003231408333852586890968363239088646305174441356654103107815484602277329816,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4043.059124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.80490337514104229406524178635480902034239625932694701846803990242395404123037","seed":80490337514104229406524178635480902034239625932694701846803990242395404123037,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3289.876399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.31173109652816957684625967411417032695896036876459899282608739504781112461046","seed":31173109652816957684625967411417032695896036876459899282608739504781112461046,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2857.793548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.62709335870850121322118508247517415470069767921948389104832280013628644164244","seed":62709335870850121322118508247517415470069767921948389104832280013628644164244,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3368.457084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.20508704691842560322272924277730954159192898674252374945293716489347065939477","seed":20508704691842560322272924277730954159192898674252374945293716489347065939477,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4364.848432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.97119280399040821547015463256184834312013363918241302751890819435923401622921","seed":97119280399040821547015463256184834312013363918241302751890819435923401622921,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3424.442605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.69811010519671893629363630394130092050093011805842821004904043924822955251108","seed":69811010519671893629363630394130092050093011805842821004904043924822955251108,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3490.841070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.112675369326041851299667479605960817269867614198383985911067599585280504468441","seed":112675369326041851299667479605960817269867614198383985911067599585280504468441,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3532.286565 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.113972521956763937023294958338862209048773974578507763005762964915103008289211","seed":113972521956763937023294958338862209048773974578507763005762964915103008289211,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3641.590740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.49249125628925002757190021460009865924073850410816615028909525095739194490303","seed":49249125628925002757190021460009865924073850410816615028909525095739194490303,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4187.519950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.41375695981750436490331486122808663422837796233269821657481267072891110960710","seed":41375695981750436490331486122808663422837796233269821657481267072891110960710,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2996.913153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.31608889579177494998818205034725886524610459633465257966797058247919261193812","seed":31608889579177494998818205034725886524610459633465257966797058247919261193812,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3322.394951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.91887352481295524182377303672738852870467972207130065554249608688968550021301","seed":91887352481295524182377303672738852870467972207130065554249608688968550021301,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4282.734768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.102989199608760641648845749575327148776177390180455649835160461256889251805545","seed":102989199608760641648845749575327148776177390180455649835160461256889251805545,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3414.424888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.33202417944440663957697480844129598771666593560902828127581999468155974649319","seed":33202417944440663957697480844129598771666593560902828127581999468155974649319,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.335166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"0.chip_sw_keymgr_sideload_otbn.91782738253154167205686871979005509318299600534067402269252764160048414219765","seed":91782738253154167205686871979005509318299600534067402269252764160048414219765,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.221726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.73951808080791025203243673366849056652587341521494924688595640440363789692001","seed":73951808080791025203243673366849056652587341521494924688595640440363789692001,"line":354,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.380148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"1.chip_sw_keymgr_sideload_otbn.92568969154998032870569869083863527306557370382228432959929882395411721269986","seed":92568969154998032870569869083863527306557370382228432959929882395411721269986,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.975407 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"2.chip_sw_hmac_multistream.25955709217758666061958984980460622031006671137550816239372862988155442731319","seed":25955709217758666061958984980460622031006671137550816239372862988155442731319,"line":348,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.599964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"2.chip_sw_keymgr_sideload_otbn.59679922853302727875042648927999383632960795980768185233030123049716312595436","seed":59679922853302727875042648927999383632960795980768185233030123049716312595436,"line":334,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.663097 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.49090983146857294190985532474039465812074726477405261902005582246301802146599","seed":49090983146857294190985532474039465812074726477405261902005582246301802146599,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34228) { a_addr: 'h10574  a_data: 'hb0fb2b3b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h18a97  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1982.294720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.72947247895491617616818397154525046976502810198423746563011327638962336555178","seed":72947247895491617616818397154525046976502810198423746563011327638962336555178,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30512) { a_addr: 'h10780  a_data: 'hb4760439  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1a945  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3083.628200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.78516605638332795151205617169576016952554772872742265775413862816774642121676","seed":78516605638332795151205617169576016952554772872742265775413862816774642121676,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32710) { a_addr: 'h10428  a_data: 'hfb7037ea  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h199af  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2820.788108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"1.chip_csr_mem_rw_with_rand_reset.74148220888769830536704867893285314268410587212597463915240618050743972058747","seed":74148220888769830536704867893285314268410587212597463915240618050743972058747,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30910) { a_addr: 'h1064c  a_data: 'hbe1b2b8b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h1ae4a  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2922.338150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.25633442198532876998089163171401637328389338151475772835660839157229763030618","seed":25633442198532876998089163171401637328389338151475772835660839157229763030618,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40286) { a_addr: 'h105a0  a_data: 'hc8cec6c6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1ba8b  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2058.493038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.27010128171089384971262148901911818764563797459303289702921286896986952941248","seed":27010128171089384971262148901911818764563797459303289702921286896986952941248,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30602) { a_addr: 'h10664  a_data: 'h9feb254b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h1a25f  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2369.140871 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.51477589781169867839947048523492908893115875745799085876616892594410128144234","seed":51477589781169867839947048523492908893115875745799085876616892594410128144234,"line":242,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@209352) { a_addr: 'h10518  a_data: 'h250f7568  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1a297  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 7513.335632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.98630770424705348319737142685362866190808212018589094213782173448779683895072","seed":98630770424705348319737142685362866190808212018589094213782173448779683895072,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@39314) { a_addr: 'h10534  a_data: 'h8f97d3af  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1a242  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2297.800609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"4.chip_csr_mem_rw_with_rand_reset.63099089051226381188709318428038012899815576469269585903907326582361689502533","seed":63099089051226381188709318428038012899815576469269585903907326582361689502533,"line":224,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31508) { a_addr: 'h104c8  a_data: 'hbabff8c6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h19955  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3110.347673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.92153916045592559558227874616553462137764598808350153505950413903012691281000","seed":92153916045592559558227874616553462137764598808350153505950413903012691281000,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33064) { a_addr: 'h10730  a_data: 'h987afe44  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1a5fd  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2567.127474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.102353038363419525559985995933829986792609468802583431836133948352877722025916","seed":102353038363419525559985995933829986792609468802583431836133948352877722025916,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36564) { a_addr: 'h1058c  a_data: 'h6854a184  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h4  a_user: 'h1ba3a  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3599.661082 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.65047796878575531136635804767111335108241596832844861177688209889479990625894","seed":65047796878575531136635804767111335108241596832844861177688209889479990625894,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30240) { a_addr: 'h10788  a_data: 'h57629781  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1bda8  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2284.790522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.93122525594695184513216886402300523735304597339809508805008817039706558371079","seed":93122525594695184513216886402300523735304597339809508805008817039706558371079,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32442) { a_addr: 'h1067c  a_data: 'h65220f08  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h19212  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2871.648196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.85479429149197086707410654910689843458354269679421982950126010634199393609712","seed":85479429149197086707410654910689843458354269679421982950126010634199393609712,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33220) { a_addr: 'h10470  a_data: 'h90034340  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1811a  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2380.702760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.94192674929909709872809876423243810092788691880384356907759272336177264645157","seed":94192674929909709872809876423243810092788691880384356907759272336177264645157,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36242) { a_addr: 'h106b4  a_data: 'h85ee42d5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3e  a_opcode: 'h4  a_user: 'h19ee7  d_param: 'h0  d_source: 'h3e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2517.916096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.48213256561157283564182984732601234554833480555706740837014570783893771542631","seed":48213256561157283564182984732601234554833480555706740837014570783893771542631,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31760) { a_addr: 'h10694  a_data: 'he60c5414  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1867f  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2156.677260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.51740121589794348743154377347260764411402507475997274834863408232139449126723","seed":51740121589794348743154377347260764411402507475997274834863408232139449126723,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32682) { a_addr: 'h1057c  a_data: 'h7369a2c3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h19e01  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2779.165307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.30807558205906896639479414622193355636163268322628433897844987667465741207677","seed":30807558205906896639479414622193355636163268322628433897844987667465741207677,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30556) { a_addr: 'h105ac  a_data: 'h8c649609  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1a2e8  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2358.175215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.75028011256321964408520281614542363120248436095285986542134048782865897237909","seed":75028011256321964408520281614542363120248436095285986542134048782865897237909,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35544) { a_addr: 'h106c0  a_data: 'hf80b307d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h186d7  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3209.665336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"17.chip_tl_errors.12283219297775140684968135294136956183202996440744357115147709662657891368238","seed":12283219297775140684968135294136956183202996440744357115147709662657891368238,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35324) { a_addr: 'h10354  a_data: 'hf3197c90  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18a54  d_param: 'h0  d_source: 'h22  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2264.764876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.75001312384217837566821842286673455446250652869210902713387261090046896789601","seed":75001312384217837566821842286673455446250652869210902713387261090046896789601,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@232592) { a_addr: 'h10688  a_data: 'hb742ab43  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1badd  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3865.202609 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.59631412625220268539106209715467441022723265517321610818787187578435020961937","seed":59631412625220268539106209715467441022723265517321610818787187578435020961937,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33610) { a_addr: 'h10544  a_data: 'hd2d83728  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h1b6e0  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2603.073590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.28583449063358229035238102465583934347670300408841640162464172621105901839076","seed":28583449063358229035238102465583934347670300408841640162464172621105901839076,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33496) { a_addr: 'h10550  a_data: 'h7e2d82b5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h19e98  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3012.502398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.10401515907494456263025551473274621542645459441187130457543748508440626924107","seed":10401515907494456263025551473274621542645459441187130457543748508440626924107,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35746) { a_addr: 'h10700  a_data: 'hc84a309a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h19987  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2614.658860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.104886012892504269836328856421870969383493686901345012695202390997521205198483","seed":104886012892504269836328856421870969383493686901345012695202390997521205198483,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32312) { a_addr: 'h10440  a_data: 'hff90f8d4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1bd18  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2430.775890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.7785541745329966986566936821998764760012461512630271813250429359911673241178","seed":7785541745329966986566936821998764760012461512630271813250429359911673241178,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36696) { a_addr: 'h10558  a_data: 'hdc858c04  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h18a4c  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3096.471473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.30485573769456686776491909526939777121066772498087798720715115164059302998212","seed":30485573769456686776491909526939777121066772498087798720715115164059302998212,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34626) { a_addr: 'h104a8  a_data: 'hc07a63fa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1a956  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2903.850134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.70305162980270233341012330451378298624962240236893309215453250793708414503983","seed":70305162980270233341012330451378298624962240236893309215453250793708414503983,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35278) { a_addr: 'h10504  a_data: 'he73a6f67  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h19e4d  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3005.363218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.38686684270233713349177548094693312845842228080175258728832371154140284171982","seed":38686684270233713349177548094693312845842228080175258728832371154140284171982,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33680) { a_addr: 'h106b8  a_data: 'h65985e98  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h186ef  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3359.781900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.94279806976087233638695849676617197952782313441017396798629349231760574718489","seed":94279806976087233638695849676617197952782313441017396798629349231760574718489,"line":217,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33574) { a_addr: 'h10414  a_data: 'ha072a44d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h1bdfb  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3485.818024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.64739020832619757974332552634247221287598917854595762988004865807381857041692","seed":64739020832619757974332552634247221287598917854595762988004865807381857041692,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4766.928569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.88570185544090759291244405409236145408469128101101904914824993185340086137295","seed":88570185544090759291244405409236145408469128101101904914824993185340086137295,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4156.655258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.49209529488625831022539979581272738596219734860914088769698154852856695997302","seed":49209529488625831022539979581272738596219734860914088769698154852856695997302,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4732.773481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.54613236824425679675268434173693158521663629140316387233685109802412848474585","seed":54613236824425679675268434173693158521663629140316387233685109802412848474585,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["Another command (pid=3221767) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=3222856) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=3223379) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.111742549307409879058048270081466525152637080244733408693821432969279425901072","seed":111742549307409879058048270081466525152637080244733408693821432969279425901072,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=254948) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=257622) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_dev.16527113129703290224347582708435688933957774129203306345355987194412848483087","seed":16527113129703290224347582708435688933957774129203306345355987194412848483087,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod.111148603850143743605349775071252425555014728516499942477759808161508668116704","seed":111148603850143743605349775071252425555014728516499942477759808161508668116704,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.53577306018163769011984728177329200081665821241775380577999019345794715950378","seed":53577306018163769011984728177329200081665821241775380577999019345794715950378,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_good_rma.17130075448919358590080594737744719610966005714938358656417776274094655754904","seed":17130075448919358590080594737744719610966005714938358656417776274094655754904,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.110643676206287825936516316029074239444103999383605743902546093971605783386942","seed":110643676206287825936516316029074239444103999383605743902546093971605783386942,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=254948) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.519433735399889958867254580203282664572213344336748066421905206435388342963","seed":519433735399889958867254580203282664572213344336748066421905206435388342963,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.64192300806775967932080980076182476298538324071256845152264210387116740465241","seed":64192300806775967932080980076182476298538324071256845152264210387116740465241,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.39368603165366382041124082355098901496896250284490478191145710333789016283596","seed":39368603165366382041124082355098901496896250284490478191145710333789016283596,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_good_b_bad_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.48388479451612201188334870114370182206316642652827529982925705450331630304483","seed":48388479451612201188334870114370182206316642652827529982925705450331630304483,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.78176789987472509807922242574817858879625535142067493691986255868278691208017","seed":78176789987472509807922242574817858879625535142067493691986255868278691208017,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log","log_context":["Another command (pid=287528) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=289522) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=293113) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_dev","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.112506715505529927096906330309324448430936311676934049180756254108585478284955","seed":112506715505529927096906330309324448430936311676934049180756254108585478284955,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.86673949597842344790545269477120016769793746209014510296358311865478076997998","seed":86673949597842344790545269477120016769793746209014510296358311865478076997998,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.45873105283069756782188512060238517817631650681257680648574873152824579974181","seed":45873105283069756782188512060238517817631650681257680648574873152824579974181,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_boot_policy_valid_a_bad_b_good_rma","qual_name":"0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.101777923759104962966372911182387211953166218667012676854372196993821177173674","seed":101777923759104962966372911182387211953166218667012676854372196993821177173674,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"0.rom_e2e_asm_init_test_unlocked0.12115810152236206998142973766940545602680363046083985052485296004697385645340","seed":12115810152236206998142973766940545602680363046083985052485296004697385645340,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=254948) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=257622) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"0.rom_e2e_asm_init_dev.54409932899728608019165919966577146424810699658334402916224094529428602087434","seed":54409932899728608019165919966577146424810699658334402916224094529428602087434,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_dev/latest/run.log","log_context":["Another command (pid=404299) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=404857) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=404906) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"0.rom_e2e_asm_init_prod.111864110550844005876984878871201362270207965276239261486943259054903484120501","seed":111864110550844005876984878871201362270207965276239261486943259054903484120501,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log","log_context":["Another command (pid=409196) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=411321) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=410034) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"0.rom_e2e_asm_init_prod_end.31610622337522726838061750495672536327627051625253276772648252267722373617088","seed":31610622337522726838061750495672536327627051625253276772648252267722373617088,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=417036) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=417595) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"0.rom_e2e_asm_init_rma.32420352219207656888855540652264726558954991842463990422183292862574180410470","seed":32420352219207656888855540652264726558954991842463990422183292862574180410470,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_asm_init_rma/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=421932) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"0.rom_volatile_raw_unlock.84865896660454127369549212360482947130061226828580863358026262701238026817929","seed":84865896660454127369549212360482947130061226828580863358026262701238026817929,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=268468) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=269846) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=278999) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.2720064260720060559124717385316524135682062617176642952702482279681430820735","seed":2720064260720060559124717385316524135682062617176642952702482279681430820735,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=268468) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=269846) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=278999) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.34609037576820602603397937011748898828827715448085974583130834355912420182803","seed":34609037576820602603397937011748898828827715448085974583130834355912420182803,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=287528) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=289522) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=293113) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.79582799216318751823655805173082571787993650508774551704254814866127645366089","seed":79582799216318751823655805173082571787993650508774551704254814866127645366089,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=4153342) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"1.rom_e2e_asm_init_test_unlocked0.34110324789628638233184688949033809221089572401759893895919448821191658086290","seed":34110324789628638233184688949033809221089572401759893895919448821191658086290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=269846) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=278999) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=268284) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"1.rom_e2e_asm_init_dev.43199047396744774239558423577378783962369861380418785617512398096510545287045","seed":43199047396744774239558423577378783962369861380418785617512398096510545287045,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"1.rom_e2e_asm_init_prod.41214768221954989088579241937962019360917378464739624587174889297725576062704","seed":41214768221954989088579241937962019360917378464739624587174889297725576062704,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"1.rom_e2e_asm_init_prod_end.66108036051635063224014227240418349461856169986340094916208971104311777318125","seed":66108036051635063224014227240418349461856169986340094916208971104311777318125,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"1.rom_e2e_asm_init_rma.90196314003322851707825990508770828256995327417956958490219068357284615885857","seed":90196314003322851707825990508770828256995327417956958490219068357284615885857,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"1.rom_volatile_raw_unlock.114265424318043981844270432896112678447770285010857736023416231880362808381438","seed":114265424318043981844270432896112678447770285010857736023416231880362808381438,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=293113) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=286680) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=279330) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.49398077197231664432320767670826339414491489398348612358151106244945538925974","seed":49398077197231664432320767670826339414491489398348612358151106244945538925974,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=263232) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=268233) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=260418) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.7933825245682000960256586005403976565975748178702234679580493345990886228714","seed":7933825245682000960256586005403976565975748178702234679580493345990886228714,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=255312) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=279826) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=263232) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.73293200014523292934994500404142313636651347300986605554760437287111055435553","seed":73293200014523292934994500404142313636651347300986605554760437287111055435553,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=903556) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=903938) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_test_unlocked0","qual_name":"2.rom_e2e_asm_init_test_unlocked0.51864980172405068722532136323554068248601751434610925877448001740584688159890","seed":51864980172405068722532136323554068248601751434610925877448001740584688159890,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_test_unlocked0/latest/run.log","log_context":["Another command (pid=279330) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=293470) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=292241) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_dev","qual_name":"2.rom_e2e_asm_init_dev.47771632942994232332069716602536486704933380933165775252931033063563715188188","seed":47771632942994232332069716602536486704933380933165775252931033063563715188188,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod","qual_name":"2.rom_e2e_asm_init_prod.102933213727662159639468892594032216785429080022005578524230907614389549628819","seed":102933213727662159639468892594032216785429080022005578524230907614389549628819,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_prod_end","qual_name":"2.rom_e2e_asm_init_prod_end.39745496705541175835834023958479719952162838953645854303525401743280819304702","seed":39745496705541175835834023958479719952162838953645854303525401743280819304702,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_prod_end/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_asm_init_rma","qual_name":"2.rom_e2e_asm_init_rma.79496617992279924865064451561039212937864591517520285590993171563817730746682","seed":79496617992279924865064451561039212937864591517520285590993171563817730746682,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.27382210137604153886944812185379254322781491553076160260722674232455114735078","seed":27382210137604153886944812185379254322781491553076160260722674232455114735078,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["Another command (pid=295030) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=318685) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=317077) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_raw_unlock","qual_name":"2.rom_raw_unlock.77986296678493163579691184138089470399378229252088190852833169657540209073917","seed":77986296678493163579691184138089470399378229252088190852833169657540209073917,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log","log_context":["Another command (pid=268233) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=284702) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=257532) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.93642934037776529461140186683730828358764761011685801496682430031245475081025","seed":93642934037776529461140186683730828358764761011685801496682430031245475081025,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=284341) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=298336) is running. Waiting for it to complete on the server (server_pid=254957)...\n","Another command (pid=296852) is running. Waiting for it to complete on the server (server_pid=254957)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.51232817469121012950711473003335620393640615210069111533217205289808908822192","seed":51232817469121012950711473003335620393640615210069111533217205289808908822192,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.6030810897610340189929979691697352776476328933729438989484616629465231753381","seed":6030810897610340189929979691697352776476328933729438989484616629465231753381,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.8081862712562581458070386907333497790882854967014137050460005088101586342684","seed":8081862712562581458070386907333497790882854967014137050460005088101586342684,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.101399535810372789423341484620323337513772781900186263292005133968362347174226","seed":101399535810372789423341484620323337513772781900186263292005133968362347174226,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.45653636229164764310157597830108324779980702083876514875331692607388828121566","seed":45653636229164764310157597830108324779980702083876514875331692607388828121566,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.55584909481940754151608193183342070007029055653546981259820580208307629155154","seed":55584909481940754151608193183342070007029055653546981259820580208307629155154,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.28733686959497142423890007204619456041368287670936172648738508185928697220783","seed":28733686959497142423890007204619456041368287670936172648738508185928697220783,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.":[{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.68360418901682141009181781363145991158802997762517206105594312569727465479181","seed":68360418901682141009181781363145991158802997762517206105594312569727465479181,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 14184.911051 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.109653454293627829218991240464185726281579098991890609641633388848027434715507","seed":109653454293627829218991240464185726281579098991890609641633388848027434715507,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 14005.562214 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.85264542165867072622945812166877795116440481087235344356285393725600558941585","seed":85264542165867072622945812166877795116440481087235344356285393725600558941585,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 13212.937250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.":[{"name":"chip_sw_rv_core_ibex_lockstep_glitch","qual_name":"0.chip_sw_rv_core_ibex_lockstep_glitch.86832033339550659084468410141805189623166487944654123677645586408395986037851","seed":86832033339550659084468410141805189623166487944654123677645586408395986037851,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log","log_context":["UVM_INFO @ 2918.546887 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.3638438894646049306664233175170335028700874540321727576192371636170284683460","seed":3638438894646049306664233175170335028700874540321727576192371636170284683460,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15569.250732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"1.chip_sw_power_idle_load.14490459402092890693102734835574009178515799737949535008858206097374919975490","seed":14490459402092890693102734835574009178515799737949535008858206097374919975490,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15604.859884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"2.chip_sw_power_idle_load.73813941524542361409279543881379604341229673557925934361391057547925552118320","seed":73813941524542361409279543881379604341229673557925934361391057547925552118320,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15013.170040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.39650377722570042076037689916894925795053041875003808103401295231757492134726","seed":39650377722570042076037689916894925795053041875003808103401295231757492134726,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 16001.984612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"1.chip_sw_power_sleep_load.95001907292194546619326538697201433701406055448217290851739990567697239919637","seed":95001907292194546619326538697201433701406055448217290851739990567697239919637,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 14791.849456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.102376103643189650799220801120836176001716117998002656717649861237516457716207","seed":102376103643189650799220801120836176001716117998002656717649861237516457716207,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 15545.418380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.113923167207048892831573934184543050032539335908019267938538732778440962326440","seed":113923167207048892831573934184543050032539335908019267938538732778440962326440,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 15418.257658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.63757105879628207851498370801692425958537847437799916453723233270601820217693","seed":63757105879628207851498370801692425958537847437799916453723233270601820217693,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 11806.472901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.54009858005539246719619005515109116742672402098989971330990704537484048227327","seed":54009858005539246719619005515109116742672402098989971330990704537484048227327,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 13919.187651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.23529817678117034118993915209276773715022002398939659617893401488379980122649","seed":23529817678117034118993915209276773715022002398939659617893401488379980122649,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.114412695335861558106674505576182631213202104591764016618334308339480771200922","seed":114412695335861558106674505576182631213202104591764016618334308339480771200922,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.90831091828698432892629059490796483492797224775582135291223625394556628191659","seed":90831091828698432892629059490796483492797224775582135291223625394556628191659,"line":272,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed \"OpenTitan:*-*-*":[{"name":"rom_e2e_shutdown_exception_c","qual_name":"0.rom_e2e_shutdown_exception_c.61560134917488387819275350165582125928165679796591622920886945280236378552881","seed":61560134917488387819275350165582125928165679796591622920886945280236378552881,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 7896.437715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"1.rom_e2e_shutdown_exception_c.30831421539285247108351570489178479976184792350837222411651791222958478332299","seed":30831421539285247108351570489178479976184792350837222411651791222958478332299,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 6824.102553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_exception_c","qual_name":"2.rom_e2e_shutdown_exception_c.65105122658655970305550571035074664224459902446753170050403256528101145440958","seed":65105122658655970305550571035074664224459902446753170050403256528101145440958,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 5319.327553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed \"OpenTitan:*-*-*":[{"name":"rom_e2e_shutdown_output","qual_name":"0.rom_e2e_shutdown_output.28541434132247280405322813617417107936489856650456675667796263574634120240400","seed":28541434132247280405322813617417107936489856650456675667796263574634120240400,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 7965.551839 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"1.rom_e2e_shutdown_output.28744030055606254566756442665837923784399860438891783016354359095144175113670","seed":28744030055606254566756442665837923784399860438891783016354359095144175113670,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 9031.341148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"rom_e2e_shutdown_output","qual_name":"2.rom_e2e_shutdown_output.94697442067602069793266296671169764625309594398854874303792593301186981955245","seed":94697442067602069793266296671169764625309594398854874303792593301186981955245,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log","log_context":["\" == \"OpenTitan:4001-0002-01\n","\" \n","UVM_INFO @ 10807.910841 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.37455033825946863803461429679973235093409659930185857146370154086917760868492","seed":37455033825946863803461429679973235093409659930185857146370154086917760868492,"line":362,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.33896949438325532894087426617544530908962267726871575507980586077139930668132","seed":33896949438325532894087426617544530908962267726871575507980586077139930668132,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_dev.7771592262757950169872840627020700718458851537266258600385849230606242417502","seed":7771592262757950169872840627020700718458851537266258600385849230606242417502,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_dev","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.10704434164693165072202385144375029013425199017531657375308956617958853942516","seed":10704434164693165072202385144375029013425199017531657375308956617958853942516,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod.32203508702392953731894789074447015739176544731944111787634313382192745836101","seed":32203508702392953731894789074447015739176544731944111787634313382192745836101,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.43176707212081816274323748599280357298653375657184143853428134763741402794013","seed":43176707212081816274323748599280357298653375657184143853428134763741402794013,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_bad_rma.57743730363139489077196669876492087196961203253986882879112653950587404595850","seed":57743730363139489077196669876492087196961203253986882879112653950587404595850,"line":364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.104677739928986682997625480691125827265332118823451115260550318181661330290982","seed":104677739928986682997625480691125827265332118823451115260550318181661330290982,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.24779790830879373981804368211414607566684010516785420042609389455938877280632","seed":24779790830879373981804368211414607566684010516785420042609389455938877280632,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_bad_b_nothing_rma","qual_name":"0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.25670910570616029987978328959116811662044207938304354304317957538376941930283","seed":25670910570616029987978328959116811662044207938304354304317957538376941930283,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.59789365737563404449525443465513189937641082678896257246368092494411474313768","seed":59789365737563404449525443465513189937641082678896257246368092494411474313768,"line":325,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log","log_context":["UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_dev","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.105943871487776318940878077956516894544041035794365746807165100865890153352368","seed":105943871487776318940878077956516894544041035794365746807165100865890153352368,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode":[{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.94727160989686710451406943674419418944935544104235517816985212986550052676224","seed":94727160989686710451406943674419418944935544104235517816985212986550052676224,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.58293066991487862749076418497757325532307043708000059880471855071074856341994","seed":58293066991487862749076418497757325532307043708000059880471855071074856341994,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log","log_context":["UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_sigverify_always_a_nothing_b_bad_rma","qual_name":"0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.106494877772432890612054738099238953994004779949817884952256977557334444435454","seed":106494877772432890612054738099238953994004779949817884952256977557334444435454,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*])":[{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.48101246170581264721995831342105671328630763862549355718668538287047701855376","seed":48101246170581264721995831342105671328630763862549355718668538287047701855376,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["UVM_INFO @ 5295.310653 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.37114507647768254901107134524318430600507441689536445016538187418524347363321","seed":37114507647768254901107134524318430600507441689536445016538187418524347363321,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 17037.671652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_meas.57800921435715300593291293470389545732052205349967161343299796828797266983735","seed":57800921435715300593291293470389545732052205349967161343299796828797266983735,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 20669.102526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.57600524217420673596007611357899515168824778322086318424934331582262444390429","seed":57600524217420673596007611357899515168824778322086318424934331582262444390429,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 6990.164092 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 6990.164092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.10634125769357897222332902313576575882864731736811390806349416911402881618387","seed":10634125769357897222332902313576575882864731736811390806349416911402881618387,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5417.701370 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5417.701370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.52206072134880664888222151267728325385854789336336077656768383881412949163511","seed":52206072134880664888222151267728325385854789336336077656768383881412949163511,"line":327,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5807.172120 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5807.172120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'":[{"name":"chip_csr_hw_reset","qual_name":"0.chip_csr_hw_reset.26684741803290023196008067249296110020608165529469028261251902151153310204681","seed":26684741803290023196008067249296110020608165529469028261251902151153310204681,"line":223,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest/run.log","log_context":["UVM_ERROR @ 3497.901498 us: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A\n","UVM_INFO @ 3497.901498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.20593701598380723825938399604358820236155785852427148762653396536246781313346","seed":20593701598380723825938399604358820236155785852427148762653396536246781313346,"line":329,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["host_rsp:\n","-------------------------------------------------------------------------\n","Name                               Type              Size  Value         \n","-------------------------------------------------------------------------\n"]}],"UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high.":[{"name":"chip_sw_sysrst_ctrl_ec_rst_l","qual_name":"1.chip_sw_sysrst_ctrl_ec_rst_l.67225676052881063238917867779217505287257279718611578356351717175751447420360","seed":67225676052881063238917867779217505287257279718611578356351717175751447420360,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log","log_context":["UVM_INFO @ 5010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:357)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.88722038856371056988473427621258828711609028371397503642330888346830320375055","seed":88722038856371056988473427621258828711609028371397503642330888346830320375055,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3442.714290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.84109358120203621077581517240377097643717741140062301883794537544126288884988","seed":84109358120203621077581517240377097643717741140062301883794537544126288884988,"line":307,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2572.627160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.33853568681253765546585072970691746688230071156158990439375490942712050441153","seed":33853568681253765546585072970691746688230071156158990439375490942712050441153,"line":215,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 2532.180635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.56876834602691472828486997568982271236665560330118372403600172621892416661294","seed":56876834602691472828486997568982271236665560330118372403600172621892416661294,"line":226,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 4432.201600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]":[{"name":"chip_sw_sleep_pin_mio_dio_val","qual_name":"2.chip_sw_sleep_pin_mio_dio_val.55065124963423221043420423803949954006028842211365750516073546595564397223975","seed":55065124963423221043420423803949954006028842211365750516073546595564397223975,"line":451,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log","log_context":["UVM_INFO @ 3714.282000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_transition","qual_name":"2.chip_sw_lc_ctrl_transition.80118445626424295480360417142456061361475935899927799460076907661444267723053","seed":80118445626424295480360417142456061361475935899927799460076907661444267723053,"line":305,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 26905.208838 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"2.chip_sw_lc_ctrl_rand_to_scrap.51567654964225504284747814014313797495576919900670342526415842756616311336456","seed":51567654964225504284747814014313797495576919900670342526415842756616311336456,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_INFO @ 26555.297304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(pend_req[h2d.a_source].pend == *)'":[{"name":"rom_e2e_keymgr_init_rom_ext_no_meas","qual_name":"2.rom_e2e_keymgr_init_rom_ext_no_meas.66634215915738850948319322205977928114862851854072071877015864865729245628300","seed":66634215915738850948319322205977928114862851854072071877015864865729245628300,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log","log_context":["UVM_ERROR @ 3075.928038 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M\n","UVM_INFO @ 3075.928038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"17.chip_sw_all_escalation_resets.16753513839228534053810460526221286496786255137404868385344067846977953533637","seed":16753513839228534053810460526221286496786255137404868385344067846977953533637,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4205.931026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"42.chip_sw_all_escalation_resets.67947963627721292174502594094055193595457818362311331452763492243672438247001","seed":67947963627721292174502594094055193595457818362311331452763492243672438247001,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3676.973496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"54.chip_sw_all_escalation_resets.110656803163524246667052179908766508022574544298402025584519714771652200748547","seed":110656803163524246667052179908766508022574544298402025584519714771652200748547,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4330.352688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"27.chip_sw_all_escalation_resets.35355542419572149476563449654405024643201678123658313332046202356311008185966","seed":35355542419572149476563449654405024643201678123658313332046202356311008185966,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4326.842252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1710,"total":2005,"percent":85.28678304239402}