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[UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"6.otbn_stress_all_with_rand_reset.56585279100996868750210936317241013813480864172764914860314722134030331935453","seed":56585279100996868750210936317241013813480864172764914860314722134030331935453,"line":228,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1106967196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"5.otbn_stress_all_with_rand_reset.12646816793191080559332180526414710717817863284265248807104641809550046734377","seed":12646816793191080559332180526414710717817863284265248807104641809550046734377,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.69181940124676584827927000345354563548035706761107029975435547852199482974493","seed":69181940124676584827927000345354563548035706761107029975435547852199482974493,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error":[{"name":"otbn_rf_bignum_intg_err","qual_name":"6.otbn_rf_bignum_intg_err.77682606230352009011445091040017333529347718789343694673741802542255531774596","seed":77682606230352009011445091040017333529347718789343694673741802542255531774596,"line":117,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_rf_bignum_intg_err/latest/run.log","log_context":["UVM_INFO @  64137304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.13420102779045678900383150595817116762603003718060640814031843676341155711760","seed":13420102779045678900383150595817116762603003718060640814031843676341155711760,"line":197,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3517282417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.91875446195364579270940490381218340602255787317384413870931796073548713285668","seed":91875446195364579270940490381218340602255787317384413870931796073548713285668,"line":162,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  28066335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":425,"total":436,"percent":97.4770642201835}