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[*])":[{"name":"sram_ctrl_throughput_w_readback","qual_name":"0.sram_ctrl_throughput_w_readback.21601354361065351724793202479582998449957069494214257503302112545032747063192","seed":21601354361065351724793202479582998449957069494214257503302112545032747063192,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 220895897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"1.sram_ctrl_throughput_w_readback.79132760470220623036887533175835430381267603324424680088314565328358608890211","seed":79132760470220623036887533175835430381267603324424680088314565328358608890211,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  30209198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"2.sram_ctrl_throughput_w_readback.25105680850018330347405174110297093543601271330395106186940858857095015733634","seed":25105680850018330347405174110297093543601271330395106186940858857095015733634,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  30236466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"3.sram_ctrl_throughput_w_readback.104559073613837902989024485866008656287743796197151707548264395323664141378644","seed":104559073613837902989024485866008656287743796197151707548264395323664141378644,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  41172912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"4.sram_ctrl_throughput_w_readback.12514749947877464270452291110567680904990334235149112096597050372300301017242","seed":12514749947877464270452291110567680904990334235149112096597050372300301017242,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @ 115802922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"5.sram_ctrl_throughput_w_readback.94891528127676975404972007513835260936928275397192354354445095630001467829639","seed":94891528127676975404972007513835260936928275397192354354445095630001467829639,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  67991112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"6.sram_ctrl_throughput_w_readback.78254124063164444674053935605970055272044037138712734504255427558235457126492","seed":78254124063164444674053935605970055272044037138712734504255427558235457126492,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  31469467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"sram_ctrl_throughput_w_readback","qual_name":"7.sram_ctrl_throughput_w_readback.33476346292286895550884622989073106705462128326081349230222396828039934341228","seed":33476346292286895550884622989073106705462128326081349230222396828039934341228,"line":86,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest/run.log","log_context":["UVM_INFO @  31864093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: *":[{"name":"sram_ctrl_csr_mem_rw_with_rand_reset","qual_name":"3.sram_ctrl_csr_mem_rw_with_rand_reset.45827622251876258088942779158678359480180198831152731875391242568102721361025","seed":45827622251876258088942779158678359480180198831152731875391242568102721361025,"line":94,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 390038623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*])":[{"name":"sram_ctrl_stress_all_with_rand_reset","qual_name":"4.sram_ctrl_stress_all_with_rand_reset.59690373853735140750057560596707718636432829140559847643027055613486098529489","seed":59690373853735140750057560596707718636432829140559847643027055613486098529489,"line":170,"log_path":"/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 121840832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":222,"total":248,"percent":89.51612903225806}