{"block":{"name":"chip","variant":null,"commit":"7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19","commit_short":"7a3ad34","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19","revision_info":"GitHub Revision: [`7a3ad34`](https://github.com/lowrisc/opentitan/tree/7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-01T02:38:09Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_flash":{"max_time":226.82,"sim_time":3841.076194,"passed":3,"total":3,"percent":100.0},"chip_sw_example_rom":{"max_time":156.75,"sim_time":2843.1360839999998,"passed":3,"total":3,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":236.5,"sim_time":3743.2393700000002,"passed":3,"total":3,"percent":100.0},"chip_sw_example_concurrency":{"max_time":275.44,"sim_time":3326.054232,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":399.67,"sim_time":6918.693431,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":663.3,"sim_time":5932.251448,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":1209.68,"sim_time":11493.502966,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":7715.860000000001,"sim_time":41993.896124,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":513.36,"sim_time":6868.409688,"passed":1,"total":5,"percent":20.0}},"passed":1,"total":5,"percent":20.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":7715.860000000001,"sim_time":41993.896124,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":663.3,"sim_time":5932.251448,"passed":5,"total":5,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":10.8,"sim_time":226.597615,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":470.46,"sim_time":5236.9098650000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":470.46,"sim_time":5236.9098650000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":470.46,"sim_time":5236.9098650000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":528.13,"sim_time":4816.300696,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":528.13,"sim_time":4816.300696,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":530.13,"sim_time":4500.661639000001,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":589.47,"sim_time":4874.677876,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":598.56,"sim_time":5713.667240000001,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":2489.04,"sim_time":13764.727214999999,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":2408.7,"sim_time":14840.506404,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":1423.22,"sim_time":13539.531595,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":124,"total":128,"percent":96.875},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":357.28,"sim_time":6360.155996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":357.28,"sim_time":6360.155996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":382.41,"sim_time":4446.050803,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":305.79,"sim_time":4026.203752,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":353.32,"sim_time":4078.717544,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":1736.04,"sim_time":18820.884821,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":462.14,"sim_time":6841.426877999999,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":585.07,"sim_time":9448.788296,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1080.56,"sim_time":13050.988178,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":714.2,"sim_time":8049.209215999999,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":714.2,"sim_time":8049.209215999999,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":1009.7799999999999,"sim_time":9339.907455,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":2142.76,"sim_time":16842.815787,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":475.48,"sim_time":4419.26106,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":783.46,"sim_time":6580.1619390000005,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5343.69,"sim_time":20888.88693,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":268.05,"sim_time":4407.152736,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1207.39,"sim_time":9781.176424000001,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":310.13,"sim_time":3945.2419130000003,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2419.47,"sim_time":13943.613942,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":370.25,"sim_time":4116.148014,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.99,"sim_time":7007.181328,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":254.74,"sim_time":2818.712889,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":304.34,"sim_time":3798.30701,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":726.19,"sim_time":7080.894925,"passed":5,"total":5,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":378.15,"sim_time":5983.582582,"passed":3,"total":3,"percent":100.0}},"passed":8,"total":8,"percent":100.0},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":276.98,"sim_time":3231.289977,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":378.15,"sim_time":5983.582582,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_smoketest":{"tests":{"chip_sw_flash_scrambling_smoketest":{"max_time":223.72,"sim_time":3432.4864279999997,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_smoketest":{"max_time":325.15,"sim_time":3253.242746,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":302.1,"sim_time":3518.363636,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":251.43,"sim_time":3809.478943,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":277.94,"sim_time":3193.68867,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":1285.62,"sim_time":8104.117092000001,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":324.91,"sim_time":3957.7910869999996,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":278.79,"sim_time":4477.600442,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":312.5,"sim_time":3291.300605,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":2128.57,"sim_time":11163.224523,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":452.47,"sim_time":7668.749199,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":407.04,"sim_time":7158.3505350000005,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":280.26,"sim_time":3602.89117,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":273.27,"sim_time":3852.035868,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":280.64,"sim_time":3759.910852,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":257.31,"sim_time":3585.351756,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":322.63,"sim_time":3573.4086540000003,"passed":3,"total":3,"percent":100.0}},"passed":51,"total":51,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":315.99,"sim_time":4204.170664,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_functest":{"max_time":567.55,"sim_time":5982.731974,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":12850.31,"sim_time":62172.313308,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":4103.09,"sim_time":15112.806938,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":313.95,"sim_time":7911.599894,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":1593.02,"sim_time":15561.99848,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":1168.24,"sim_time":14979.920192,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":11039.78,"sim_time":53864.592935999994,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_inject_scramble_seed":{"tests":{"chip_sw_inject_scramble_seed":{"max_time":11273.86,"sim_time":55883.355887000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":324.74,"sim_time":4890.43386,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":324.74,"sim_time":4890.43386,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":7715.860000000001,"sim_time":41993.896124,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":4404.02,"sim_time":28498.61664,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":399.67,"sim_time":6918.693431,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":663.3,"sim_time":5932.251448,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":7715.860000000001,"sim_time":41993.896124,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":4404.02,"sim_time":28498.61664,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":399.67,"sim_time":6918.693431,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":663.3,"sim_time":5932.251448,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":92.09,"sim_time":2337.7452599999997,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":7.27,"sim_time":52.772871,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":95.95,"sim_time":9548.696414999999,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":96.8,"sim_time":7503.031663,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":47.34,"sim_time":508.15855200000004,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":433.37,"sim_time":54366.480466,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":408.15,"sim_time":32427.068432,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":58.86,"sim_time":1267.998317,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":55.89,"sim_time":1240.441881,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":75.92,"sim_time":2081.327594,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":55.89,"sim_time":1240.441881,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":104.9,"sim_time":2506.58689,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":895.85,"sim_time":80310.99034,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":78.09,"sim_time":2484.277003,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":559.4,"sim_time":17497.941032000002,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":606.77,"sim_time":18556.969081,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":653.4,"sim_time":15738.765867,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":769.48,"sim_time":22180.075914,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":4103.09,"sim_time":15112.806938,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":3738.6699999999996,"sim_time":33329.290698,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":4041.76,"sim_time":17175.795835999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":3222.52,"sim_time":11651.705071,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":3897.8599999999997,"sim_time":15619.611025,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":4003.92,"sim_time":16462.410701,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":3836.6500000000005,"sim_time":15912.396563999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":4192.52,"sim_time":17491.148672,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":3128.07,"sim_time":12073.567416,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":4014.2300000000005,"sim_time":19237.173498,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":4247.42,"sim_time":16553.234188,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":4022.3000000000006,"sim_time":16800.286492,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":4151.23,"sim_time":15932.60586,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":5636.44,"sim_time":18952.403449999998,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":6970.51,"sim_time":25395.3218,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":7270.81,"sim_time":24104.629761999997,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":7132.23,"sim_time":25043.932041,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":6923.76,"sim_time":23157.54144,"passed":1,"total":1,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":5591.25,"sim_time":18329.459870000002,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":7071.52,"sim_time":23426.565704,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":6689.46,"sim_time":23057.369956,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":6744.05,"sim_time":30622.743870000002,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":6614.07,"sim_time":22687.798977000002,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":3213.51,"sim_time":12429.769505,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":3814.15,"sim_time":14973.868622,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":3907.0099999999998,"sim_time":15634.611155999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":3775.2999999999997,"sim_time":14606.622636,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":3808.41,"sim_time":15247.18822,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":3315.1,"sim_time":13546.80096,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":3788.55,"sim_time":15520.975400000001,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":3536.0,"sim_time":15577.12198,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":3885.44,"sim_time":17488.9698,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":3807.4899999999993,"sim_time":14694.567368,"passed":1,"total":1,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":3298.85,"sim_time":13175.986894,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_dev":{"max_time":4350.78,"sim_time":15357.879516,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_prod":{"max_time":4415.84,"sim_time":16620.93565,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_prod_end":{"max_time":4413.3,"sim_time":17672.58155,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_rma":{"max_time":4452.71,"sim_time":19011.016440000003,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_keymgr_init":{"tests":{"rom_e2e_keymgr_init_rom_ext_meas":{"max_time":8186.25,"sim_time":30793.763478,"passed":1,"total":3,"percent":33.333333333333336},"rom_e2e_keymgr_init_rom_ext_no_meas":{"max_time":8388.53,"sim_time":29218.52443,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_init_rom_ext_invalid_meas":{"max_time":8418.54,"sim_time":30488.896919,"passed":3,"total":3,"percent":100.0}},"passed":7,"total":9,"percent":77.77777777777777},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":4349.62,"sim_time":17068.979725,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.177937956527,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.177937956527,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":317.35,"sim_time":3598.964633,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":268.05,"sim_time":4407.152736,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":196.47,"sim_time":3584.5159219999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":276.37,"sim_time":3708.387976,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":1894.62,"sim_time":12315.488625,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":275.36,"sim_time":4278.346234000001,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":523.49,"sim_time":6147.107665,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":711.06,"sim_time":5695.602583,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":386.65,"sim_time":3853.353965,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":517.03,"sim_time":5629.656599999999,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":322.33,"sim_time":4574.146322,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1668.79,"sim_time":16397.692928,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":555.92,"sim_time":7520.83744,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":294.57,"sim_time":3349.8626,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":14400.20710434485,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1366.83,"sim_time":8922.430167999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1292.41,"sim_time":8083.811035,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":1138.41,"sim_time":8344.233696000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":14400.18350864481,"sim_time":0.0,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":373.11,"sim_time":4262.006614,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":452.47,"sim_time":7668.749199,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":373.11,"sim_time":4262.006614,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":641.9,"sim_time":8785.513,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":641.9,"sim_time":8785.513,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":510.18,"sim_time":9683.22793,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":562.79,"sim_time":6001.794930999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":876.56,"sim_time":6291.788748,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":276.37,"sim_time":3708.387976,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":308.94,"sim_time":4098.067868,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":200.51,"sim_time":3824.085947,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":421.39,"sim_time":7109.32155,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":515.07,"sim_time":5904.331296,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":440.66,"sim_time":6192.009776,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":428.07,"sim_time":6085.329237,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":1315.79,"sim_time":14915.273070000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":598.74,"sim_time":5364.309125,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":559.55,"sim_time":5819.94512,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":606.33,"sim_time":4960.9083,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":513.35,"sim_time":5867.480649,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":542.95,"sim_time":4797.053344999999,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":569.16,"sim_time":5456.5650319999995,"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":1009.7799999999999,"sim_time":9339.907455,"passed":3,"total":3,"percent":100.0}},"passed":21,"total":21,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":836.99,"sim_time":16613.662828,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":606.33,"sim_time":4960.9083,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":513.35,"sim_time":5867.480649,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":475.48,"sim_time":4419.26106,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":783.46,"sim_time":6580.1619390000005,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5343.69,"sim_time":20888.88693,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":268.05,"sim_time":4407.152736,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1207.39,"sim_time":9781.176424000001,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":310.13,"sim_time":3945.2419130000003,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2419.47,"sim_time":13943.613942,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":370.25,"sim_time":4116.148014,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.99,"sim_time":7007.181328,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":254.74,"sim_time":2818.712889,"passed":3,"total":3,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":281.83,"sim_time":4233.545178,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en_reduced_freq":{"max_time":559.52,"sim_time":5681.658604,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en_reduced_freq":{"max_time":839.03,"sim_time":6871.204957999999,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":5415.92,"sim_time":25895.492777,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":259.41,"sim_time":3395.3050580000004,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":243.22,"sim_time":3480.151365,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq":{"max_time":1660.75,"sim_time":13280.017292999999,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":305.68,"sim_time":3964.9345040000003,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":665.11,"sim_time":6474.185555,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init_reduced_freq":{"max_time":1984.08,"sim_time":33379.863667,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":4070.6,"sim_time":23221.624396000003,"passed":3,"total":3,"percent":100.0}},"passed":33,"total":33,"percent":100.0},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":1009.7799999999999,"sim_time":9339.907455,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":562.28,"sim_time":5281.321526,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":432.23,"sim_time":4605.907287999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":1366.83,"sim_time":8922.430167999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2877.31,"sim_time":24217.846120000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":419.23,"sim_time":6577.9324879999995,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":791.08,"sim_time":8266.255224,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":293.66,"sim_time":3492.5418539999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":9039.48,"sim_time":35280.591563,"passed":10,"total":10,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":244.92,"sim_time":3175.888848,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":1193.38,"sim_time":9083.479546,"passed":3,"total":3,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":244.92,"sim_time":3175.888848,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":2877.31,"sim_time":24217.846120000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":288.23,"sim_time":4045.5429269999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_init":{"tests":{"chip_sw_flash_init":{"max_time":1958.6399999999999,"sim_time":30657.555815,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_host_access":{"tests":{"chip_sw_flash_ctrl_access":{"max_time":730.28,"sim_time":6608.736552,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_access_jitter_en":{"max_time":783.46,"sim_time":6580.1619390000005,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_ctrl_ops":{"tests":{"chip_sw_flash_ctrl_ops":{"max_time":515.86,"sim_time":5362.526382,"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_ops_jitter_en":{"max_time":475.48,"sim_time":4419.26106,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_flash_rma_unlocked":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4863.01,"sim_time":46126.82573,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_scramble":{"tests":{"chip_sw_flash_init":{"max_time":1958.6399999999999,"sim_time":30657.555815,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_idle_low_power":{"tests":{"chip_sw_flash_ctrl_idle_low_power":{"max_time":318.25,"sim_time":4274.597116000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_keymgr_seeds":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_creator_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_creator_seed_wipe_on_rma":{"tests":{"chip_sw_flash_rma_unlocked":{"max_time":4863.01,"sim_time":46126.82573,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_lc_owner_seed_sw_rw_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_iso_part_sw_wr_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_seed_hw_rd_en":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_flash_lc_escalate_en":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_flash_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":741.64,"sim_time":12717.218535,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_clock_freqs":{"tests":{"chip_sw_flash_ctrl_clock_freqs":{"max_time":789.64,"sim_time":6639.033421,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_escalation_reset":{"tests":{"chip_sw_flash_crash_alert":{"max_time":611.98,"sim_time":5886.121636,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_ctrl_write_clear":{"tests":{"chip_sw_flash_crash_alert":{"max_time":611.98,"sim_time":5886.121636,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":282.46,"sim_time":4221.114406000001,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":310.13,"sim_time":3945.2419130000003,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":308.94,"sim_time":4098.067868,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":2101.18,"sim_time":11067.423636,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":2277.9,"sim_time":12018.350009,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":603.16,"sim_time":6148.332804,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":599.51,"sim_time":5406.813524,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":619.53,"sim_time":5013.44005,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":472.18,"sim_time":4265.086652,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation_jitter_en":{"max_time":2419.47,"sim_time":13943.613942,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_keymgr_sideload_kmac":{"tests":{"chip_sw_keymgr_sideload_kmac":{"max_time":2061.31,"sim_time":12973.3295,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_aes":{"tests":{"chip_sw_keymgr_sideload_aes":{"max_time":1894.62,"sim_time":12315.488625,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_sideload_otbn":{"tests":{"chip_sw_keymgr_sideload_otbn":{"max_time":6529.82,"sim_time":20018.539128,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":275.85,"sim_time":4218.547944,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":262.77,"sim_time":2954.133918,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":370.25,"sim_time":4116.148014,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_kmac_app_keymgr":{"tests":{"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":237.67,"sim_time":3670.7443879999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":1951.93,"sim_time":11328.207964,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":200.51,"sim_time":3824.085947,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":523.49,"sim_time":6147.107665,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":1736.04,"sim_time":18820.884821,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":585.07,"sim_time":9448.788296,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1080.56,"sim_time":13050.988178,"passed":5,"total":5,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":315.34,"sim_time":4097.948619,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_key_derivation_prod":{"max_time":1226.53,"sim_time":10304.346707,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_flash_ctrl_lc_rw_en":{"max_time":322.38,"sim_time":4193.039745,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_rma_unlocked":{"max_time":4863.01,"sim_time":46126.82573,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":310.59,"sim_time":3572.4549079999997,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":903.59,"sim_time":9580.203374,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":836.94,"sim_time":6763.47229,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":771.41,"sim_time":9881.693248,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":553.11,"sim_time":9359.613177,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":1038.6,"sim_time":13290.249566,"passed":3,"total":3,"percent":100.0},"chip_prim_tl_access":{"max_time":741.64,"sim_time":12717.218535,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":836.99,"sim_time":16613.662828,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":598.74,"sim_time":5364.309125,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":559.55,"sim_time":5819.94512,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":606.33,"sim_time":4960.9083,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":513.35,"sim_time":5867.480649,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":542.95,"sim_time":4797.053344999999,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":569.16,"sim_time":5456.5650319999995,"passed":3,"total":3,"percent":100.0},"chip_tap_straps_dev":{"max_time":1736.04,"sim_time":18820.884821,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":585.07,"sim_time":9448.788296,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":1080.56,"sim_time":13050.988178,"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":575.27,"sim_time":14720.7526,"passed":1,"total":3,"percent":33.333333333333336}},"passed":76,"total":84,"percent":90.47619047619048},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":215.74,"sim_time":3096.774528,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":160.12,"sim_time":4015.287205,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":149.31,"sim_time":3029.231765,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":291.12,"sim_time":4219.151892,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":2947.11,"sim_time":46793.775971,"passed":2,"total":3,"percent":66.66666666666667},"chip_rv_dm_lc_disabled":{"max_time":575.27,"sim_time":14720.7526,"passed":1,"total":3,"percent":33.333333333333336}},"passed":3,"total":6,"percent":50.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":1082.18,"sim_time":12338.269006999999,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":1130.72,"sim_time":14162.945176000001,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":963.5599999999998,"sim_time":13878.0658,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":599.21,"sim_time":9400.445024,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":2947.11,"sim_time":46793.775971,"passed":2,"total":3,"percent":66.66666666666667}},"passed":5,"total":15,"percent":33.333333333333336},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":133.25,"sim_time":3513.81819,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":151.04,"sim_time":3012.218452,"passed":3,"total":3,"percent":100.0},"rom_volatile_raw_unlock":{"max_time":108.03,"sim_time":2461.6594219999997,"passed":3,"total":3,"percent":100.0}},"passed":8,"total":9,"percent":88.88888888888889},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":4970.65,"sim_time":18196.26058,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":5343.69,"sim_time":20888.88693,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":876.56,"sim_time":6291.788748,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":876.56,"sim_time":6291.788748,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":876.56,"sim_time":6291.788748,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":472.0,"sim_time":5049.629016,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_flash_init":{"max_time":1958.6399999999999,"sim_time":30657.555815,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":472.0,"sim_time":5049.629016,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":666.92,"sim_time":7000.583,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":246.43000000000004,"sim_time":4063.420756,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_flash_init":{"max_time":1958.6399999999999,"sim_time":30657.555815,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"max_time":472.0,"sim_time":5049.629016,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_key_derivation":{"max_time":2435.72,"sim_time":14837.770306,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":666.92,"sim_time":7000.583,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":246.43000000000004,"sim_time":4063.420756,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":593.98,"sim_time":6763.740836,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":315.34,"sim_time":4097.948619,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":310.59,"sim_time":3572.4549079999997,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":903.59,"sim_time":9580.203374,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":836.94,"sim_time":6763.47229,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":771.41,"sim_time":9881.693248,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":1134.69,"sim_time":14594.310101,"passed":15,"total":15,"percent":100.0},"chip_prim_tl_access":{"max_time":741.64,"sim_time":12717.218535,"passed":3,"total":3,"percent":100.0}},"passed":27,"total":30,"percent":90.0},"chip_sw_otp_prim_tl_access":{"tests":{"chip_prim_tl_access":{"max_time":741.64,"sim_time":12717.218535,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":1042.57,"sim_time":7452.8733600000005,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":302.46,"sim_time":7276.194699,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":1544.86,"sim_time":27459.776132,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":383.61,"sim_time":8555.939228,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":585.24,"sim_time":9925.783,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":810.28,"sim_time":9083.519859999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":1776.32,"sim_time":28541.28668,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":607.36,"sim_time":10508.936,"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":641.9,"sim_time":8785.513,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":1350.52,"sim_time":15762.785949,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":540.29,"sim_time":5116.22386,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":302.46,"sim_time":7276.194699,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":380.65,"sim_time":4141.35369,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":3595.94,"sim_time":38226.184034000005,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":538.14,"sim_time":9762.520915,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":272.8,"sim_time":3614.976891,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":744.6,"sim_time":11470.851,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1127.46,"sim_time":9548.199672,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1731.1,"sim_time":12389.685365,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":2536.07,"sim_time":33513.446125,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":279.79,"sim_time":3461.194754,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":553.11,"sim_time":9359.613177,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":553.11,"sim_time":9359.613177,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1731.1,"sim_time":12389.685365,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":744.6,"sim_time":11470.851,"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"max_time":540.29,"sim_time":5116.22386,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":452.47,"sim_time":7668.749199,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":12,"percent":75.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":497.13999999999993,"sim_time":4646.662837,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":543.74,"sim_time":7310.51459,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":478.29,"sim_time":6399.535201000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":1668.79,"sim_time":16397.692928,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":307.28,"sim_time":3794.0179730000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":1292.41,"sim_time":8083.811035,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":650.23,"sim_time":5708.341576000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":680.47,"sim_time":5256.540599000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":274.45,"sim_time":3082.8141,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":246.43000000000004,"sim_time":4063.420756,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":543.74,"sim_time":7310.51459,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":543.74,"sim_time":7310.51459,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_mcounteren_writable":{"tests":{"chip_sw_rv_core_ibex_mcounteren_writable":{"max_time":235.01,"sim_time":3732.096015,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":1378.49,"sim_time":16352.075815999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":1606.31,"sim_time":17344.508468,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":497.13999999999993,"sim_time":4646.662837,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":310.2,"sim_time":4087.846792,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":1850.81,"sim_time":13265.183752,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":585.07,"sim_time":9448.788296,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":575.27,"sim_time":14720.7526,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":711.06,"sim_time":5695.602583,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":386.65,"sim_time":3853.353965,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":517.03,"sim_time":5629.656599999999,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":283.87,"sim_time":3659.14952,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":272.57,"sim_time":4207.400249,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":4103.09,"sim_time":15112.806938,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":407.46,"sim_time":4323.288141,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":285.16,"sim_time":4310.145,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":388.23,"sim_time":3712.880897,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":283.6,"sim_time":3896.768192,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":666.92,"sim_time":7000.583,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":567.99,"sim_time":7007.181328,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":728.36,"sim_time":8178.999768000001,"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":836.63,"sim_time":10655.761865,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":1038.6,"sim_time":13290.249566,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0},"chip_sw_data_integrity_escalation":{"max_time":714.2,"sim_time":8049.209215999999,"passed":6,"total":6,"percent":100.0}},"passed":93,"total":106,"percent":87.73584905660377},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1127.46,"sim_time":9548.199672,"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":1583.91,"sim_time":24311.85,"passed":1,"total":3,"percent":33.333333333333336}},"passed":4,"total":6,"percent":66.66666666666667},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":283.3,"sim_time":3915.69328,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":361.8,"sim_time":5053.239786,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":564.03,"sim_time":5356.546116,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1583.91,"sim_time":24311.85,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":1583.91,"sim_time":24311.85,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3177.89,"sim_time":21019.993627,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":3177.89,"sim_time":21019.993627,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":575.74,"sim_time":9014.07101,"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.177937956527,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":200.59,"sim_time":2953.1910589999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":248.34999999999997,"sim_time":3179.0049879999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":373.45,"sim_time":3805.002268,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":508.86,"sim_time":5364.830824,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":1377.26,"sim_time":8281.4288,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":7580.37,"sim_time":32505.893446000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":2661.74,"sim_time":13140.36496,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":249.43999999999997,"sim_time":3929.772908,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1583,"total":1796,"percent":88.1403118040089},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":320.06,"sim_time":3960.757392,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":248.07,"sim_time":3709.960897,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":15592.73,"sim_time":68578.0652,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":1586.98,"sim_time":7367.0538559999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":296.96,"sim_time":3630.174727,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":667.47,"sim_time":6567.228922,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":245.06,"sim_time":4934.845668999999,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":144.63,"sim_time":3541.291575,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":116.25,"sim_time":2351.608948,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":103.42,"sim_time":3434.641125,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":95.56639395654202,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":405.6,"sim_time":4418.022729,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":521.36,"sim_time":3179.93361,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":1536.14,"sim_time":7142.205188,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":1479.28,"sim_time":9194.35784,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":338.71,"sim_time":3206.3320400000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_flash_memory_protection":{"tests":{"chip_sw_flash_ctrl_mem_protection":{"max_time":856.54,"sim_time":6143.2659539999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_vendor_test_csr_access":{"tests":{"chip_sw_otp_ctrl_vendor_test_csr_access":{"max_time":244.30000000000004,"sim_time":3522.5459389999996,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":255.73,"sim_time":3632.815842,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":573.79,"sim_time":7592.919144,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":526.26,"sim_time":6531.280142,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1731.1,"sim_time":12389.685365,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":296.96,"sim_time":3630.174727,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":667.47,"sim_time":6567.228922,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":245.06,"sim_time":4934.845668999999,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":598.75,"sim_time":6723.410086,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":699.32,"sim_time":7454.509416,"passed":87,"total":100,"percent":87.0}},"passed":87,"total":100,"percent":87.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.184278259054,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.184278259054,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":330.32,"sim_time":4770.980792,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":528.13,"sim_time":4816.300696,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":4092.5999999999995,"sim_time":19386.162915,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":129,"total":159,"percent":81.13207547169812},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sival_flash_info_access":{"max_time":310.89,"sim_time":3824.9782250000003,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":33.04,"sim_time":10.100001,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":9.13,"sim_time":0.0,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_ecc_error_vendor_test":{"max_time":248.64000000000001,"sim_time":3884.667848,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_descrambling":{"max_time":312.09,"sim_time":4202.047275000001,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":341.28,"sim_time":5342.60241,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":11.990416772663593,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_sw_flash_ctrl_write_clear":{"max_time":302.15,"sim_time":3871.378591,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_flash_erase":{"max_time":778.06,"sim_time":10010.160001,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":9780.27,"sim_time":44548.91351699999,"passed":3,"total":3,"percent":100.0},"ate_bootstrap_disjoint":{"max_time":10800.18814890366,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":17,"total":31,"percent":54.83870967741935}},"passed":17,"total":31,"percent":54.83870967741935}},"coverage":{"code":{"block":null,"line_statement":94.47,"branch":94.48,"condition_expression":92.91,"toggle":75.07,"fsm":57.14},"assertion":97.87,"functional":99.38},"cov_report_page":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.92305694720327885850794202312769037979635142283215346522978595394818996911532","seed":92305694720327885850794202312769037979635142283215346522978595394818996911532,"line":302,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.65428626086336517448290820713060049995956910637310463377646294445535112822008","seed":65428626086336517448290820713060049995956910637310463377646294445535112822008,"line":302,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.35599365445574741727018192851030744564316212020778443394783171476199889537671","seed":35599365445574741727018192851030744564316212020778443394783171476199889537671,"line":302,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.14381053476807840524934577375232355167032546844697146896954205032742390313600","seed":14381053476807840524934577375232355167032546844697146896954205032742390313600,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["host_rsp:\n","-------------------------------------------------------------------------\n","Name                               Type              Size  Value         \n","-------------------------------------------------------------------------\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.37676791928825140629178172802984055147858225128186676180819627027257240924037","seed":37676791928825140629178172802984055147858225128186676180819627027257240924037,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["host_rsp:\n","-------------------------------------------------------------------------\n","Name                               Type              Size  Value         \n","-------------------------------------------------------------------------\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"0.chip_sw_flash_ctrl_lc_rw_en.80178661635270983376426177770457793593699631516397824125556648952793056193320","seed":80178661635270983376426177770457793593699631516397824125556648952793056193320,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 4193.039745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"1.chip_sw_flash_ctrl_lc_rw_en.13427199244399188858172525568032952920094368994191189349906135820111309990063","seed":13427199244399188858172525568032952920094368994191189349906135820111309990063,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 2802.990825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_flash_ctrl_lc_rw_en","qual_name":"2.chip_sw_flash_ctrl_lc_rw_en.6872867662812255979079096741577461512284957078097870489984134043280713129661","seed":6872867662812255979079096741577461512284957078097870489984134043280713129661,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_ctrl_lc_rw_en/latest/run.log","log_context":["UVM_INFO @ 3974.065868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.3822755318061833681014951302963480899899591217854610165846077122911939927436","seed":3822755318061833681014951302963480899899591217854610165846077122911939927436,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 9881.693248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.93134555427082416873823544230201490297370753925415737338435064283367066218172","seed":93134555427082416873823544230201490297370753925415737338435064283367066218172,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 7604.183650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.19837173939807261770076095224461063980002481088700275838982626160735471596434","seed":19837173939807261770076095224461063980002481088700275838982626160735471596434,"line":343,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 5859.954456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.48549445463435354985603960157807164212011837794478441593350599622927394894284","seed":48549445463435354985603960157807164212011837794478441593350599622927394894284,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 3632.815842 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3632.815842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_csrng_fuse_en_sw_app_read_test","qual_name":"1.chip_sw_csrng_fuse_en_sw_app_read_test.78216443739025249269861901561953420066165325308624183007382626116035388996155","seed":78216443739025249269861901561953420066165325308624183007382626116035388996155,"line":313,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log","log_context":["UVM_ERROR @ 3743.712474 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3743.712474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"47.chip_sw_all_escalation_resets.38290060977828159878261781954410387795974261663728468127927589896397820828560","seed":38290060977828159878261781954410387795974261663728468127927589896397820828560,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3615.281864 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3615.281864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"62.chip_sw_all_escalation_resets.4310129866592068430106513927809751520069377976943731266278004303056239262172","seed":4310129866592068430106513927809751520069377976943731266278004303056239262172,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 4017.232014 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 4017.232014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"81.chip_sw_all_escalation_resets.30917898155406931262024196804197821978382347452219232567790427445674936574689","seed":30917898155406931262024196804197821978382347452219232567790427445674936574689,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 4067.289264 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 4067.289264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"93.chip_sw_all_escalation_resets.37375071399055174298503925225055472502206560229415384507737200049106755731789","seed":37375071399055174298503925225055472502206560229415384507737200049106755731789,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3787.638890 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3787.638890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.87367924992529194755904187548141247396531318580307777458326129651621408941787","seed":87367924992529194755904187548141247396531318580307777458326129651621408941787,"line":283,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.8237586889893674022504307062460342661947762772965926344581024613228080131453","seed":8237586889893674022504307062460342661947762772965926344581024613228080131453,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 12707.634035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.48735256400397695085945900470915659972051735591614937126360663107164391227229","seed":48735256400397695085945900470915659972051735591614937126360663107164391227229,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 14001.918374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.84003371747522398189629759910020723888627082564860526527427678890539739862085","seed":84003371747522398189629759910020723888627082564860526527427678890539739862085,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7935.141794 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.34999908303955932961980782287970636400665569022887577863542305832316436429686","seed":34999908303955932961980782287970636400665569022887577863542305832316436429686,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 10626.540386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.6724351948127827542484944652943695472844533895128277854794277420743211315019","seed":6724351948127827542484944652943695472844533895128277854794277420743211315019,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 14162.945176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.32824836026883821335735215733327967033358820086991436848759013691413569861433","seed":32824836026883821335735215733327967033358820086991436848759013691413569861433,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 7376.558298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.104807482691971282481260475360574302683803163280900424718932056658177964125455","seed":104807482691971282481260475360574302683803163280900424718932056658177964125455,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 12338.269007 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.37039524638396931000928433976748473203691915839271664854223353695814696218759","seed":37039524638396931000928433976748473203691915839271664854223353695814696218759,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 13618.927440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.12656609933410947141208255166600662963646481576373702316701485531909354620902","seed":12656609933410947141208255166600662963646481576373702316701485531909354620902,"line":342,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 9400.445024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration.":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"0.chip_sw_lc_ctrl_volatile_raw_unlock.85437376600189779923020114772263827856548277322101195933966121732849192200178","seed":85437376600189779923020114772263827856548277322101195933966121732849192200178,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 3229.770568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '((~rst_ni) === (~seed_en_q))'":[{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"0.chip_sw_pwrmgr_full_aon_reset.62416285940447729564994763557328024686840647325280884097559692967939034734794","seed":62416285940447729564994763557328024686840647325280884097559692967939034734794,"line":304,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 2705.182470 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 2705.182470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"1.chip_sw_pwrmgr_full_aon_reset.69709404333710894200365630014271127500384402780903243470912790832555474299056","seed":69709404333710894200365630014271127500384402780903243470912790832555474299056,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 6189.814424 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 6189.814424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_full_aon_reset","qual_name":"2.chip_sw_pwrmgr_full_aon_reset.44647978523192600384882168428619344690684200051124536439569535027268855771372","seed":44647978523192600384882168428619344690684200051124536439569535027268855771372,"line":321,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_full_aon_reset/latest/run.log","log_context":["UVM_ERROR @ 7276.194699 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A\n","UVM_INFO @ 7276.194699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(rstreqs[*] && (reset_cause == HwReq))'":[{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.114601991607524169920904091925917672894053684227032213348027255930049875712792","seed":114601991607524169920904091925917672894053684227032213348027255930049875712792,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6140.789000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6140.789000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.41015714735539851773423667562294611893626598302283066665876069444113157524503","seed":41015714735539851773423667562294611893626598302283066665876069444113157524503,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6343.675500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6343.675500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_deep_sleep_por_reset.32482310947993952217233382506595730374508836470270421480381397301389621800842","seed":32482310947993952217233382506595730374508836470270421480381397301389621800842,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 9457.371000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9457.371000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.39266950507096556776412309651133598258450382601068454770664238755895731215725","seed":39266950507096556776412309651133598258450382601068454770664238755895731215725,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 18501.933000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 18501.933000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"0.chip_sw_sysrst_ctrl_reset.7858656919003183649558708076665259073327786519305234742646617713340841442729","seed":7858656919003183649558708076665259073327786519305234742646617713340841442729,"line":335,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 24311.850000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 24311.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"0.chip_sw_aon_timer_wdog_bite_reset.55550782091846756708825788809012857320419630083053789268667480986779701453871","seed":55550782091846756708825788809012857320419630083053789268667480986779701453871,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 7571.655000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7571.655000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.47952541987626129282920229739212653024641510390251317940432575577611568886044","seed":47952541987626129282920229739212653024641510390251317940432575577611568886044,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 7038.301000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 7038.301000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.83074119527628244134539650401446591702814479058097220049194471647753869765311","seed":83074119527628244134539650401446591702814479058097220049194471647753869765311,"line":315,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 6571.036000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 6571.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_deep_sleep_por_reset.33876507311294723005248851164132197223317610818251780534805959207528683926835","seed":33876507311294723005248851164132197223317610818251780534805959207528683926835,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 8626.668000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8626.668000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sysrst_ctrl_reset","qual_name":"1.chip_sw_sysrst_ctrl_reset.87840163420551554714561080491004900611414406571699364705065831292208639390577","seed":87840163420551554714561080491004900611414406571699364705065831292208639390577,"line":335,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_reset/latest/run.log","log_context":["UVM_ERROR @ 24631.278000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 24631.278000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"1.chip_sw_aon_timer_wdog_bite_reset.99753040630499052439077606860738159216096706946693703576093076680544231615526","seed":99753040630499052439077606860738159216096706946693703576093076680544231615526,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8367.716000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8367.716000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.64149152375396426288645446772376439980031794115012151293777860847795437466134","seed":64149152375396426288645446772376439980031794115012151293777860847795437466134,"line":345,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 11470.851000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 11470.851000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.13885084249762540977011042857833288199280008843444706324274677632953473071108","seed":13885084249762540977011042857833288199280008843444706324274677632953473071108,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_ERROR @ 10508.936000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 10508.936000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_deep_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_deep_sleep_por_reset.92825339889332420211159867195976929533360275208959881622087665755367958091308","seed":92825339889332420211159867195976929533360275208959881622087665755367958091308,"line":326,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log","log_context":["UVM_ERROR @ 9925.783000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 9925.783000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_aon_timer_wdog_bite_reset","qual_name":"2.chip_sw_aon_timer_wdog_bite_reset.84876604137486594714668986293287383359668258888804767147367770962207704687911","seed":84876604137486594714668986293287383359668258888804767147367770962207704687911,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_aon_timer_wdog_bite_reset/latest/run.log","log_context":["UVM_ERROR @ 8785.513000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A\n","UVM_INFO @ 8785.513000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.48325770381640272558916662763735173520532392873422288788591339138606620282628","seed":48325770381640272558916662763735173520532392873422288788591339138606620282628,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3614.976891 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3614.976891 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.74298050457023024710329940405312801609273657174034821560919066489432406303667","seed":74298050457023024710329940405312801609273657174034821560919066489432406303667,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 4027.172160 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 4027.172160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.109335851452151083016746612174566688139222996248346063651510661298344520759611","seed":109335851452151083016746612174566688139222996248346063651510661298344520759611,"line":316,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 6114.894755 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 6114.894755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.96903170184856025675134661674110388895743629625267225064043246533022855746345","seed":96903170184856025675134661674110388895743629625267225064043246533022855746345,"line":314,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3427.731448 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3427.731448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.115083886042914950294509185264407841807479636924316971625484461850746769696038","seed":115083886042914950294509185264407841807479636924316971625484461850746769696038,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.73923352861968900239597259179920230865447434298684552068605072678218238223549","seed":73923352861968900239597259179920230865447434298684552068605072678218238223549,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.75836650384557891297522074222983933793322906428731694375866876357230596065173","seed":75836650384557891297522074222983933793322906428731694375866876357230596065173,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.85902393402166764399203189855338032920327787380235393596827902928341054198697","seed":85902393402166764399203189855338032920327787380235393596827902928341054198697,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.115337611539336221195075123214597149625941797030648097415846315731703855621028","seed":115337611539336221195075123214597149625941797030648097415846315731703855621028,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.9696587969936656012009493972568865749118547085849936525152693783279456338414","seed":9696587969936656012009493972568865749118547085849936525152693783279456338414,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.105105050455166976358728243093308121713497426541858376506520379229785523837082","seed":105105050455166976358728243093308121713497426541858376506520379229785523837082,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.69124462742063272063047797490302119893619436567009699962871818310151973208490","seed":69124462742063272063047797490302119893619436567009699962871818310151973208490,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.110917951773525291309367267585165647660316750689773243394467653062524083148331","seed":110917951773525291309367267585165647660316750689773243394467653062524083148331,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.17436579984518763077909433175240558139333600530806299636880595554117990247109","seed":17436579984518763077909433175240558139333600530806299636880595554117990247109,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.10720828223357868484989708772666972594660378583098141923702811060618866462361","seed":10720828223357868484989708772666972594660378583098141923702811060618866462361,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.55185193170524378620486432191772852360664220041371634817044811158337302154004","seed":55185193170524378620486432191772852360664220041371634817044811158337302154004,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.21805437736595895847283843847025353103729081657549051431759336876782147002141","seed":21805437736595895847283843847025353103729081657549051431759336876782147002141,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:376)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.49454942289311107301832778167094745651408275517595863416982599332433650406481","seed":49454942289311107301832778167094745651408275517595863416982599332433650406481,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2899.398880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.23114985257324457642124974971146378973193487140254969902858757464331637071859","seed":23114985257324457642124974971146378973193487140254969902858757464331637071859,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 4278.346234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.34222672215537989475832272581144644521948314636394477764341535416766411724674","seed":34222672215537989475832272581144644521948314636394477764341535416766411724674,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3011.028120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.12069702958648893542952672381858442522423431837956572090204754641312926132566","seed":12069702958648893542952672381858442522423431837956572090204754641312926132566,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2951.166120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.20636058852535280527655634575668980675657771502676096144909652488742510239250","seed":20636058852535280527655634575668980675657771502676096144909652488742510239250,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2870.311480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.114420569373485464717057595406313505544592900651943963484779913457554738243222","seed":114420569373485464717057595406313505544592900651943963484779913457554738243222,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2931.799131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.71150513655431562073029983498906233822012530039955551252915521433329850808867","seed":71150513655431562073029983498906233822012530039955551252915521433329850808867,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3539.529802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.60828086466129797396098198379447986821181229219239304618042052598876872495224","seed":60828086466129797396098198379447986821181229219239304618042052598876872495224,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3883.782264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.20323039632147670474999377498407020426359994107973478150253525563708332951162","seed":20323039632147670474999377498407020426359994107973478150253525563708332951162,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3137.316224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.97934592277259501155003642310048512642494758931915087944174147666921817351596","seed":97934592277259501155003642310048512642494758931915087944174147666921817351596,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3878.443590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.49853826845522257971569657515078939969353291225779710346133893521921039652640","seed":49853826845522257971569657515078939969353291225779710346133893521921039652640,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3658.098860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.14090527686522752682621062013899072961286514655048759135622740186564155342823","seed":14090527686522752682621062013899072961286514655048759135622740186564155342823,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3474.783080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.114879543853651184466528960722825806988323717614042918595683427062959141480236","seed":114879543853651184466528960722825806988323717614042918595683427062959141480236,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3103.623640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.78525127415049736117272858033887510780057950689260698494669161910864537158663","seed":78525127415049736117272858033887510780057950689260698494669161910864537158663,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2751.020528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.105972701676460574608062115658990007084361071891800845796025205091882907854950","seed":105972701676460574608062115658990007084361071891800845796025205091882907854950,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3076.547055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.56687629751730476135502657073796566692337001276975362030597742262787303029671","seed":56687629751730476135502657073796566692337001276975362030597742262787303029671,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3528.411777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.112395349726616690360653194854045430310485774440404003908616142978998232988487","seed":112395349726616690360653194854045430310485774440404003908616142978998232988487,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3693.640964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.87765234316317895039884248342319687606503776689449073072030932846613010420318","seed":87765234316317895039884248342319687606503776689449073072030932846613010420318,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2509.100904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.86909719095716335771252372697915821635741922882528413022878610389191815554365","seed":86909719095716335771252372697915821635741922882528413022878610389191815554365,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3770.928000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.93604750968032831305038058062923568361077532196080395392313880791627570022061","seed":93604750968032831305038058062923568361077532196080395392313880791627570022061,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2854.201042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.29164432915352911516019831118095716323110386347240659151289186252134639771850","seed":29164432915352911516019831118095716323110386347240659151289186252134639771850,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4083.736904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.102975586012175443194275437225157836249042908812312834099028408834151610726465","seed":102975586012175443194275437225157836249042908812312834099028408834151610726465,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3664.854440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.81363762630776504117789297495813892195844290673682727889965036778612949027326","seed":81363762630776504117789297495813892195844290673682727889965036778612949027326,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4470.760352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.85048804479805089873164436963357255253476539048857161708163490444224269061228","seed":85048804479805089873164436963357255253476539048857161708163490444224269061228,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3612.792400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.106246588221941213340989463986266596370916820174787648662654619605156501511712","seed":106246588221941213340989463986266596370916820174787648662654619605156501511712,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3483.945747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.29355299806594316067736762355652322003496893469800443089773551929285346791764","seed":29355299806594316067736762355652322003496893469800443089773551929285346791764,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3453.006312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.108103842066537769968950848955865393530897831737147899690338093929110610241996","seed":108103842066537769968950848955865393530897831737147899690338093929110610241996,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3734.321494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.30599778601677063240867081969200254827130800853878239478288498368967760591860","seed":30599778601677063240867081969200254827130800853878239478288498368967760591860,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3763.783272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.18853644505160045844290548215751181272263303436425036800434175531879789412984","seed":18853644505160045844290548215751181272263303436425036800434175531879789412984,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4273.873113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.27164224828597763558407470399570497052578281415761465648047960629740594063823","seed":27164224828597763558407470399570497052578281415761465648047960629740594063823,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3985.534852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.43468334165409166594605325917722095138816528497541068447789179311371830718825","seed":43468334165409166594605325917722095138816528497541068447789179311371830718825,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3176.206942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.27611540484252166224040430200585481237673280601929245370485898652685944009820","seed":27611540484252166224040430200585481237673280601929245370485898652685944009820,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3929.823800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.72021979021170621305477902991898333694008842814913730591920035150383605577581","seed":72021979021170621305477902991898333694008842814913730591920035150383605577581,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3732.265056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.20121481044698767283003182568221704585517859206436084274333624256431796561355","seed":20121481044698767283003182568221704585517859206436084274333624256431796561355,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3304.259380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.472359894208155228924480367965770499538472317955862383934026239889859597554","seed":472359894208155228924480367965770499538472317955862383934026239889859597554,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3341.611542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.79499788657044242366331856818823125424402334954773600407231184512311490864807","seed":79499788657044242366331856818823125424402334954773600407231184512311490864807,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3590.163717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.29100971049470596134076823755916551790825382302188745555918506833634486212615","seed":29100971049470596134076823755916551790825382302188745555918506833634486212615,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3433.366120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.33652996031296399099464421373772602207012969568419691896898007188491501164554","seed":33652996031296399099464421373772602207012969568419691896898007188491501164554,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4071.561096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2028264496157414579044266648958034561948410022695740774843425956723427158994","seed":2028264496157414579044266648958034561948410022695740774843425956723427158994,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3830.843836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.28817461552618669787422138054023331811009512635910439392992832299902304243214","seed":28817461552618669787422138054023331811009512635910439392992832299902304243214,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3469.834014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.112062242525927436907133507427381226264576603136866955567501448713566302688678","seed":112062242525927436907133507427381226264576603136866955567501448713566302688678,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4305.044115 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.37409160488913224382096100685724201356099596487800093974327719752590715614446","seed":37409160488913224382096100685724201356099596487800093974327719752590715614446,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3552.197296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.15115509891399364623468331566705660534349737480050135880300777814291621147647","seed":15115509891399364623468331566705660534349737480050135880300777814291621147647,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3812.100373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.44776506562210713105145704274108016917256673644951019656338284752923897222563","seed":44776506562210713105145704274108016917256673644951019656338284752923897222563,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3033.973109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.88320247455431160979592705855161824840879265512337046792711340847546753554633","seed":88320247455431160979592705855161824840879265512337046792711340847546753554633,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3369.673332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.19326583189878758216608571757295181249586441226550660851825357954625772827101","seed":19326583189878758216608571757295181249586441226550660851825357954625772827101,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3200.583438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.105380620618407060843860696287934489918112656327139825539376631780903197574858","seed":105380620618407060843860696287934489918112656327139825539376631780903197574858,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3219.906555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.45731175786279158267956406318472921195805230853554721265721029400523935276231","seed":45731175786279158267956406318472921195805230853554721265721029400523935276231,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3694.954388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.54511835115550250544580752793964729891132048906873717441876642917441353293955","seed":54511835115550250544580752793964729891132048906873717441876642917441353293955,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2806.251090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.59178487071616179566352872161725345260772771746939089609224344645808737115989","seed":59178487071616179566352872161725345260772771746939089609224344645808737115989,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4356.336050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.20006092869398313324793808757763959312256552860451934186860740184658777902218","seed":20006092869398313324793808757763959312256552860451934186860740184658777902218,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4284.752000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.8826033111828141895800694764076089342439296823942390284420454662003306322756","seed":8826033111828141895800694764076089342439296823942390284420454662003306322756,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3349.862600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.99762392602175118954540503043590562798020488314873813004566537074966347585579","seed":99762392602175118954540503043590562798020488314873813004566537074966347585579,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3551.969324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.63613832761560154545147429046459839579351784207225788993892804143963915895874","seed":63613832761560154545147429046459839579351784207225788993892804143963915895874,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3897.307496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.34899337428878462618889219587286777659988360537248619249769048796060308320001","seed":34899337428878462618889219587286777659988360537248619249769048796060308320001,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4060.202444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.61891348526412610470020103664503964238689912762996862696950144806739128615393","seed":61891348526412610470020103664503964238689912762996862696950144806739128615393,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4111.340754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.115468707347939037096150272351285066920131710102062180904160756752317797006819","seed":115468707347939037096150272351285066920131710102062180904160756752317797006819,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3410.299283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.48090909287739271520568758375239998984885496166662496987091577969620116394224","seed":48090909287739271520568758375239998984885496166662496987091577969620116394224,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4025.282510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.25255592679665262309596656025519983267067275119602515901234082829400971778844","seed":25255592679665262309596656025519983267067275119602515901234082829400971778844,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4218.371840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.11807706349535421147576623435806274519195921574676532538735884056970320488414","seed":11807706349535421147576623435806274519195921574676532538735884056970320488414,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4155.494972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.49417023992569009244081738832137804485802439894866470857140900721502557063822","seed":49417023992569009244081738832137804485802439894866470857140900721502557063822,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3497.591176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.74971277383342207807690523867665031962341014599131047831770201997678123820989","seed":74971277383342207807690523867665031962341014599131047831770201997678123820989,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3034.142680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.52648492387346320515107167881609056346813356486958280387414878312834586476195","seed":52648492387346320515107167881609056346813356486958280387414878312834586476195,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3052.506566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3125525316252934755966564214351876093418080243910939892136559746111758440002","seed":3125525316252934755966564214351876093418080243910939892136559746111758440002,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3127.147528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.55153429543162985798612963960180273977616733638971555862867177159268504587277","seed":55153429543162985798612963960180273977616733638971555862867177159268504587277,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2885.485640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.35853098763826351613218448929323811420656114566659595902503463919490801924521","seed":35853098763826351613218448929323811420656114566659595902503463919490801924521,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3098.735804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.46659645606422960170909847414847602542451586434222525445253405758364549749751","seed":46659645606422960170909847414847602542451586434222525445253405758364549749751,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3444.144801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.89460882984516158039288984797550604153089151721275028204688950166748111152723","seed":89460882984516158039288984797550604153089151721275028204688950166748111152723,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3516.606196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.87436691644877482724683675481842447996098813965440743797287520511386669391343","seed":87436691644877482724683675481842447996098813965440743797287520511386669391343,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3798.945296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.62973073888691420403809761627764654676638663182477544693750248486164584909012","seed":62973073888691420403809761627764654676638663182477544693750248486164584909012,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3678.938614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.33076915038053657126917921556830074601340773291098953925890589898603254418285","seed":33076915038053657126917921556830074601340773291098953925890589898603254418285,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3121.562968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.53747108034014391426195122944428936006691164949326966596690666009873897917693","seed":53747108034014391426195122944428936006691164949326966596690666009873897917693,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3654.038102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.78995048535013390404062442043307208642291115798529706953014051315610865437703","seed":78995048535013390404062442043307208642291115798529706953014051315610865437703,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4120.895915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.78843572504269626141670087938303534614522549082805993295948175099990781055981","seed":78843572504269626141670087938303534614522549082805993295948175099990781055981,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3455.513036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.51851487060350092423546835983311144201415935199189147195290999075567721667283","seed":51851487060350092423546835983311144201415935199189147195290999075567721667283,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3126.231699 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.103533461933359788328519053533255567410367619242265318533828658418885726456738","seed":103533461933359788328519053533255567410367619242265318533828658418885726456738,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3534.008878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.62609007256959632603774460482962324180972279678438259409941737423249841953773","seed":62609007256959632603774460482962324180972279678438259409941737423249841953773,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3726.599836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.84499322698815955470983381389095308129467653513011737511551979361745873834246","seed":84499322698815955470983381389095308129467653513011737511551979361745873834246,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3389.438336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.77132495151026676968343042498908711740917525003287618898493961695719835399300","seed":77132495151026676968343042498908711740917525003287618898493961695719835399300,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3835.351040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.36472507931617215921168172122683920558264720508879376538380786249816399647463","seed":36472507931617215921168172122683920558264720508879376538380786249816399647463,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3778.396967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.19513002226538586781306298704504180664799419108234777683382239186563826727343","seed":19513002226538586781306298704504180664799419108234777683382239186563826727343,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4312.290390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.5842227476101998222811920576638012785787898559252058012213573760911554512306","seed":5842227476101998222811920576638012785787898559252058012213573760911554512306,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2952.810650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.93121321335176215490332321305608439239674858225608270230588932916317509333411","seed":93121321335176215490332321305608439239674858225608270230588932916317509333411,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3016.338872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.34651501213308701336893070615976855738847626767094241149365702657543681652861","seed":34651501213308701336893070615976855738847626767094241149365702657543681652861,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2936.254748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.27833177804286397861331356883773208061445760722518068413039791181641951955870","seed":27833177804286397861331356883773208061445760722518068413039791181641951955870,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3454.633264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.44773349042381907441062569939804077654130260090300564949623931658542759833255","seed":44773349042381907441062569939804077654130260090300564949623931658542759833255,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3940.145436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.102170992321102720271376908706640901841455925606366969662413832718176711218846","seed":102170992321102720271376908706640901841455925606366969662413832718176711218846,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4142.754583 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.112775949430471372140336963523031643733390277248216232430794086854971260954063","seed":112775949430471372140336963523031643733390277248216232430794086854971260954063,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3239.602976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.88547142494486909520723694299149065383168878611917197035080351076558063494443","seed":88547142494486909520723694299149065383168878611917197035080351076558063494443,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4143.267816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.71876729578692569384114746157164069926423574603082592220790300676884913865786","seed":71876729578692569384114746157164069926423574603082592220790300676884913865786,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 4020.538496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.39072958448670032119283617470740427424748062438031988567653659418768218402862","seed":39072958448670032119283617470740427424748062438031988567653659418768218402862,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3923.408110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.106662530073957008103421225734009706946791191517306274570897901544584869771222","seed":106662530073957008103421225734009706946791191517306274570897901544584869771222,"line":309,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3190.606520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.36614934349068031174240488916928894114411127185489178252854839103879497257409","seed":36614934349068031174240488916928894114411127185489178252854839103879497257409,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.701411 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"0.chip_sw_keymgr_sideload_otbn.102542561882544697802390249779772842237624061410896513171210836395384548738835","seed":102542561882544697802390249779772842237624061410896513171210836395384548738835,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.667254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.104382540816034814871618412238481338187063039343280342275709451986151332863977","seed":104382540816034814871618412238481338187063039343280342275709451986151332863977,"line":358,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.432574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"1.chip_sw_keymgr_sideload_otbn.99163905870961983493692542779244699871060496261683470921617559172439473891600","seed":99163905870961983493692542779244699871060496261683470921617559172439473891600,"line":335,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20026.705017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"2.chip_sw_hmac_multistream.41066139206010965736566345255799451263471236247739816580407862226264898164282","seed":41066139206010965736566345255799451263471236247739816580407862226264898164282,"line":351,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12018.350009 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_keymgr_sideload_otbn","qual_name":"2.chip_sw_keymgr_sideload_otbn.98777798961135364456366596004526601969128541672881162470339434933618735892601","seed":98777798961135364456366596004526601969128541672881162470339434933618735892601,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_otbn/latest/run.log","log_context":["\n","UVM_INFO @ 20018.539128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.91594881653641395668087470031835529404390039885833183065916895030047252967467","seed":91594881653641395668087470031835529404390039885833183065916895030047252967467,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30576) { a_addr: 'h104b4  a_data: 'h818363e3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h195eb  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2792.437006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.50248693964169931405517543937575371214460211628604642912455429219688133744934","seed":50248693964169931405517543937575371214460211628604642912455429219688133744934,"line":225,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30994) { a_addr: 'h104a8  a_data: 'h7bc0da33  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1a909  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3695.069049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.4176657978839797362045961451651110215405564168510751897679889456315117130396","seed":4176657978839797362045961451651110215405564168510751897679889456315117130396,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32788) { a_addr: 'h107a4  a_data: 'h5d998364  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1bd71  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3186.820637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"1.chip_csr_mem_rw_with_rand_reset.56873771652449524898986455603194678279097298579840266775736874449692935333641","seed":56873771652449524898986455603194678279097298579840266775736874449692935333641,"line":225,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30372) { a_addr: 'h10794  a_data: 'h4b56eb67  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h18144  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2722.504754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.82847917717963341842841114370730849024108329149007984946058429423232216509911","seed":82847917717963341842841114370730849024108329149007984946058429423232216509911,"line":223,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30686) { a_addr: 'h1035c  a_data: 'hcf6edf1b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h19e82  d_param: 'h0  d_source: 'h38  d_data: 'h100073  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd04  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2626.375470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.75872193790766988331684030701485746480832267708042611081178295971042004368942","seed":75872193790766988331684030701485746480832267708042611081178295971042004368942,"line":225,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30604) { a_addr: 'h10480  a_data: 'hd5275f9c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1a514  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2816.698775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.68101537337942087461080358604372470022598646015329776502572780195286130484115","seed":68101537337942087461080358604372470022598646015329776502572780195286130484115,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31280) { a_addr: 'h104b4  a_data: 'h6288bfb6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h195ba  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2379.346345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.92886722050611297301583359761197968026564753887894620015156376438012817304712","seed":92886722050611297301583359761197968026564753887894620015156376438012817304712,"line":225,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30392) { a_addr: 'h104e8  a_data: 'h7c4254dd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h181a5  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2929.964720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.29051991167201728067133160760012876570780842178406046965215964317909406799162","seed":29051991167201728067133160760012876570780842178406046965215964317909406799162,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30590) { a_addr: 'h10524  a_data: 'h535232f4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h186a4  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2777.538215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.5033157048683797302494749871592956781242742220527478332892600342830923662593","seed":5033157048683797302494749871592956781242742220527478332892600342830923662593,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@37532) { a_addr: 'h104dc  a_data: 'h607a8b62  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1b11c  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2575.189296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"6.chip_tl_errors.66977015871852586125997704368570486427753062599307202776688185329462245173145","seed":66977015871852586125997704368570486427753062599307202776688185329462245173145,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31408) { a_addr: 'h10724  a_data: 'he0e3915b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h18dc6  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3314.085639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.83424629133089168753518575211333175825901005605502194033759152211229334606305","seed":83424629133089168753518575211333175825901005605502194033759152211229334606305,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31366) { a_addr: 'h10728  a_data: 'he40dea0e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h19591  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2609.377348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.38004909951789168133752723707849835889463912195606289524771589158532245974410","seed":38004909951789168133752723707849835889463912195606289524771589158532245974410,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30700) { a_addr: 'h107ac  a_data: 'h38277cf2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1a9e6  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3677.664144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.27164173797875737123672298522266050135823149341746767632159993256801910858701","seed":27164173797875737123672298522266050135823149341746767632159993256801910858701,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@38334) { a_addr: 'h10368  a_data: 'hbbea86b8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1ae26  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2776.609909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.13441481610152310880150275616172997371894265136254818474426018858801958643909","seed":13441481610152310880150275616172997371894265136254818474426018858801958643909,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@36424) { a_addr: 'h10518  a_data: 'h4a43bb90  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1a2eb  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3524.682529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.33958186194076243116305949314161582988039738144235691993741155106725151985768","seed":33958186194076243116305949314161582988039738144235691993741155106725151985768,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31416) { a_addr: 'h106a8  a_data: 'h17c598fb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1a24c  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2528.604148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"12.chip_tl_errors.81791558360921785266055477487811220701325788900159205353243308124179019581430","seed":81791558360921785266055477487811220701325788900159205353243308124179019581430,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32698) { a_addr: 'h104e8  a_data: 'h9d903e7a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h181f2  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2820.987893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.87761796784656307096221174763470775133123781014086675900329754971276633701253","seed":87761796784656307096221174763470775133123781014086675900329754971276633701253,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33478) { a_addr: 'h105fc  a_data: 'h15da165a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1aeb6  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2728.875704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.10202960939728277432424077736060004744030956805974700675221686151687859416612","seed":10202960939728277432424077736060004744030956805974700675221686151687859416612,"line":219,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40370) { a_addr: 'h10384  a_data: 'hbf72dad  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h4  a_user: 'h1b6ea  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2852.921218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.73725156674135773140447494234954120570852992195145414825557090684458070115992","seed":73725156674135773140447494234954120570852992195145414825557090684458070115992,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30598) { a_addr: 'h106c0  a_data: 'hc3086291  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h186d9  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2812.974955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.52711491628721212135059657117842527528400358190928622800677520636970740328627","seed":52711491628721212135059657117842527528400358190928622800677520636970740328627,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32672) { a_addr: 'h106d4  a_data: 'h926ce84e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h1aea4  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3595.694784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.70933245154283517564671567296573537609704278193953395152912206479765318919774","seed":70933245154283517564671567296573537609704278193953395152912206479765318919774,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32146) { a_addr: 'h104d4  a_data: 'hf4a4e8e8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1a5a3  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2815.446615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.106129727229005848789011419034043246751149022653978105764405804476782142922463","seed":106129727229005848789011419034043246751149022653978105764405804476782142922463,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32094) { a_addr: 'h10764  a_data: 'h2443d3dd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1a534  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2826.143367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.108146786042033791852089555607673049563999996251700489002042088011694505443092","seed":108146786042033791852089555607673049563999996251700489002042088011694505443092,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31594) { a_addr: 'h1057c  a_data: 'hd3d9609f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h19e32  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2707.019538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.33458224219779851782966580529372113348915365838759521175259456770131280816398","seed":33458224219779851782966580529372113348915365838759521175259456770131280816398,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31378) { a_addr: 'h10450  a_data: 'hfae533cc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h199a7  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2905.088526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.38724631127303655923707071889141095372773638668980068312983450446201365913438","seed":38724631127303655923707071889141095372773638668980068312983450446201365913438,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30462) { a_addr: 'h1059c  a_data: 'h76875583  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h19edb  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3633.812247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.15504905667437278130041782506977368087651591982611780902284138039704570137675","seed":15504905667437278130041782506977368087651591982611780902284138039704570137675,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30474) { a_addr: 'h10354  a_data: 'h57899aa3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h18a15  d_param: 'h0  d_source: 'h39  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3180.630266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.112274012494094448723500823798581785924780927052864239066058825239689715337150","seed":112274012494094448723500823798581785924780927052864239066058825239689715337150,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30654) { a_addr: 'h1076c  a_data: 'hc024016b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1b1c6  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3108.534841 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.67589158306821246039531139770852381729032519377741748978827943265316639057625","seed":67589158306821246039531139770852381729032519377741748978827943265316639057625,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32222) { a_addr: 'h1056c  a_data: 'hab9e3408  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h4  a_user: 'h1baed  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3325.290570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.4438966626634035990437682050793500539192711913741890024286284620112516210274","seed":4438966626634035990437682050793500539192711913741890024286284620112516210274,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40448) { a_addr: 'h1078c  a_data: 'hcba87471  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1b154  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2958.734905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.24493655343603108715771760350033472285773128656219544555757716247965061547865","seed":24493655343603108715771760350033472285773128656219544555757716247965061547865,"line":218,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@30472) { a_addr: 'h107ac  a_data: 'h7f0831cd  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2a  a_opcode: 'h4  a_user: 'h1a988  d_param: 'h0  d_source: 'h2a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 3387.968851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.112941486751678234274091186635033819570585380683222303344013175636335610522087","seed":112941486751678234274091186635033819570585380683222303344013175636335610522087,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4108.237948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.34164000169208942401788480455309707268894446902813316635498494209010087191368","seed":34164000169208942401788480455309707268894446902813316635498494209010087191368,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4065.575087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.12803564844158059960793839147885474846539136509805118431807119048990646960470","seed":12803564844158059960793839147885474846539136509805118431807119048990646960470,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 4418.022729 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.17516502714951362327135414994483998665452289339897894589379556051045936034714","seed":17516502714951362327135414994483998665452289339897894589379556051045936034714,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDERR ----\n","Another command (pid=3548563) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=3548719) is running. Waiting for it to complete on the server (server_pid=254264)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.10737956995340434932703951469821638784441396816451433114032525440222966330520","seed":10737956995340434932703951469821638784441396816451433114032525440222966330520,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=280150) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=256524) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=281374) is running. Waiting for it to complete on the server (server_pid=254264)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.52051998137638712363421141324364650462144208554283037148727666901821300576037","seed":52051998137638712363421141324364650462144208554283037148727666901821300576037,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.100083602782769386590736215400408010135466312888807028073955032024306808384907","seed":100083602782769386590736215400408010135466312888807028073955032024306808384907,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=293269) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=295474) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=296504) is running. Waiting for it to complete on the server (server_pid=254264)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.99745037027006450980580648601288518435930275844552024985978914830961292985867","seed":99745037027006450980580648601288518435930275844552024985978914830961292985867,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1239620) is running. Waiting for it to complete on the server (server_pid=254264)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.51683189799082347424831752500789515124759533435969045723420958080707827682290","seed":51683189799082347424831752500789515124759533435969045723420958080707827682290,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=337752) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=323497) is running. Waiting for it to complete on the server (server_pid=254264)...\n","Another command (pid=336639) is running. Waiting for it to complete on the server (server_pid=254264)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.6481516774124264825155227742761655477083043686338393835069256387133269415558","seed":6481516774124264825155227742761655477083043686338393835069256387133269415558,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.46686318867307796510914423777315869190088810917528098141134384986419216881704","seed":46686318867307796510914423777315869190088810917528098141134384986419216881704,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.35878281220031151462462038231066776884037464526799278291480513940283614306953","seed":35878281220031151462462038231066776884037464526799278291480513940283614306953,"line":353,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.33428949440220461390181856978229060685683861080448622754336560778993253511121","seed":33428949440220461390181856978229060685683861080448622754336560778993253511121,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.104946642727039043373936060166057711667173062653800916354076677118874526156710","seed":104946642727039043373936060166057711667173062653800916354076677118874526156710,"line":304,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.59149653514979946401672318845744662265741328198586328103118289108233147429120","seed":59149653514979946401672318845744662265741328198586328103118289108233147429120,"line":304,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.97816427555527379988664496437629494023312837371568209172897426819288729877576","seed":97816427555527379988664496437629494023312837371568209172897426819288729877576,"line":304,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.75154901476030610116201491148692740036831958260670078232476257783486927937100","seed":75154901476030610116201491148692740036831958260670078232476257783486927937100,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.84595914508219527017195153532270959329203964481977592661906547623291951195464","seed":84595914508219527017195153532270959329203964481977592661906547623291951195464,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write.":[{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.52135279576439687080782306484190571074502312361222892618221486388049072085866","seed":52135279576439687080782306484190571074502312361222892618221486388049072085866,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 4195.300059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.12698715410077590011973963792613898077431365694135943966648531707446194591572","seed":12698715410077590011973963792613898077431365694135943966648531707446194591572,"line":226,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 5534.011810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.23658849778370704146013595830539307007108943684272714445411235317085489904786","seed":23658849778370704146013595830539307007108943684272714445411235317085489904786,"line":226,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 4569.029047 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_idle_load","qual_name":"0.chip_sw_power_idle_load.61536463856479523862999398495364223369067933567375263236015025667131806331346","seed":61536463856479523862999398495364223369067933567375263236015025667131806331346,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 16300.754672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"1.chip_sw_power_idle_load.55835932480823916921517828615719447764167719495590335720008436151498209262446","seed":55835932480823916921517828615719447764167719495590335720008436151498209262446,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15561.998480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_idle_load","qual_name":"2.chip_sw_power_idle_load.92326825316019513368366485411310718446533644068834213961796839089631921791618","seed":92326825316019513368366485411310718446533644068834213961796839089631921791618,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_idle_load/latest/run.log","log_context":["UVM_INFO @ 15280.864104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)":[{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.17445599111597885146434270097227420075930418928078037352875592807525323074228","seed":17445599111597885146434270097227420075930418928078037352875592807525323074228,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 14979.920192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"1.chip_sw_power_sleep_load.37003666348663092215851460081143306424603158485052772045523963325917143725678","seed":37003666348663092215851460081143306424603158485052772045523963325917143725678,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 15023.992712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.54575385217497145510700854693339651114978812124790605139859422130839710273348","seed":54575385217497145510700854693339651114978812124790605139859422130839710273348,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 15305.848724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.65232741664850320598991895332795303847522608391518123573555605203490257580813","seed":65232741664850320598991895332795303847522608391518123573555605203490257580813,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 15358.289428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.68587996203455448471150190310014745829172552948115656116067318336945317738830","seed":68587996203455448471150190310014745829172552948115656116067318336945317738830,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 16842.815787 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.51773169296478517327436656141333541789522985283539409812664989378272062674887","seed":51773169296478517327436656141333541789522985283539409812664989378272062674887,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 12755.676033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.26820053273632624456385168950166935438689092376200267375542466733970504301520","seed":26820053273632624456385168950166935438689092376200267375542466733970504301520,"line":273,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.29532772879352097006530544597100741264910085488247190102163789371155630721633","seed":29532772879352097006530544597100741264910085488247190102163789371155630721633,"line":273,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.108291381355967726729734298498552240319411328570467277134034103530652178042103","seed":108291381355967726729734298498552240319411328570467277134034103530652178042103,"line":273,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *":[{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"0.rom_e2e_keymgr_init_rom_ext_meas.43816559789347824799632163853919403159250500066063679014948591702608184437266","seed":43816559789347824799632163853919403159250500066063679014948591702608184437266,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 18193.336047 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_keymgr_init_rom_ext_meas","qual_name":"1.rom_e2e_keymgr_init_rom_ext_meas.53871681656975027774728097710986638493680378702591549901928493466574985244476","seed":53871681656975027774728097710986638493680378702591549901928493466574985244476,"line":320,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log","log_context":["UVM_INFO @ 16622.498454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '$stable(key_data_i)'":[{"name":"rom_keymgr_functest","qual_name":"0.rom_keymgr_functest.34765328542107232003248372767486090538463444102182390666501664862995853940907","seed":34765328542107232003248372767486090538463444102182390666501664862995853940907,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 6345.133568 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 6345.133568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"1.rom_keymgr_functest.104333071053874871949280563453869146880493101805802575459025629380847631292478","seed":104333071053874871949280563453869146880493101805802575459025629380847631292478,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5982.731974 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5982.731974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"rom_keymgr_functest","qual_name":"2.rom_keymgr_functest.108084054873020014016326923236934570815615937027399102110871434051024323726347","seed":108084054873020014016326923236934570815615937027399102110871434051024323726347,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_keymgr_functest/latest/run.log","log_context":["UVM_ERROR @ 5045.007802 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M\n","UVM_INFO @ 5045.007802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly.":[{"name":"chip_sw_all_escalation_resets","qual_name":"1.chip_sw_all_escalation_resets.78474268477953963701542841023105819007939903828060890522882910126220523739467","seed":78474268477953963701542841023105819007939903828060890522882910126220523739467,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3762.866424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"2.chip_sw_all_escalation_resets.3555030859624360526847388745871085219457859409810211275152226279066371327864","seed":3555030859624360526847388745871085219457859409810211275152226279066371327864,"line":317,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4031.614546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$isunknown(pin_wkup_req_o))'":[{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.64187206667569219703675955620509841586846908789080444719147094925262806428999","seed":64187206667569219703675955620509841586846908789080444719147094925262806428999,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_ERROR @ 3691.422000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A\n","UVM_INFO @ 3691.422000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.106476352468168240969659696706894367363473575283038100219731216567363204482628","seed":106476352468168240969659696706894367363473575283038100219731216567363204482628,"line":319,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_ERROR @ 3066.535000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A\n","UVM_INFO @ 3066.535000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.67403351815798201070949019576978426192736291471350665473507597038172524872096","seed":67403351815798201070949019576978426192736291471350665473507597038172524872096,"line":328,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 4310.145000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.4852212643766996847135578731734612041374202520063886293983072842806599239617","seed":4852212643766996847135578731734612041374202520063886293983072842806599239617,"line":446,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["UVM_INFO @ 46793.775971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:346)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.98376173413493281968725358242314382833637151189135981524886571290260275473404","seed":98376173413493281968725358242314382833637151189135981524886571290260275473404,"line":308,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3084.373378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.":[{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.91836721783328762549645030129619598448517608682934009493157224541277934132308","seed":91836721783328762549645030129619598448517608682934009493157224541277934132308,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 13265.183752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.99817002251522325515381467390712724336514353984617251453642185936629425802051","seed":99817002251522325515381467390712724336514353984617251453642185936629425802051,"line":330,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 13472.597496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()":[{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"2.chip_sw_pwrmgr_lowpower_cancel.106095187728225984007779342068895742095105071114350974667684572244444630804721","seed":106095187728225984007779342068895742095105071114350974667684572244444630804721,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 4213.443709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rv_jtag_o == '0)'":[{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.49211416397427831989113178559972977085757377685487188346222478721456277801950","seed":49211416397427831989113178559972977085757377685487188346222478721456277801950,"line":312,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["UVM_ERROR @ 4375.498616 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A\n","UVM_INFO @ 4375.498616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"3.chip_sw_all_escalation_resets.21440168123478459623319392912257255538156560674078949504348095312475306508504","seed":21440168123478459623319392912257255538156560674078949504348095312475306508504,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3392.231102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"15.chip_sw_all_escalation_resets.43137363438612850068712550287283655281199601043195516630523532436326500480038","seed":43137363438612850068712550287283655281199601043195516630523532436326500480038,"line":318,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4026.369140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1095)] Unexpected fault":[{"name":"chip_sw_all_escalation_resets","qual_name":"39.chip_sw_all_escalation_resets.103295829612729746655802317735710042714968569905411447017437096262563451031304","seed":103295829612729746655802317735710042714968569905411447017437096262563451031304,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3437.911120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"55.chip_sw_all_escalation_resets.65132499306287886748936025447729915449075092441246922113026784944628607268469","seed":65132499306287886748936025447729915449075092441246922113026784944628607268469,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2787.492770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.50200028937864900651745905296366524111610238649612801725164399434009672589297","seed":50200028937864900651745905296366524111610238649612801725164399434009672589297,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3281.583975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"65.chip_sw_all_escalation_resets.29742199209574836485374752943944561762490566676200190221230153865529289434629","seed":29742199209574836485374752943944561762490566676200190221230153865529289434629,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 4036.553880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"94.chip_sw_all_escalation_resets.26817784134837440864266658645210774107350499435516095255310662325017662352342","seed":26817784134837440864266658645210774107350499435516095255310662325017662352342,"line":311,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/94.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2582.334904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1757,"total":2005,"percent":87.63092269326684}