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minutes":[{"name":"csrng_stress_all_with_rand_reset","qual_name":"0.csrng_stress_all_with_rand_reset.76104217104356644049362157689353596924125256984846617834482064936187324386396","seed":76104217104356644049362157689353596924125256984846617834482064936187324386396,"line":null,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"1.csrng_stress_all_with_rand_reset.4264999760589628323892519822665123740478305194910316736930470058330093489755","seed":4264999760589628323892519822665123740478305194910316736930470058330093489755,"line":null,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"4.csrng_stress_all_with_rand_reset.4609243020431340450337873932764482807766854070529434892564763139008541459351","seed":4609243020431340450337873932764482807766854070529434892564763139008541459351,"line":null,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"5.csrng_stress_all_with_rand_reset.97226513395630467686689628045632433501761970186278463079099389665889232909132","seed":97226513395630467686689628045632433501761970186278463079099389665889232909132,"line":null,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log","log_context":[]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"9.csrng_stress_all_with_rand_reset.30707812355364897573828282525864237595242134796858360540816761912420676681016","seed":30707812355364897573828282525864237595242134796858360540816761912420676681016,"line":null,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log","log_context":[]}],"UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE":[{"name":"csrng_regwen","qual_name":"1.csrng_regwen.87587643570241502158642148574469021837802687826112014595905422912496903936617","seed":87587643570241502158642148574469021837802687826112014595905422912496903936617,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_regwen/latest/run.log","log_context":["UVM_INFO @  20427196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"8.csrng_regwen.26199410249708862001206694958057388308892950549872113628506886172570623853555","seed":26199410249708862001206694958057388308892950549872113628506886172570623853555,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/8.csrng_regwen/latest/run.log","log_context":["UVM_INFO @  13112229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"9.csrng_regwen.110528063242506584236809805761445063358652138098336193375403712080875150631530","seed":110528063242506584236809805761445063358652138098336193375403712080875150631530,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/9.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   1586620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"16.csrng_regwen.23410871620401600571227875830926647170753014505409402331669851476966126180681","seed":23410871620401600571227875830926647170753014505409402331669851476966126180681,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/16.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   3783741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"csrng_cmds","qual_name":"2.csrng_cmds.73479580773416033444839867235403051233833565594277940119783561134978899821927","seed":73479580773416033444839867235403051233833565594277940119783561134978899821927,"line":109,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_cmds/latest/run.log","log_context":["UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [*] vs * [*])":[{"name":"csrng_stress_all_with_rand_reset","qual_name":"2.csrng_stress_all_with_rand_reset.25971449701877237621879015059634804884436192969594394149297706704634149342900","seed":25971449701877237621879015059634804884436192969594394149297706704634149342900,"line":117,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 370576284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE":[{"name":"csrng_regwen","qual_name":"3.csrng_regwen.41065662735421973725089043051328116763813166635900627174417337943558676585182","seed":41065662735421973725089043051328116763813166635900627174417337943558676585182,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/3.csrng_regwen/latest/run.log","log_context":["UVM_INFO @  12663417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"6.csrng_regwen.104083261649979779652921436689919584909263236193527388480883489044827438428047","seed":104083261649979779652921436689919584909263236193527388480883489044827438428047,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   6212726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"7.csrng_regwen.26912313353379309763095514214813032695361302069481485917743185419089357673759","seed":26912313353379309763095514214813032695361302069481485917743185419089357673759,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/7.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   2125284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"11.csrng_regwen.48424661398182167210717810679917219924595241437585551018091845573123811320876","seed":48424661398182167210717810679917219924595241437585551018091845573123811320876,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   1542556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"12.csrng_regwen.75163697697973678047415622764286419689863029310113270584005086538101438099375","seed":75163697697973678047415622764286419689863029310113270584005086538101438099375,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/12.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   3105670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_regwen","qual_name":"14.csrng_regwen.82807929644062474394187106201924497641757779555372199907670991611612287667254","seed":82807929644062474394187106201924497641757779555372199907670991611612287667254,"line":99,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/14.csrng_regwen/latest/run.log","log_context":["UVM_INFO @   2605136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started":[{"name":"csrng_stress_all_with_rand_reset","qual_name":"3.csrng_stress_all_with_rand_reset.82637344319565736995233902853838854553398781549486621516537164944866073782749","seed":82637344319565736995233902853838854553398781549486621516537164944866073782749,"line":110,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  87395486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"6.csrng_stress_all_with_rand_reset.27281269661661856412059447181806583641634881945354613219038279906518577927724","seed":27281269661661856412059447181806583641634881945354613219038279906518577927724,"line":157,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2408261858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_stress_all_with_rand_reset","qual_name":"8.csrng_stress_all_with_rand_reset.11208978612989829571044198694811739786181646721069499163493387570244998443991","seed":11208978612989829571044198694811739786181646721069499163493387570244998443991,"line":115,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  60265449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*])":[{"name":"csrng_cmds","qual_name":"5.csrng_cmds.81686941330610841130058752379964321631208539087651759570656834263626458736154","seed":81686941330610841130058752379964321631208539087651759570656834263626458736154,"line":109,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/5.csrng_cmds/latest/run.log","log_context":["UVM_INFO @ 445407195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_cmds","qual_name":"6.csrng_cmds.18341024193876460046930434864119840208636744473874574535941472584019516296298","seed":18341024193876460046930434864119840208636744473874574535941472584019516296298,"line":109,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/6.csrng_cmds/latest/run.log","log_context":["UVM_INFO @  74432582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_cmds","qual_name":"16.csrng_cmds.6689668236352747811236834309207527697459044960173941283046375540915247372728","seed":6689668236352747811236834309207527697459044960173941283046375540915247372728,"line":109,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/16.csrng_cmds/latest/run.log","log_context":["UVM_INFO @ 218613209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq":[{"name":"csrng_stress_all_with_rand_reset","qual_name":"7.csrng_stress_all_with_rand_reset.7578608700936425728994628246739546822413611375250139913082730214617309259513","seed":7578608700936425728994628246739546822413611375250139913082730214617309259513,"line":131,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 504560874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"csrng_stress_all","qual_name":"17.csrng_stress_all.110765331908819556728864461982824396383249550544100255967377229440242040636827","seed":110765331908819556728864461982824396383249550544100255967377229440242040636827,"line":106,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log","log_context":["UVM_INFO @  40896870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits":[{"name":"csrng_cmds","qual_name":"13.csrng_cmds.761039977608151580981321253024975377462586849486966662673541245007019024197","seed":761039977608151580981321253024975377462586849486966662673541245007019024197,"line":103,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/13.csrng_cmds/latest/run.log","log_context":["UVM_INFO @ 562792721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly":[{"name":"csrng_cmds","qual_name":"21.csrng_cmds.34046698526056250131419966671019838913946262884231265076700720895875548882156","seed":34046698526056250131419966671019838913946262884231265076700720895875548882156,"line":118,"log_path":"/nightly/current_run/scratch/master/csrng-sim-xcelium/21.csrng_cmds/latest/run.log","log_context":["UVM_INFO @  11810632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1358,"total":1403,"percent":96.79258731290092}