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[`7a3ad34`](https://github.com/lowrisc/opentitan/tree/7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-01T02:38:09Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":400.12,"sim_time":279331.672125,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.3,"sim_time":84.14743899999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.88,"sim_time":182.36191399999998,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":19.92,"sim_time":574.880659,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":11.53,"sim_time":1380.441996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.3,"sim_time":449.44686700000005,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.88,"sim_time":182.36191399999998,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":11.53,"sim_time":1380.441996,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.82,"sim_time":20.999204000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":2.02,"sim_time":195.754943,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.17,"sim_time":24.863271,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.08,"sim_time":1.705638,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":0.72,"sim_time":4.447407,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":9.2,"sim_time":318.29420899999997,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":9.2,"sim_time":318.29420899999997,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":9.32,"sim_time":3890.9393330000003,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.38,"sim_time":104.889053,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":33.07,"sim_time":29650.672487,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":14.37,"sim_time":15857.540724999999,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":12.86,"sim_time":16622.574855,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":12.86,"sim_time":16622.574855,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":16.99,"sim_time":6268.779698,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":16.99,"sim_time":6268.779698,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":16.99,"sim_time":6268.779698,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":16.99,"sim_time":6268.779698,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":16.99,"sim_time":6268.779698,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":1854.77,"sim_time":1500000.0,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":25.56,"sim_time":19589.523738000004,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":25.56,"sim_time":19589.523738000004,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":25.56,"sim_time":19589.523738000004,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":30.73,"sim_time":5538.287082000001,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":13.38,"sim_time":19747.950230000002,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":25.56,"sim_time":19589.523738000004,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":237.81,"sim_time":206052.358717,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":23.28,"sim_time":4852.310708,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":23.28,"sim_time":4852.310708,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"flash_mode_ignore_cmds":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":175.75,"sim_time":143504.92187400002,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":400.12,"sim_time":279331.672125,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":369.54,"sim_time":238387.338417,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":536.52,"sim_time":258527.83378800002,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.07,"sim_time":42.990104,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.13,"sim_time":146.83879000000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":6.44,"sim_time":241.941927,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":6.44,"sim_time":241.941927,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.3,"sim_time":84.14743899999999,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.88,"sim_time":182.36191399999998,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":11.53,"sim_time":1380.441996,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.71,"sim_time":193.84979800000002,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.3,"sim_time":84.14743899999999,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.88,"sim_time":182.36191399999998,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":11.53,"sim_time":1380.441996,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.71,"sim_time":193.84979800000002,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":356,"total":378,"percent":94.17989417989418},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.56,"sim_time":353.295392,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":27.2,"sim_time":4201.595389,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":27.2,"sim_time":4201.595389,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.89,"branch":98.28,"condition_expression":96.55,"toggle":87.85,"fsm":89.36},"assertion":95.4,"functional":98.86},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.71330589267824835551041093748777902937501756852427084159617163701453775990480","seed":71330589267824835551041093748777902937501756852427084159617163701453775990480,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4346953 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4346953 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.103164597159821056423549971044225831297057565317632619979559425522934454255601","seed":103164597159821056423549971044225831297057565317632619979559425522934454255601,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    953438 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    953438 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.95603614837324557735290266017554524439877527328899982502061553426804897416399","seed":95603614837324557735290266017554524439877527328899982502061553426804897416399,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    975573 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    975573 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.90558757234079556059214623352847463411574909446949898070252883331657722204587","seed":90558757234079556059214623352847463411574909446949898070252883331657722204587,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1303587 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1303587 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[976])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.107240906252112452467831866097355665445216538812650757933262539455805348224744","seed":107240906252112452467831866097355665445216538812650757933262539455805348224744,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1675786 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1675786 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[900])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.47450536481533056825326646458789623279579684573832484072225181088785915730992","seed":47450536481533056825326646458789623279579684573832484072225181088785915730992,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    949811 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    949811 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[981])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.16033038501416329089743490331861701346638027486868770390427204056183222946466","seed":16033038501416329089743490331861701346638027486868770390427204056183222946466,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1537825 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1537825 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.62919308390279997857807909317833282748923114018712714179629866999158636137528","seed":62919308390279997857807909317833282748923114018712714179629866999158636137528,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3739816 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3739816 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.3849671839704065652846196649425883886386341851442041975594220662842761635219","seed":3849671839704065652846196649425883886386341851442041975594220662842761635219,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    763151 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    763151 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[909])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.3063151973672058780240113908785066517683657705824448362745640840598806560399","seed":3063151973672058780240113908785066517683657705824448362745640840598806560399,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2268364 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2268364 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.59263574151868001325493607705478430954618758594407253122018242243716901014087","seed":59263574151868001325493607705478430954618758594407253122018242243716901014087,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4216290 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4216290 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[946])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.88128508109261230449616836618670454835687544256872322241223388876387374661449","seed":88128508109261230449616836618670454835687544256872322241223388876387374661449,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1006634 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1006634 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[968])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.64867151699168179875050244624965540486902953018444363188451711511856733377553","seed":64867151699168179875050244624965540486902953018444363188451711511856733377553,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2027234 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2027234 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[970])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.104229341048034310917194661400263487838445754331835911587604460263932686230315","seed":104229341048034310917194661400263487838445754331835911587604460263932686230315,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1128350 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1128350 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[968])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.34548142607460421796162267737148241944123224560400340415870810086611441879491","seed":34548142607460421796162267737148241944123224560400340415870810086611441879491,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1246335 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1246335 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[980])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.5847060683524506987516976919105637037545795633069058408228082849189851584160","seed":5847060683524506987516976919105637037545795633069058408228082849189851584160,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2297553 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2297553 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.106311483182633498255165673338650114249467242281112697694643211624903320011343","seed":106311483182633498255165673338650114249467242281112697694643211624903320011343,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1037689 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1037689 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[946])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.95597941162671528883704412871170349050519662088181498137442754173052895276748","seed":95597941162671528883704412871170349050519662088181498137442754173052895276748,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1026098 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1026098 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[918])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.54116794597239102469984373096567609926495723183998359313215094378494560677704","seed":54116794597239102469984373096567609926495723183998359313215094378494560677704,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    910916 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    910916 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[952])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.91912466034820383792325086321794373104758170091942245409248832665707980549484","seed":91912466034820383792325086321794373104758170091942245409248832665707980549484,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4479097 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4479097 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[959])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.103987571162690227916555177696725316670240525090643262734005486641990735093032","seed":103987571162690227916555177696725316670240525090643262734005486641990735093032,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   2340407 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x88 [10001000] vs 0x0 [0]) \n","UVM_ERROR @   2373407 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x37e [1101111110] vs 0x0 [0]) \n","UVM_ERROR @   2440407 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x307 [1100000111] vs 0x0 [0]) \n","UVM_ERROR @   2476407 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x344 [1101000100] vs 0x0 [0]) \n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"spi_device_upload","qual_name":"6.spi_device_upload.63571005227440246647085051034201363390683702575121528151437629713343595822751","seed":63571005227440246647085051034201363390683702575121528151437629713343595822751,"line":83,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest/run.log","log_context":["UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":394,"total":416,"percent":94.71153846153847}