{"block":{"name":"sysrst_ctrl","variant":null,"commit":"7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19","commit_short":"7a3ad34","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19","revision_info":"GitHub Revision: [`7a3ad34`](https://github.com/lowrisc/opentitan/tree/7a3ad34b6d483f4d1d69ac670ddb1c45f1172e19)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-01T02:38:09Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":7.82,"sim_time":2112.1900299999998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":8.73,"sim_time":2453.154684,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":7.5,"sim_time":2418.0931269999996,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":6.48,"sim_time":2501.666845,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":10.18,"sim_time":4028.617799,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.01,"sim_time":2064.685179,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":76.55,"sim_time":32255.384573999996,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":3.77,"sim_time":2457.419742,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":6.42,"sim_time":2086.850613,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.01,"sim_time":2064.685179,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.77,"sim_time":2457.419742,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":363.71,"sim_time":157930.378508,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":388.06,"sim_time":173005.341875,"passed":97,"total":100,"percent":97.0}},"passed":97,"total":100,"percent":97.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":627.34,"sim_time":297091.52468800003,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":859.05,"sim_time":423280.30308499996,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":5.52,"sim_time":2511.297188,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":7.79,"sim_time":2194.492146,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":12.71,"sim_time":4767.7397089999995,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":8.85,"sim_time":2609.7033760000004,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":123.80000000000001,"sim_time":1799902.5782060002,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":74.14,"sim_time":33415.199757,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":136.16,"sim_time":77410.723866,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":6.84,"sim_time":2008.718934,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":6.98,"sim_time":2015.808624,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.34,"sim_time":2144.896255,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.34,"sim_time":2144.896255,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":10.18,"sim_time":4028.617799,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.01,"sim_time":2064.685179,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.77,"sim_time":2457.419742,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":32.44,"sim_time":10052.871662000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":10.18,"sim_time":4028.617799,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.01,"sim_time":2064.685179,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":3.77,"sim_time":2457.419742,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":32.44,"sim_time":10052.871662000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":330,"total":334,"percent":98.80239520958084},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":109.03,"sim_time":42010.929042,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":114.09,"sim_time":42500.278176,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":114.09,"sim_time":42500.278176,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":21.24,"sim_time":6622.704582,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.42,"branch":99.52,"condition_expression":97.58,"toggle":100.0,"fsm":94.87},"assertion":98.75,"functional":92.78},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.63592894623358608442040859864861173117239984319860111766411161913132056559410","seed":63592894623358608442040859864861173117239984319860111766411161913132056559410,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2541852695 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 7591852695 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7648703188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"16.sysrst_ctrl_combo_detect_with_pre_cond.24102188418529426859433529151668363564185467248577553478521265162594260852248","seed":24102188418529426859433529151668363564185467248577553478521265162594260852248,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13458333870 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == 1) Unexpected L2H transition of ec_rst_l_o \n","UVM_INFO @ 13458333870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"34.sysrst_ctrl_combo_detect_with_pre_cond.32377507333009256230936492120595541463989423927663047759756467118450014599744","seed":32377507333009256230936492120595541463989423927663047759756467118450014599744,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 26864642696 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 26864642696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"45.sysrst_ctrl_combo_detect_with_pre_cond.79743293037199963962737333960918395150172345444230964524486071299276540503693","seed":79743293037199963962737333960918395150172345444230964524486071299276540503693,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 17593234228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 \n","UVM_INFO @ 17593234228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":406,"total":410,"percent":99.02439024390245}