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(uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_mac_bignum_acc_err","qual_name":"3.otbn_mac_bignum_acc_err.93844463363401503568679712594381037213553246465358034330569670982737916367358","seed":93844463363401503568679712594381037213553246465358034330569670982737916367358,"line":129,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_mac_bignum_acc_err/latest/run.log","log_context":["UVM_INFO @  83633049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"otbn_multi","qual_name":"2.otbn_multi.107015742907650768689387574977394261996962657719502442229264806163092089862111","seed":107015742907650768689387574977394261996962657719502442229264806163092089862111,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_multi/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_single","qual_name":"60.otbn_single.8743681256310061874010007845107565576711230754896808043374279777960119152041","seed":8743681256310061874010007845107565576711230754896808043374279777960119152041,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/60.otbn_single/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.92942533795352168555075915733400248772966930320239471435482796784138805645214","seed":92942533795352168555075915733400248772966930320239471435482796784138805645214,"line":590,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 8820174541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"3.otbn_stress_all_with_rand_reset.23641139750299200888839998377399610613283557056438199284624589255844481865156","seed":23641139750299200888839998377399610613283557056438199284624589255844481865156,"line":165,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1082407996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.87575739747783449436946288492234291923821896521234132924088701335282914447842","seed":87575739747783449436946288492234291923821896521234132924088701335282914447842,"line":193,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 565006886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.43316074360443698286183916722053070493480437394062070507529213297526802673778","seed":43316074360443698286183916722053070493480437394062070507529213297526802673778,"line":217,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 2081821350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:349) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"4.otbn_stress_all_with_rand_reset.19128690964203046413646518757396209095262138093915699945006453477297223044544","seed":19128690964203046413646518757396209095262138093915699945006453477297223044544,"line":261,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 1230293895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.99094099953468762317382688827338609583056063520943636333394590443262936999544","seed":99094099953468762317382688827338609583056063520943636333394590443262936999544,"line":556,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 8505145515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status":[{"name":"otbn_escalate","qual_name":"9.otbn_escalate.85060553176959693478058881484719176698934216963536952701854387871055000863654","seed":85060553176959693478058881484719176698934216963536952701854387871055000863654,"line":105,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_escalate/latest/run.log","log_context":["UVM_INFO @  23747356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_escalate","qual_name":"26.otbn_escalate.23158738810929205873479823536652264452092611131810253395213306861451462477604","seed":23158738810929205873479823536652264452092611131810253395213306861451462477604,"line":105,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/26.otbn_escalate/latest/run.log","log_context":["UVM_INFO @  17458412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":422,"total":436,"percent":96.78899082568807}