{"block":{"name":"spi_device","variant":"1r1w","commit":"d313c7159c9e227d44ccc50f5c3515f9d2cb7668","commit_short":"d313c71","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d313c7159c9e227d44ccc50f5c3515f9d2cb7668","revision_info":"GitHub Revision: [`d313c71`](https://github.com/lowrisc/opentitan/tree/d313c7159c9e227d44ccc50f5c3515f9d2cb7668)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-08T02:25:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":289.11,"sim_time":54135.939206,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.27,"sim_time":349.923387,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.83,"sim_time":117.969977,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":9.7,"sim_time":543.194377,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":4.7,"sim_time":408.496146,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.21,"sim_time":102.39981399999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.83,"sim_time":117.969977,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":4.7,"sim_time":408.496146,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.85,"sim_time":12.255397,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.46,"sim_time":231.53525299999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.16,"sim_time":17.794121,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.09,"sim_time":5.878773,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":0.92,"sim_time":13.800120999999999,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":3.04,"sim_time":3951.490119,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":3.04,"sim_time":3951.490119,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":16.44,"sim_time":30823.794348,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.31,"sim_time":70.284973,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":39.53,"sim_time":112925.976484,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":11.42,"sim_time":2950.683258,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":20.44,"sim_time":16126.026949,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":20.44,"sim_time":16126.026949,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":14.54,"sim_time":2400.8828,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":14.54,"sim_time":2400.8828,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":14.54,"sim_time":2400.8828,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":14.54,"sim_time":2400.8828,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":14.54,"sim_time":2400.8828,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":14.8,"sim_time":11028.033055,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":54.42,"sim_time":14909.453626,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":54.42,"sim_time":14909.453626,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":54.42,"sim_time":14909.453626,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":23.84,"sim_time":3805.793004,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":13.57,"sim_time":2363.283257,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":54.42,"sim_time":14909.453626,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":155.64,"sim_time":119192.934027,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":20.27,"sim_time":12361.118681,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":20.27,"sim_time":12361.118681,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"flash_mode_ignore_cmds":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":330.21,"sim_time":54566.390862,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":289.11,"sim_time":54135.939206,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":414.78,"sim_time":58267.174527,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":476.79,"sim_time":263773.832435,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.12,"sim_time":18.651991000000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.12,"sim_time":15.541221,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":5.9,"sim_time":746.473477,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":5.9,"sim_time":746.473477,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.27,"sim_time":349.923387,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.83,"sim_time":117.969977,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":4.7,"sim_time":408.496146,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.69,"sim_time":327.972826,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.27,"sim_time":349.923387,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.83,"sim_time":117.969977,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":4.7,"sim_time":408.496146,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.69,"sim_time":327.972826,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":356,"total":378,"percent":94.17989417989418},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.55,"sim_time":409.419873,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":22.87,"sim_time":1835.312922,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":22.87,"sim_time":1835.312922,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.89,"branch":98.28,"condition_expression":96.52,"toggle":74.3,"fsm":89.36},"assertion":95.52,"functional":98.81},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.91930925542978815627370291746462237915646695799280158762353275863794333424127","seed":91930925542978815627370291746462237915646695799280158762353275863794333424127,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1951482 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1951482 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[941])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.114582174841609655986753943397120556458568568420071408975631252722817574344114","seed":114582174841609655986753943397120556458568568420071408975631252722817574344114,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4440123 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4440123 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[898])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.11010484523704169488191438710068483747296260818409890024959129701727435520462","seed":11010484523704169488191438710068483747296260818409890024959129701727435520462,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3346436 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3346436 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.1573597493469741443222691175854605669214534577548799861347793522501166140005","seed":1573597493469741443222691175854605669214534577548799861347793522501166140005,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    943341 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    943341 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.114086166659962875652773912351195721473231862740173393559679100931313921650112","seed":114086166659962875652773912351195721473231862740173393559679100931313921650112,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1244483 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1244483 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.60248100191956655328453819795955591528844725005309419500600012825606385470712","seed":60248100191956655328453819795955591528844725005309419500600012825606385470712,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1767311 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1767311 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[953])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.110002447385585744523749977012056543749861893122147934191166400950189432816143","seed":110002447385585744523749977012056543749861893122147934191166400950189432816143,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4918094 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4918094 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[984])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.95270398089287336591481742681784686396807841076170456939899034826306326768109","seed":95270398089287336591481742681784686396807841076170456939899034826306326768109,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2599577 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2599577 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[926])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.65547360432431749189181712023005076561028123770149761808151276365773609718432","seed":65547360432431749189181712023005076561028123770149761808151276365773609718432,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4753764 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4753764 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[896])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.102157497013698982802285269161231501919817770968151252616276400487595569929929","seed":102157497013698982802285269161231501919817770968151252616276400487595569929929,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4416061 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4416061 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[965])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.11642593397612640607588910527413307543569703194262985948363825593328140757740","seed":11642593397612640607588910527413307543569703194262985948363825593328140757740,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    964664 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    964664 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[969])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.93499817004036772145656371071643973852520313832045091659035317444451601023080","seed":93499817004036772145656371071643973852520313832045091659035317444451601023080,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3475535 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3475535 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[933])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.99055965891155989133233264190365426144565102783641098544194539647885504550207","seed":99055965891155989133233264190365426144565102783641098544194539647885504550207,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1113397 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1113397 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1007])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.84642324128906420902436445713395965631390577969484616514667381531874967053251","seed":84642324128906420902436445713395965631390577969484616514667381531874967053251,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1053319 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1053319 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[932])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.86089559820954558472997549841519549406561832242939955724726340237780961364655","seed":86089559820954558472997549841519549406561832242939955724726340237780961364655,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1014105 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1014105 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[929])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.11327000929799411857931968469677249845609447923666536293030549010400780109625","seed":11327000929799411857931968469677249845609447923666536293030549010400780109625,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1008489 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1008489 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[973])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.85706400594376077804053367540969422591370597362611487041689459160073440734565","seed":85706400594376077804053367540969422591370597362611487041689459160073440734565,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1535997 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1535997 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.103318282994363987937292290288962508699931102079930097243059494874092440864353","seed":103318282994363987937292290288962508699931102079930097243059494874092440864353,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3580498 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3580498 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.21250342049800751802004012883688214420761554161109164912720599993850367958063","seed":21250342049800751802004012883688214420761554161109164912720599993850367958063,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2098106 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2098106 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[901])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.1289820389603183676432067544812781433590413515394541552943463299106856622119","seed":1289820389603183676432067544812781433590413515394541552943463299106856622119,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1004931 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1004931 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.52293419999819301958497544188737455808184736952102512060283829310255063172912","seed":52293419999819301958497544188737455808184736952102512060283829310255063172912,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @  11630121 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x353 [1101010011] vs 0x0 [0]) \n","UVM_ERROR @  11634121 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3df [1111011111] vs 0x0 [0]) \n","UVM_ERROR @  11664121 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3ed [1111101101] vs 0x0 [0]) \n","UVM_ERROR @  11751121 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11e [100011110] vs 0x0 [0]) \n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_stress_all","qual_name":"12.spi_device_stress_all.49094794191449288818215932016151154572619458978197991288899757429801507810997","seed":49094794191449288818215932016151154572619458978197991288899757429801507810997,"line":94,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest/run.log","log_context":["UVM_INFO @ 5369523263 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/14\n","UVM_INFO @ 5369523263 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/14\n","UVM_INFO @ 5435543399 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/10\n","UVM_INFO @ 6378103871 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/14\n"]}]}},"passed":394,"total":416,"percent":94.71153846153847}