{"block":{"name":"sysrst_ctrl","variant":null,"commit":"d313c7159c9e227d44ccc50f5c3515f9d2cb7668","commit_short":"d313c71","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/d313c7159c9e227d44ccc50f5c3515f9d2cb7668","revision_info":"GitHub Revision: [`d313c71`](https://github.com/lowrisc/opentitan/tree/d313c7159c9e227d44ccc50f5c3515f9d2cb7668)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-08T02:25:00Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":7.23,"sim_time":2112.980767,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":8.6,"sim_time":2452.510573,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":6.88,"sim_time":2131.6747020000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":5.35,"sim_time":2509.164417,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":12.96,"sim_time":4028.813845,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":6.82,"sim_time":2056.963031,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":82.12,"sim_time":48640.642861,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":5.81,"sim_time":2573.446368,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":4.33,"sim_time":2118.936674,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":6.82,"sim_time":2056.963031,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":5.81,"sim_time":2573.446368,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":348.21,"sim_time":157248.65954300002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":436.59,"sim_time":207513.960181,"passed":90,"total":100,"percent":90.0}},"passed":90,"total":100,"percent":90.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":696.53,"sim_time":325471.314256,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":128.07,"sim_time":180128.692806,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":8.41,"sim_time":2510.55442,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":7.59,"sim_time":2248.631397,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":402.34,"sim_time":186299.465696,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":8.82,"sim_time":2610.326265,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":14.75,"sim_time":58446.011846,"passed":21,"total":25,"percent":84.0}},"passed":21,"total":25,"percent":84.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":91.53,"sim_time":41678.754353,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":3737.03,"sim_time":1759138.43431,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.11,"sim_time":2011.763237,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.17,"sim_time":2011.7492270000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.28,"sim_time":2045.3484300000002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.28,"sim_time":2045.3484300000002,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":12.96,"sim_time":4028.813845,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":6.82,"sim_time":2056.963031,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":5.81,"sim_time":2573.446368,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":12.12,"sim_time":10411.709856000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":12.96,"sim_time":4028.813845,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":6.82,"sim_time":2056.963031,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":5.81,"sim_time":2573.446368,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":12.12,"sim_time":10411.709856000001,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":320,"total":334,"percent":95.80838323353294},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":92.97,"sim_time":42013.879971,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":104.17,"sim_time":42494.422009999995,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":104.17,"sim_time":42494.422009999995,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":12.65,"sim_time":5512.453945,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.27,"branch":99.33,"condition_expression":97.88,"toggle":100.0,"fsm":92.95},"assertion":98.47,"functional":85.08},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"0.sysrst_ctrl_ultra_low_pwr.81337991489188610485914023136462274247085142534984166719560741093699103790753","seed":81337991489188610485914023136462274247085142534984166719560741093699103790753,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 7728781662 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 7728781662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"8.sysrst_ctrl_ultra_low_pwr.70060198354766438693592169470909077080626742112258308194868544820789807225571","seed":70060198354766438693592169470909077080626742112258308194868544820789807225571,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5073118545 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 5073118545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"10.sysrst_ctrl_ultra_low_pwr.29672494158654484348479771832890112078936100679822031074943652845188508409168","seed":29672494158654484348479771832890112078936100679822031074943652845188508409168,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 4242444227 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 5177444227 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 5189045578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"17.sysrst_ctrl_ultra_low_pwr.14758063699869288646017004569414178632249956954977833744922682956488167018805","seed":14758063699869288646017004569414178632249956954977833744922682956488167018805,"line":655,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 7690811404 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 9260811404 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 9272978278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"15.sysrst_ctrl_combo_detect_with_pre_cond.46689197047876214191504510199490876148805132170431430568876052846021454346528","seed":46689197047876214191504510199490876148805132170431430568876052846021454346528,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 15706850957 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 15706850957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"16.sysrst_ctrl_combo_detect_with_pre_cond.2663219313643976804981183280107570016825187047267951054064400824252759831500","seed":2663219313643976804981183280107570016825187047267951054064400824252759831500,"line":683,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 36140930039 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 36140930039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"42.sysrst_ctrl_combo_detect_with_pre_cond.95551761493086367071535673059303479176840517777583714267392848061433811585807","seed":95551761493086367071535673059303479176840517777583714267392848061433811585807,"line":673,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 43652245675 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 43652245675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"97.sysrst_ctrl_combo_detect_with_pre_cond.64642969124288213804166072633213179987894277038940384155739403248470909924097","seed":64642969124288213804166072633213179987894277038940384155739403248470909924097,"line":712,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 77014043250 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 77014043250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"20.sysrst_ctrl_combo_detect_with_pre_cond.7183677269790129290703916407692063938189338388514093175687703262851439225468","seed":7183677269790129290703916407692063938189338388514093175687703262851439225468,"line":700,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 58733574085 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x25\n","UVM_INFO @ 58733709506 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c\n","UVM_INFO @ 59650713775 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 59651051360 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"67.sysrst_ctrl_combo_detect_with_pre_cond.27606182544041506472707783940079718505137820983205667730673324716486717962592","seed":27606182544041506472707783940079718505137820983205667730673324716486717962592,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 26728883686 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27\n","UVM_INFO @ 26729003686 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1a\n","UVM_INFO @ 27041400599 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 27041400599 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"33.sysrst_ctrl_combo_detect_with_pre_cond.6048128765164790226267081242397247328096365507597798190979652407957550287050","seed":6048128765164790226267081242397247328096365507597798190979652407957550287050,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 12969770603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0\n","UVM_INFO @ 13104770603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 13124770603 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 23148945066 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1f\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"36.sysrst_ctrl_combo_detect_with_pre_cond.78733592519840611318016657633450421166616866852720408531824268801963960583618","seed":78733592519840611318016657633450421166616866852720408531824268801963960583618,"line":673,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 18740367718 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0\n","UVM_INFO @ 18885367718 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 18905367718 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 28983156798 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x21\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"73.sysrst_ctrl_combo_detect_with_pre_cond.4380316070857934068422837179418895054567855431076026354419056176313045834863","seed":4380316070857934068422837179418895054567855431076026354419056176313045834863,"line":675,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 29579518765 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 \n","UVM_INFO @ 29579518765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"91.sysrst_ctrl_combo_detect_with_pre_cond.97831482936363709680161120165263507265918197273192329169070555602877553130680","seed":97831482936363709680161120165263507265918197273192329169070555602877553130680,"line":692,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 64230200231 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x23\n","UVM_INFO @ 64230320231 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x17\n","UVM_INFO @ 64677702233 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 64677920231 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2\n"]}]}},"passed":396,"total":410,"percent":96.58536585365853}