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pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"0.otbn_stress_all_with_rand_reset.95875250748285630009456799732973352391667276494058232930166301971844783768298","seed":95875250748285630009456799732973352391667276494058232930166301971844783768298,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"2.otbn_stress_all_with_rand_reset.108279859877066109235596317562496353017474553849795210631698659988984379502443","seed":108279859877066109235596317562496353017474553849795210631698659988984379502443,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"4.otbn_stress_all_with_rand_reset.52864279988259882704571078053680630656285322503324088557535007685232440768548","seed":52864279988259882704571078053680630656285322503324088557535007685232440768548,"line":null,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed":[{"name":"otbn_urnd_err","qual_name":"0.otbn_urnd_err.79524800506202914864193309098311142626282277053820193531040104254148876833931","seed":79524800506202914864193309098311142626282277053820193531040104254148876833931,"line":116,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_urnd_err/latest/run.log","log_context":["UVM_ERROR @  15336723 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A\n","UVM_INFO @  15336723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed":[{"name":"otbn_stack_addr_integ_chk","qual_name":"0.otbn_stack_addr_integ_chk.50477020844302495465208529112424827137500830131010792181298039365735066721276","seed":50477020844302495465208529112424827137500830131010792181298039365735066721276,"line":135,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log","log_context":["UVM_ERROR @   7761903 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @   7761903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_escalate","qual_name":"2.otbn_escalate.15135070522513822684884608175571527356968440995747822310142999240080655380160","seed":15135070522513822684884608175571527356968440995747822310142999240080655380160,"line":117,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/2.otbn_escalate/latest/run.log","log_context":["UVM_ERROR @  12990534 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @  12990534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"otbn_stack_addr_integ_chk","qual_name":"3.otbn_stack_addr_integ_chk.79489068205267959516576303435222907618720892350346963239729484910285893469987","seed":79489068205267959516576303435222907618720892350346963239729484910285893469987,"line":122,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_stack_addr_integ_chk/latest/run.log","log_context":["xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 9426590 PS) Assertion tb.model_if.NoModelErrs has failed \n","UVM_ERROR @   9426590 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A\n","UVM_INFO @   9426590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error":[{"name":"otbn_alu_bignum_mod_err","qual_name":"1.otbn_alu_bignum_mod_err.93361590890349587128590984575014869812588944015401896732036849442459756888266","seed":93361590890349587128590984575014869812588944015401896732036849442459756888266,"line":115,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_alu_bignum_mod_err/latest/run.log","log_context":["UVM_INFO @ 143144394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_partial_wipe","qual_name":"4.otbn_partial_wipe.19311906243858916547896448222446558738971102491088574180061168651983570595522","seed":19311906243858916547896448222446558738971102491088574180061168651983570595522,"line":112,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log","log_context":["UVM_INFO @  42677321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_partial_wipe","qual_name":"8.otbn_partial_wipe.96747970186333353340492080567615076265097025073214174348360810931653192299859","seed":96747970186333353340492080567615076265097025073214174348360810931653192299859,"line":108,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log","log_context":["UVM_INFO @ 233487990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"1.otbn_stress_all_with_rand_reset.36492028671831024291685187784029345909788880915875349065947425914899922652928","seed":36492028671831024291685187784029345909788880915875349065947425914899922652928,"line":552,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3659695603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"8.otbn_stress_all_with_rand_reset.31682321344799787390271288302872457040041338499064064346053467854504434383937","seed":31682321344799787390271288302872457040041338499064064346053467854504434383937,"line":162,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 471728615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,186): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS)":[{"name":"otbn_partial_wipe","qual_name":"3.otbn_partial_wipe.88070473800914122887942791222301029467203468703628244922456647368064114210956","seed":88070473800914122887942791222301029467203468703628244922456647368064114210956,"line":118,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log","log_context":["UVM_ERROR @   7951384 ps: (otbn_idle_checker.sv:186) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A\n","UVM_INFO @   7951384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"6.otbn_stress_all_with_rand_reset.38087654619322674731252322889180086649774667398428326637624261086554905602073","seed":38087654619322674731252322889180086649774667398428326637624261086554905602073,"line":198,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 972971682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.83283571135046742215286285717315900856114431969543761338425170561191248393250","seed":83283571135046742215286285717315900856114431969543761338425170561191248393250,"line":162,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  58488323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status":[{"name":"otbn_escalate","qual_name":"53.otbn_escalate.84839985336593423372841246936286902380062126349801654236736335272158103344969","seed":84839985336593423372841246936286902380062126349801654236736335272158103344969,"line":114,"log_path":"/nightly/current_run/scratch/master/otbn-sim-xcelium/53.otbn_escalate/latest/run.log","log_context":["UVM_INFO @   5149589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":420,"total":436,"percent":96.3302752293578}