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[`e6fb888`](https://github.com/lowrisc/opentitan/tree/e6fb888ff636ad15425df7316b6429a9f3d336b0)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-15T02:51:09Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":360.99,"sim_time":197764.006394,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.26,"sim_time":38.474525,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.55,"sim_time":87.99632700000001,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":27.88,"sim_time":15486.230451,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":7.73,"sim_time":407.196298,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.34,"sim_time":55.281334,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.55,"sim_time":87.99632700000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":7.73,"sim_time":407.196298,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.9,"sim_time":12.282881999999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.29,"sim_time":145.409138,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":39,"total":40,"percent":97.5},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.18,"sim_time":68.68308400000001,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.1,"sim_time":18.390262,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":1.07,"sim_time":4.230258,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":4.65,"sim_time":598.406022,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":4.65,"sim_time":598.406022,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":11.22,"sim_time":60691.441073,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.24,"sim_time":98.58316599999999,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":36.46,"sim_time":45376.193935999996,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":26.54,"sim_time":53203.638551,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":20.7,"sim_time":117762.186592,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":20.7,"sim_time":117762.186592,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":22.49,"sim_time":10879.320357,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":22.49,"sim_time":10879.320357,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":22.49,"sim_time":10879.320357,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":22.49,"sim_time":10879.320357,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":22.49,"sim_time":10879.320357,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":15.96,"sim_time":58248.295718999994,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":34.66,"sim_time":10969.748342,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":34.66,"sim_time":10969.748342,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":34.66,"sim_time":10969.748342,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":22.3,"sim_time":3259.8235959999997,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":8.33,"sim_time":1144.7426950000001,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":34.66,"sim_time":10969.748342,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":347.94,"sim_time":149907.238458,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":18.57,"sim_time":1858.004146,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":18.57,"sim_time":1858.004146,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"flash_mode_ignore_cmds":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":1297.63,"sim_time":1500000.0,"passed":13,"total":15,"percent":86.66666666666667}},"passed":13,"total":15,"percent":86.66666666666667},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":360.99,"sim_time":197764.006394,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":502.31,"sim_time":76474.081049,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":752.99,"sim_time":357283.274607,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.08,"sim_time":50.11331,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.13,"sim_time":14.315457,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":5.04,"sim_time":223.51243,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":5.04,"sim_time":223.51243,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.26,"sim_time":38.474525,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.55,"sim_time":87.99632700000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":7.73,"sim_time":407.196298,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.67,"sim_time":215.166229,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.26,"sim_time":38.474525,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.55,"sim_time":87.99632700000001,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":7.73,"sim_time":407.196298,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":3.67,"sim_time":215.166229,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":353,"total":378,"percent":93.3862433862434},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.52,"sim_time":246.031801,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":22.93,"sim_time":6145.662654,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":22.93,"sim_time":6145.662654,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.9,"branch":98.3,"condition_expression":96.53,"toggle":74.3,"fsm":89.36},"assertion":95.52,"functional":99.21},"cov_report_page":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.93464473551520884873468186697012162343082976100084755650349916070702760289320","seed":93464473551520884873468186697012162343082976100084755650349916070702760289320,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1042229 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1042229 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[898])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.97958150098892991697672777203380398950303792014592292875615450696102230888174","seed":97958150098892991697672777203380398950303792014592292875615450696102230888174,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4263284 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4263284 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[927])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.58137121169789082002274882690026526617563208349056416749957032811424260160715","seed":58137121169789082002274882690026526617563208349056416749957032811424260160715,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4216047 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4216047 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[914])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.26222558715866815443720279275710117182975870530828701011246101821241535660669","seed":26222558715866815443720279275710117182975870530828701011246101821241535660669,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1005200 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1005200 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[971])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.23091500627762811267435603019905504286768998639378494003897811765253912723201","seed":23091500627762811267435603019905504286768998639378494003897811765253912723201,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2359909 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2359909 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.19942999114903182609205998602676858313029796894169781180759474503334362510672","seed":19942999114903182609205998602676858313029796894169781180759474503334362510672,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1385216 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1385216 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1002])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.85662875915094794099996267070988745229564008954813610485291811140015104721877","seed":85662875915094794099996267070988745229564008954813610485291811140015104721877,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1192851 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1192851 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[953])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.2633181775115902594067118219548634406946818840779851940592089438368504727764","seed":2633181775115902594067118219548634406946818840779851940592089438368504727764,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1144226 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1144226 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[949])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.108077990735923471156312378128569223105814787130276621841617582429934894503177","seed":108077990735923471156312378128569223105814787130276621841617582429934894503177,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   6457077 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   6457077 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.105308276976877560158785944325752673507761796804779594718696669575798471352568","seed":105308276976877560158785944325752673507761796804779594718696669575798471352568,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3860568 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3860568 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[924])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.19524237913812673135029322716623783456596279622225950865926270886557271808368","seed":19524237913812673135029322716623783456596279622225950865926270886557271808368,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3503993 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3503993 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1003])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.107853471586602992590056604218153364342328945069380569902516549734948549005572","seed":107853471586602992590056604218153364342328945069380569902516549734948549005572,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1248539 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1248539 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[908])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.73110441182356813182534915201686763501639142547666647342710472336085367824394","seed":73110441182356813182534915201686763501639142547666647342710472336085367824394,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4598665 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4598665 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.104015230858044918520788415388707011961306213061029575933108363742226460567919","seed":104015230858044918520788415388707011961306213061029575933108363742226460567919,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1029459 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1029459 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[899])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.53007399460784790075743404327624723264840003059492763845535071088336977386050","seed":53007399460784790075743404327624723264840003059492763845535071088336977386050,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4684033 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4684033 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[974])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.22910685522657122417905646418273990138555173582203608572102793635710792137989","seed":22910685522657122417905646418273990138555173582203608572102793635710792137989,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    789386 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    789386 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[986])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.58082265036433664328250215947368639839230734330155373426853039231320962223089","seed":58082265036433664328250215947368639839230734330155373426853039231320962223089,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3670641 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3670641 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[981])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.28923241417017643832227887909323357435818696042411820416783719734554682654228","seed":28923241417017643832227887909323357435818696042411820416783719734554682654228,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @  11515262 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @  11515262 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[929])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.39797576505642755521887459783476781216626993348191888296145779493851366661986","seed":39797576505642755521887459783476781216626993348191888296145779493851366661986,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4252648 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4252648 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[997])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.102303988160946246481574079874729420772547292701537271796733459118998409092189","seed":102303988160946246481574079874729420772547292701537271796733459118998409092189,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2392468 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2392468 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.5508734665673876303360353207823864615905184334951937062521497106834036306509","seed":5508734665673876303360353207823864615905184334951937062521497106834036306509,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   2066258 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x49 [1001001] vs 0x0 [0]) \n","UVM_ERROR @   2116258 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x374 [1101110100] vs 0x0 [0]) \n","UVM_ERROR @   2175258 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e9 [1011101001] vs 0x0 [0]) \n","UVM_ERROR @   2248258 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18 [11000] vs 0x0 [0]) \n"]}],"UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"spi_device_flash_mode_ignore_cmds","qual_name":"1.spi_device_flash_mode_ignore_cmds.82476256108039120312743231228775967775036021098558806553269751929908305079060","seed":82476256108039120312743231228775967775036021098558806553269751929908305079060,"line":87,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest/run.log","log_context":["UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (spi_device_scoreboard.sv:2513) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_and_tpm","qual_name":"3.spi_device_flash_and_tpm.86765096858570295550145377326693343447056836300421783348828525080419524022504","seed":86765096858570295550145377326693343447056836300421783348828525080419524022504,"line":93,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log","log_context":["UVM_INFO @ 6164202498 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/12\n","UVM_INFO @ 6543304026 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/6\n","UVM_INFO @ 6543304026 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/6\n","tl_ul_fuzzy_flash_status_q[i] = 0x6fdf90\n"]},{"name":"spi_device_flash_all","qual_name":"21.spi_device_flash_all.99363173859726155259949565143121856354432704772253832167406217400362180683832","seed":99363173859726155259949565143121856354432704772253832167406217400362180683832,"line":92,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest/run.log","log_context":["tl_ul_fuzzy_flash_status_q[i] = 0xf75c44\n","tl_ul_fuzzy_flash_status_q[i] = 0xf75c44\n","tl_ul_fuzzy_flash_status_q[i] = 0xf75c44\n","UVM_INFO @ 2672234041 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/10\n"]}],"UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be *":[{"name":"spi_device_flash_mode_ignore_cmds","qual_name":"5.spi_device_flash_mode_ignore_cmds.51829551047238165372273531724540586245071857629132309258956872238094425669841","seed":51829551047238165372273531724540586245071857629132309258956872238094425669841,"line":102,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest/run.log","log_context":["UVM_INFO @ 4355870118 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/9\n","UVM_INFO @ 4355870118 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 8/9\n","UVM_INFO @ 4817475996 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/9\n","UVM_INFO @ 4846068281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}]}},"passed":391,"total":416,"percent":93.99038461538461}