{"block":{"name":"chip","variant":null,"commit":"34ceb5eb568742f75f01ee23de994ad9f65eae82","commit_short":"34ceb5e","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/34ceb5eb568742f75f01ee23de994ad9f65eae82","revision_info":"GitHub Revision: [`34ceb5e`](https://github.com/lowrisc/opentitan/tree/34ceb5eb568742f75f01ee23de994ad9f65eae82)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-22T09:08:29Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html","stages":{"V1":{"testpoints":{"chip_sw_example_tests":{"tests":{"chip_sw_example_rom":{"max_time":197.42,"sim_time":2171.801224,"passed":3,"total":3,"percent":100.0},"chip_sw_example_manufacturer":{"max_time":304.75,"sim_time":2407.0653859999998,"passed":3,"total":3,"percent":100.0},"chip_sw_example_concurrency":{"max_time":421.17,"sim_time":2868.4146880000003,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"csr_hw_reset":{"tests":{"chip_csr_hw_reset":{"max_time":881.89,"sim_time":11309.840397,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"chip_csr_rw":{"max_time":1291.83,"sim_time":13356.480742,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"chip_csr_bit_bash":{"max_time":2116.29,"sim_time":16664.198110999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"chip_csr_aliasing":{"max_time":8398.67,"sim_time":39942.595122,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"chip_csr_mem_rw_with_rand_reset":{"max_time":1145.81,"sim_time":13599.80233,"passed":1,"total":5,"percent":20.0}},"passed":1,"total":5,"percent":20.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"chip_csr_aliasing":{"max_time":8398.67,"sim_time":39942.595122,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":1291.83,"sim_time":13356.480742,"passed":5,"total":5,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":12.19,"sim_time":226.825088,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"chip_sw_gpio_out":{"tests":{"chip_sw_gpio":{"max_time":633.64,"sim_time":4251.6681260000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_in":{"tests":{"chip_sw_gpio":{"max_time":633.64,"sim_time":4251.6681260000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_irq":{"tests":{"chip_sw_gpio":{"max_time":633.64,"sim_time":4251.6681260000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_uart_tx_rx":{"tests":{"chip_sw_uart_tx_rx":{"max_time":783.56,"sim_time":3936.859803,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_uart_rx_overflow":{"tests":{"chip_sw_uart_tx_rx":{"max_time":783.56,"sim_time":3936.859803,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx1":{"max_time":757.66,"sim_time":4942.251031999999,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx2":{"max_time":873.63,"sim_time":4640.676068,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_idx3":{"max_time":789.11,"sim_time":4250.430233,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_baud_rate":{"tests":{"chip_sw_uart_rand_baudrate":{"max_time":3333.92,"sim_time":13126.819574,"passed":20,"total":20,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq":{"tests":{"chip_sw_uart_tx_rx_alt_clk_freq":{"max_time":1748.13,"sim_time":7804.765497,"passed":5,"total":5,"percent":100.0},"chip_sw_uart_tx_rx_alt_clk_freq_low_speed":{"max_time":1944.7900000000002,"sim_time":13118.570494000001,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":121,"total":125,"percent":96.8},"V2":{"testpoints":{"chip_pin_mux":{"tests":{"chip_padctrl_attributes":{"max_time":923.75,"sim_time":9763.489761,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"chip_padctrl_attributes":{"tests":{"chip_padctrl_attributes":{"max_time":923.75,"sim_time":9763.489761,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"chip_sw_sleep_pin_mio_dio_val":{"tests":{"chip_sw_sleep_pin_mio_dio_val":{"max_time":474.83,"sim_time":3230.857132,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sleep_pin_wake":{"tests":{"chip_sw_sleep_pin_wake":{"max_time":319.64,"sim_time":3266.79434,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_sleep_pin_retention":{"tests":{"chip_sw_sleep_pin_retention":{"max_time":399.56,"sim_time":3141.699502,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_tap_strap_sampling":{"tests":{"chip_tap_straps_dev":{"max_time":2148.24,"sim_time":15564.049576,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_testunlock0":{"max_time":815.74,"sim_time":7496.397258999999,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":750.6,"sim_time":6262.33781,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":789.22,"sim_time":7348.546585,"passed":5,"total":5,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"chip_sw_data_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":835.0,"sim_time":5154.707835,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_instruction_integrity":{"tests":{"chip_sw_data_integrity_escalation":{"max_time":835.0,"sim_time":5154.707835,"passed":6,"total":6,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_ast_clk_outputs":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":1319.63,"sim_time":7972.1943710000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_rst_inputs":{"tests":{"chip_sw_ast_clk_rst_inputs":{"max_time":3410.64,"sim_time":14550.102724999999,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_ast_sys_clk_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":6231.95,"sim_time":19040.030566,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":355.46,"sim_time":3499.945151,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1582.28,"sim_time":7110.912712,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":402.21,"sim_time":3026.166817,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":2878.5,"sim_time":12965.105832000001,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":397.7,"sim_time":3022.3624139999997,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":766.21,"sim_time":4674.786068,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":408.15,"sim_time":3063.358589,"passed":3,"total":3,"percent":100.0}},"passed":24,"total":24,"percent":100.0},"chip_sw_ast_usb_clk_calib":{"tests":{"chip_sw_usb_ast_clk_calib":{"max_time":363.74,"sim_time":3271.035043,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_sensor_ctrl_ast_alerts":{"tests":{"chip_sw_sensor_ctrl_alert":{"max_time":1370.77,"sim_time":8600.465272,"passed":5,"total":5,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":380.73,"sim_time":3157.718724,"passed":0,"total":3,"percent":0.0}},"passed":5,"total":8,"percent":62.5},"chip_sw_sensor_ctrl_ast_status":{"tests":{"chip_sw_sensor_ctrl_status":{"max_time":383.72,"sim_time":2515.536852,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"tests":{"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup":{"max_time":380.73,"sim_time":3157.718724,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_smoketest":{"tests":{"chip_sw_aes_smoketest":{"max_time":417.04,"sim_time":2949.220718,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_smoketest":{"max_time":385.11,"sim_time":2390.8919330000003,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_smoketest":{"max_time":304.03,"sim_time":2745.39515,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_smoketest":{"max_time":344.16,"sim_time":2787.04714,"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_smoketest":{"max_time":1871.62,"sim_time":7206.635781999999,"passed":3,"total":3,"percent":100.0},"chip_sw_gpio_smoketest":{"max_time":424.45,"sim_time":3184.922946,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_smoketest":{"max_time":455.29,"sim_time":3045.890288,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_smoketest":{"max_time":429.39,"sim_time":2591.309391,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_smoketest":{"max_time":2235.7,"sim_time":8118.227758999999,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":681.19,"sim_time":5781.530673,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usbdev_smoketest":{"max_time":684.99,"sim_time":5323.167664,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_plic_smoketest":{"max_time":376.68,"sim_time":3355.575167,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_timer_smoketest":{"max_time":416.76,"sim_time":3068.083439,"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_smoketest":{"max_time":339.48,"sim_time":2486.467147,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_smoketest":{"max_time":363.47,"sim_time":2596.590625,"passed":3,"total":3,"percent":100.0},"chip_sw_uart_smoketest":{"max_time":358.05,"sim_time":3370.429659,"passed":3,"total":3,"percent":100.0}},"passed":48,"total":48,"percent":100.0},"chip_sw_otp_smoketest":{"tests":{"chip_sw_otp_ctrl_smoketest":{"max_time":352.76,"sim_time":2407.351095,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_functests":{"tests":{"rom_keymgr_dpe_functest":{"max_time":715.03,"sim_time":4768.367264,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_boot":{"tests":{"chip_sw_uart_tx_rx_bootstrap":{"max_time":28800.208922402002,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_secure_boot":{"tests":{"rom_e2e_smoke":{"max_time":5264.23,"sim_time":14953.108454,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_raw_unlock":{"tests":{"rom_raw_unlock":{"max_time":921.09,"sim_time":10795.114639000001,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_power_idle_load":{"tests":{"chip_sw_power_idle_load":{"max_time":791.92,"sim_time":4307.792622000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_power_sleep_load":{"tests":{"chip_sw_power_sleep_load":{"max_time":634.99,"sim_time":9775.335908,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_sw_exit_test_unlocked_bootstrap":{"tests":{"chip_sw_exit_test_unlocked_bootstrap":{"max_time":13200.197949882597,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"tl_d_oob_addr_access":{"tests":{"chip_tl_errors":{"max_time":3600.1973035540427,"sim_time":0.0,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_illegal_access":{"tests":{"chip_tl_errors":{"max_time":3600.1973035540427,"sim_time":0.0,"passed":3,"total":30,"percent":10.0}},"passed":3,"total":30,"percent":10.0},"tl_d_outstanding_access":{"tests":{"chip_csr_aliasing":{"max_time":8398.67,"sim_time":39942.595122,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":5664.82,"sim_time":34185.550476000004,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":881.89,"sim_time":11309.840397,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":1291.83,"sim_time":13356.480742,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"chip_csr_aliasing":{"max_time":8398.67,"sim_time":39942.595122,"passed":1,"total":1,"percent":100.0},"chip_same_csr_outstanding":{"max_time":5664.82,"sim_time":34185.550476000004,"passed":5,"total":5,"percent":100.0},"chip_csr_hw_reset":{"max_time":881.89,"sim_time":11309.840397,"passed":1,"total":1,"percent":100.0},"chip_csr_rw":{"max_time":1291.83,"sim_time":13356.480742,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":93.45,"sim_time":2062.250833,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":7.86,"sim_time":52.925022,"passed":50,"total":50,"percent":100.0},"xbar_smoke_large_delays":{"max_time":127.6,"sim_time":11248.016503,"passed":50,"total":50,"percent":100.0},"xbar_smoke_slow_rsp":{"max_time":107.07,"sim_time":6634.5525609999995,"passed":50,"total":50,"percent":100.0},"xbar_random_zero_delays":{"max_time":48.53,"sim_time":519.598343,"passed":50,"total":50,"percent":100.0},"xbar_random_large_delays":{"max_time":537.95,"sim_time":50106.441628,"passed":50,"total":50,"percent":100.0},"xbar_random_slow_rsp":{"max_time":512.48,"sim_time":30250.314075,"passed":50,"total":50,"percent":100.0}},"passed":300,"total":300,"percent":100.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":61.910000000000004,"sim_time":1180.094753,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":62.199999999999996,"sim_time":1339.053513,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":89.05,"sim_time":2236.364647,"passed":50,"total":50,"percent":100.0},"xbar_error_and_unmapped_addr":{"max_time":62.199999999999996,"sim_time":1339.053513,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":150.34,"sim_time":3159.321613,"passed":50,"total":50,"percent":100.0},"xbar_access_same_device_slow_rsp":{"max_time":1193.05,"sim_time":70481.186044,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":87.92,"sim_time":2517.862481,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":777.9,"sim_time":17705.320286,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_error":{"max_time":703.31,"sim_time":15660.917068,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":1351.55,"sim_time":26628.71673,"passed":50,"total":50,"percent":100.0},"xbar_stress_all_with_reset_error":{"max_time":1116.21,"sim_time":22723.463174,"passed":50,"total":50,"percent":100.0}},"passed":100,"total":100,"percent":100.0},"rom_e2e_smoke":{"tests":{"rom_e2e_smoke":{"max_time":5264.23,"sim_time":14953.108454,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_output":{"tests":{"rom_e2e_shutdown_output":{"max_time":6400.78,"sim_time":42843.32536,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_shutdown_exception_c":{"tests":{"rom_e2e_shutdown_exception_c":{"max_time":5933.54,"sim_time":30263.33916,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_boot_policy_valid":{"tests":{"rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0":{"max_time":4084.0299999999997,"sim_time":11763.693587,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_dev":{"max_time":5616.87,"sim_time":16476.678938,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod":{"max_time":5543.83,"sim_time":16552.28806,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_prod_end":{"max_time":5736.1,"sim_time":15660.624319,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_good_rma":{"max_time":5456.02,"sim_time":15470.871509999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0":{"max_time":4072.92,"sim_time":12121.115597999998,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_dev":{"max_time":5732.01,"sim_time":15683.767893999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod":{"max_time":5746.71,"sim_time":17444.911033,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_prod_end":{"max_time":5632.66,"sim_time":16003.521768999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_good_b_bad_rma":{"max_time":5332.62,"sim_time":15336.706279999999,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0":{"max_time":7308.370000000001,"sim_time":17738.197539,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_dev":{"max_time":9783.72,"sim_time":24760.027399,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod":{"max_time":9524.74,"sim_time":24229.512762,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_prod_end":{"max_time":9710.38,"sim_time":25812.053359,"passed":1,"total":1,"percent":100.0},"rom_e2e_boot_policy_valid_a_bad_b_good_rma":{"max_time":9480.42,"sim_time":23817.887721,"passed":1,"total":1,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_sigverify_always":{"tests":{"rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0":{"max_time":7700.200000000001,"sim_time":28517.041537999998,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_dev":{"max_time":10329.84,"sim_time":38618.085048,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod":{"max_time":9790.22,"sim_time":29556.964574,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_prod_end":{"max_time":9237.59,"sim_time":29948.595402,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_bad_rma":{"max_time":9506.82,"sim_time":30390.035563,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0":{"max_time":4437.9,"sim_time":15890.310378,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_dev":{"max_time":6045.03,"sim_time":27731.272897,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod":{"max_time":5821.76,"sim_time":21337.260553,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_prod_end":{"max_time":5594.8,"sim_time":19606.008744,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_bad_b_nothing_rma":{"max_time":4795.52,"sim_time":13815.882668,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0":{"max_time":4604.48,"sim_time":17069.323579999997,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_dev":{"max_time":5969.79,"sim_time":28307.00562,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod":{"max_time":5498.19,"sim_time":19466.917096,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_prod_end":{"max_time":5066.67,"sim_time":14899.553704,"passed":1,"total":1,"percent":100.0},"rom_e2e_sigverify_always_a_nothing_b_bad_rma":{"max_time":5460.75,"sim_time":22349.5841,"passed":1,"total":1,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_asm_init":{"tests":{"rom_e2e_asm_init_test_unlocked0":{"max_time":4475.92,"sim_time":15742.640959,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_dev":{"max_time":5788.97,"sim_time":15342.907232000001,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_prod":{"max_time":5820.48,"sim_time":15763.329668,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_prod_end":{"max_time":5839.19,"sim_time":15858.54989,"passed":3,"total":3,"percent":100.0},"rom_e2e_asm_init_rma":{"max_time":5514.83,"sim_time":15104.559185,"passed":3,"total":3,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"rom_e2e_keymgr_dpe_init":{"tests":{"rom_e2e_keymgr_dpe_init_rom_ext_meas":{"max_time":10933.29,"sim_time":29712.670684,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_dpe_init_rom_ext_no_meas":{"max_time":10851.72,"sim_time":28988.184704,"passed":3,"total":3,"percent":100.0},"rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas":{"max_time":10842.25,"sim_time":32121.483589,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"rom_e2e_static_critical":{"tests":{"rom_e2e_static_critical":{"max_time":5827.27,"sim_time":16553.395416,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_debug_cable_irq":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.195131128654,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"tests":{"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.195131128654,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aes_enc":{"tests":{"chip_sw_aes_enc":{"max_time":394.48,"sim_time":2687.850858,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":355.46,"sim_time":3499.945151,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_aes_entropy":{"tests":{"chip_sw_aes_entropy":{"max_time":329.04,"sim_time":2708.838472,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"tests":{"chip_sw_aes_idle":{"max_time":421.98,"sim_time":2813.6999690000002,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aes_sideload":{"tests":{"chip_sw_keymgr_dpe_sideload_aes":{"max_time":3449.0,"sim_time":12894.480075,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_alerts":{"tests":{"chip_sw_alert_test":{"max_time":428.12,"sim_time":2855.249702,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_escalations":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":790.69,"sim_time":4708.343196000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_escalation_resets":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"chip_sw_alert_handler_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":971.86,"sim_time":5076.167265,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":623.06,"sim_time":3593.2368229999997,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":757.71,"sim_time":3554.225145,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_alert_handler_entropy":{"tests":{"chip_sw_alert_handler_entropy":{"max_time":462.4,"sim_time":2926.35009,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_crashdump":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":2040.9099999999999,"sim_time":10822.440233,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_timeout":{"tests":{"chip_sw_alert_handler_ping_timeout":{"max_time":765.85,"sim_time":5411.399682,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_alerts":{"max_time":391.69,"sim_time":3112.9712799999998,"passed":0,"total":90,"percent":0.0}},"passed":0,"total":90,"percent":0.0},"chip_sw_alert_handler_lpg_sleep_mode_pings":{"tests":{"chip_sw_alert_handler_lpg_sleep_mode_pings":{"max_time":408.86,"sim_time":3091.283432,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_alert_handler_lpg_clock_off":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":2115.26,"sim_time":8148.55007,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_lpg_reset_toggle":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":2206.47,"sim_time":8276.274991999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_ping_ok":{"tests":{"chip_sw_alert_handler_ping_ok":{"max_time":1692.77,"sim_time":8141.640593,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"tests":{"chip_sw_alert_handler_reverse_ping_in_deep_sleep":{"max_time":14400.187498139216,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_aon_timer_wakeup_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":530.25,"sim_time":3445.470806,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wakeup":{"tests":{"chip_sw_pwrmgr_smoketest":{"max_time":681.19,"sim_time":5781.530673,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bark_irq":{"tests":{"chip_sw_aon_timer_irq":{"max_time":530.25,"sim_time":3445.470806,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":988.51,"sim_time":8493.663095,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wdog_bite_reset":{"tests":{"chip_sw_aon_timer_wdog_bite_reset":{"max_time":988.51,"sim_time":8493.663095,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"tests":{"chip_sw_aon_timer_sleep_wdog_sleep_pause":{"max_time":550.87,"sim_time":6680.518176,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_aon_timer_wdog_lc_escalate":{"tests":{"chip_sw_aon_timer_wdog_lc_escalate":{"max_time":781.83,"sim_time":4377.515163,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_idle_trans":{"tests":{"chip_sw_otbn_randomness":{"max_time":1247.09,"sim_time":5878.937451999999,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_idle":{"max_time":421.98,"sim_time":2813.6999690000002,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_idle":{"max_time":424.87,"sim_time":2750.632305,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"max_time":380.68,"sim_time":2898.499972,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_trans":{"tests":{"chip_sw_clkmgr_off_aes_trans":{"max_time":734.7,"sim_time":4013.915771000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_hmac_trans":{"max_time":598.48,"sim_time":4279.439472,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_kmac_trans":{"max_time":733.51,"sim_time":4372.138411999999,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_off_otbn_trans":{"max_time":659.96,"sim_time":4479.2390350000005,"passed":3,"total":3,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"chip_sw_clkmgr_off_peri":{"tests":{"chip_sw_clkmgr_off_peri":{"max_time":1891.82,"sim_time":10088.573077,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_div":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":808.32,"sim_time":3969.306284,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":803.32,"sim_time":5150.852649,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":786.38,"sim_time":3719.510476,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":849.19,"sim_time":5024.074552,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":808.39,"sim_time":4299.416133000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":812.24,"sim_time":5099.585755,"passed":3,"total":3,"percent":100.0},"chip_sw_ast_clk_outputs":{"max_time":1319.63,"sim_time":7972.1943710000005,"passed":3,"total":3,"percent":100.0}},"passed":21,"total":21,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"tests":{"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":3121.4,"sim_time":26163.086185,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw":{"tests":{"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":786.38,"sim_time":3719.510476,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":849.19,"sim_time":5024.074552,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_clkmgr_jitter":{"tests":{"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":6231.95,"sim_time":19040.030566,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en":{"max_time":355.46,"sim_time":3499.945151,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs_jitter":{"max_time":1582.28,"sim_time":7110.912712,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":402.21,"sim_time":3026.166817,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":2878.5,"sim_time":12965.105832000001,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":397.7,"sim_time":3022.3624139999997,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":766.21,"sim_time":4674.786068,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_jitter":{"max_time":408.15,"sim_time":3063.358589,"passed":3,"total":3,"percent":100.0}},"passed":24,"total":24,"percent":100.0},"chip_sw_clkmgr_extended_range":{"tests":{"chip_sw_clkmgr_jitter_reduced_freq":{"max_time":345.23,"sim_time":2785.060299,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq":{"max_time":6607.5,"sim_time":25299.399247999998,"passed":3,"total":3,"percent":100.0},"chip_sw_aes_enc_jitter_en_reduced_freq":{"max_time":359.6,"sim_time":2672.68498,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en_reduced_freq":{"max_time":360.18,"sim_time":2998.437685,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq":{"max_time":2462.79,"sim_time":11368.769645,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq":{"max_time":402.45,"sim_time":3390.0640240000002,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq":{"max_time":727.56,"sim_time":4148.242194,"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_concurrency_reduced_freq":{"max_time":28800.200957555327,"sim_time":0.0,"passed":1,"total":3,"percent":33.333333333333336}},"passed":22,"total":24,"percent":91.66666666666667},"chip_sw_clkmgr_deep_sleep_frequency":{"tests":{"chip_sw_ast_clk_outputs":{"max_time":1319.63,"sim_time":7972.1943710000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_sleep_frequency":{"tests":{"chip_sw_clkmgr_sleep_frequency":{"max_time":835.92,"sim_time":5101.860068,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_reset_frequency":{"tests":{"chip_sw_clkmgr_reset_frequency":{"max_time":913.97,"sim_time":7765.69228,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"chip_sw_clkmgr_alert_handler_clock_enables":{"tests":{"chip_sw_alert_handler_lpg_clkoff":{"max_time":2115.26,"sim_time":8148.55007,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_edn_cmd":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3952.3600000000006,"sim_time":23887.243816,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_fuse_en_sw_app_read":{"tests":{"chip_sw_csrng_fuse_en_sw_app_read_test":{"max_time":654.86,"sim_time":4202.3137879999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_lc_hw_debug_en":{"tests":{"chip_sw_csrng_lc_hw_debug_en_test":{"max_time":1515.22,"sim_time":9124.29769,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_csrng_known_answer_tests":{"tests":{"chip_sw_csrng_kat_test":{"max_time":395.74,"sim_time":2933.3161090000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"tests":{"chip_sw_csrng_edn_concurrency":{"max_time":14182.8,"sim_time":41958.993196999996,"passed":10,"total":10,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"max_time":404.22,"sim_time":3114.309092,"passed":3,"total":3,"percent":100.0},"chip_sw_edn_entropy_reqs":{"max_time":1482.71,"sim_time":6677.135123,"passed":3,"total":3,"percent":100.0}},"passed":16,"total":16,"percent":100.0},"chip_sw_entropy_src_ast_rng_req":{"tests":{"chip_sw_entropy_src_ast_rng_req":{"max_time":404.22,"sim_time":3114.309092,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_csrng":{"tests":{"chip_sw_entropy_src_csrng":{"max_time":3952.3600000000006,"sim_time":23887.243816,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_entropy_src_known_answer_tests":{"tests":{"chip_sw_entropy_src_kat_test":{"max_time":348.13,"sim_time":3238.850156,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc":{"tests":{"chip_sw_hmac_enc":{"max_time":361.38,"sim_time":3149.739525,"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_enc_jitter_en":{"max_time":402.21,"sim_time":3026.166817,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_hmac_idle":{"tests":{"chip_sw_hmac_enc_idle":{"max_time":424.87,"sim_time":2750.632305,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_all_configurations":{"tests":{"chip_sw_hmac_oneshot":{"max_time":2924.16,"sim_time":11764.575471999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_hmac_multistream_mode":{"tests":{"chip_sw_hmac_multistream":{"max_time":3420.01,"sim_time":12010.320001,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_i2c_host_tx_rx":{"tests":{"chip_sw_i2c_host_tx_rx":{"max_time":843.04,"sim_time":4844.865984,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx1":{"max_time":975.7600000000001,"sim_time":5777.113334,"passed":3,"total":3,"percent":100.0},"chip_sw_i2c_host_tx_rx_idx2":{"max_time":954.45,"sim_time":4812.228626,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_i2c_device_tx_rx":{"tests":{"chip_sw_i2c_device_tx_rx":{"max_time":682.49,"sim_time":4343.679968,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":3231.88,"sim_time":12073.747064,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation_jitter_en":{"max_time":2878.5,"sim_time":12965.105832000001,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_keymgr_dpe_sideload_kmac":{"tests":{"chip_sw_keymgr_dpe_sideload_kmac":{"max_time":3311.73,"sim_time":12622.024421,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_sideload_aes":{"tests":{"chip_sw_keymgr_dpe_sideload_aes":{"max_time":3449.0,"sim_time":12894.480075,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_sideload_otbn":{"tests":{"chip_sw_keymgr_dpe_sideload_otbn":{"max_time":3600.22636197973,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_kmac_enc":{"tests":{"chip_sw_kmac_mode_cshake":{"max_time":425.5,"sim_time":2902.569741,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac":{"max_time":439.87,"sim_time":3147.6585529999998,"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_mode_kmac_jitter_en":{"max_time":397.7,"sim_time":3022.3624139999997,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_kmac_app_keymgr_dpe":{"tests":{"chip_sw_keymgr_dpe_key_derivation":{"max_time":3231.88,"sim_time":12073.747064,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_app_lc":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_kmac_app_rom":{"tests":{"chip_sw_kmac_app_rom":{"max_time":809.97,"sim_time":7999.363923999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_entropy":{"tests":{"chip_sw_kmac_entropy":{"max_time":3020.53,"sim_time":10936.595098,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_kmac_idle":{"tests":{"chip_sw_kmac_idle":{"max_time":380.68,"sim_time":2898.499972,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_alert_handler_escalation":{"tests":{"chip_sw_alert_handler_escalation":{"max_time":790.69,"sim_time":4708.343196000001,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_jtag_access":{"tests":{"chip_tap_straps_dev":{"max_time":2148.24,"sim_time":15564.049576,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":750.6,"sim_time":6262.33781,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":789.22,"sim_time":7348.546585,"passed":5,"total":5,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"chip_sw_lc_ctrl_otp_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":414.93,"sim_time":3220.351225,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_lc_ctrl_transitions":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_lc_ctrl_kmac_req":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_lc_ctrl_key_div":{"tests":{"chip_sw_keymgr_dpe_key_derivation_prod":{"max_time":3255.71,"sim_time":11913.237806,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_lc_ctrl_broadcast":{"tests":{"chip_sw_rram_rma_unlocked":{"max_time":735.95,"sim_time":10010.400001,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":556.85,"sim_time":3633.032073,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":1096.45,"sim_time":6201.177064,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":1209.7,"sim_time":6500.201362,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":1192.48,"sim_time":6450.514108,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_rram_ctrl_lc_rw_en":{"max_time":709.71,"sim_time":5461.709388,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":3231.88,"sim_time":12073.747064,"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"max_time":1676.49,"sim_time":20777.684275,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_execution_main":{"max_time":1120.65,"sim_time":7048.865837,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_lc":{"max_time":3121.4,"sim_time":26163.086185,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0":{"max_time":808.32,"sim_time":3969.306284,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0":{"max_time":803.32,"sim_time":5150.852649,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_dev":{"max_time":786.38,"sim_time":3719.510476,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_dev":{"max_time":849.19,"sim_time":5024.074552,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_fast_rma":{"max_time":808.39,"sim_time":4299.416133000001,"passed":3,"total":3,"percent":100.0},"chip_sw_clkmgr_external_clk_src_for_sw_slow_rma":{"max_time":812.24,"sim_time":5099.585755,"passed":3,"total":3,"percent":100.0},"chip_tap_straps_dev":{"max_time":2148.24,"sim_time":15564.049576,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_rma":{"max_time":750.6,"sim_time":6262.33781,"passed":5,"total":5,"percent":100.0},"chip_tap_straps_prod":{"max_time":789.22,"sim_time":7348.546585,"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"max_time":211.3,"sim_time":4671.36073,"passed":0,"total":3,"percent":0.0}},"passed":68,"total":81,"percent":83.95061728395062},"chip_lc_scrap":{"tests":{"chip_sw_lc_ctrl_rma_to_scrap":{"max_time":658.11,"sim_time":4904.576308000001,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_raw_to_scrap":{"max_time":885.04,"sim_time":9099.122727,"passed":0,"total":1,"percent":0.0},"chip_sw_lc_ctrl_test_locked0_to_scrap":{"max_time":694.45,"sim_time":8333.168440000001,"passed":1,"total":1,"percent":100.0},"chip_sw_lc_ctrl_rand_to_scrap":{"max_time":1615.38,"sim_time":26175.114952,"passed":2,"total":3,"percent":66.66666666666667}},"passed":4,"total":6,"percent":66.66666666666667},"chip_lc_test_locked":{"tests":{"chip_sw_lc_walkthrough_testunlocks":{"max_time":3600.199551062659,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"chip_rv_dm_lc_disabled":{"max_time":211.3,"sim_time":4671.36073,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_lc_walkthrough":{"tests":{"chip_sw_lc_walkthrough_dev":{"max_time":2600.75,"sim_time":20463.394904,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prod":{"max_time":2682.66,"sim_time":20034.414350000003,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_prodend":{"max_time":2305.31,"sim_time":18726.821583,"passed":3,"total":3,"percent":100.0},"chip_sw_lc_walkthrough_rma":{"max_time":1789.04,"sim_time":14980.635442,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_walkthrough_testunlocks":{"max_time":3600.199551062659,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":15,"percent":20.0},"chip_sw_lc_ctrl_volatile_raw_unlock":{"tests":{"chip_sw_lc_ctrl_volatile_raw_unlock":{"max_time":1480.08,"sim_time":26219.845362,"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz":{"max_time":1376.52,"sim_time":25769.138084,"passed":2,"total":3,"percent":66.66666666666667},"rom_volatile_raw_unlock":{"max_time":414.51,"sim_time":5272.702421,"passed":2,"total":3,"percent":66.66666666666667}},"passed":6,"total":9,"percent":66.66666666666667},"chip_sw_otbn_op":{"tests":{"chip_sw_otbn_ecdsa_op_irq":{"max_time":5984.08,"sim_time":17509.673541,"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_ecdsa_op_irq_jitter_en":{"max_time":6231.95,"sim_time":19040.030566,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_otbn_rnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":1247.09,"sim_time":5878.937451999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_urnd_entropy":{"tests":{"chip_sw_otbn_randomness":{"max_time":1247.09,"sim_time":5878.937451999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_idle":{"tests":{"chip_sw_otbn_randomness":{"max_time":1247.09,"sim_time":5878.937451999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otbn_mem_scramble":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":711.3,"sim_time":3283.300916,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_otp_ctrl_init":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_otp_ctrl_keys":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":711.3,"sim_time":3283.300916,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":3231.88,"sim_time":12073.747064,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":855.49,"sim_time":4844.970192,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":3600.1989358169953,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":9,"total":12,"percent":75.0},"chip_sw_otp_ctrl_entropy":{"tests":{"chip_sw_otbn_mem_scramble":{"max_time":711.3,"sim_time":3283.300916,"passed":3,"total":3,"percent":100.0},"chip_sw_keymgr_dpe_key_derivation":{"max_time":3231.88,"sim_time":12073.747064,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access":{"max_time":855.49,"sim_time":4844.970192,"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":3600.1989358169953,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":9,"total":12,"percent":75.0},"chip_sw_otp_ctrl_program":{"tests":{"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":11,"total":15,"percent":73.33333333333333},"chip_sw_otp_ctrl_program_error":{"tests":{"chip_sw_lc_ctrl_program_error":{"max_time":932.48,"sim_time":5485.365677,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_hw_cfg0":{"tests":{"chip_sw_lc_ctrl_otp_hw_cfg0":{"max_time":414.93,"sim_time":3220.351225,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals":{"tests":{"chip_sw_otp_ctrl_lc_signals_test_unlocked0":{"max_time":556.85,"sim_time":3633.032073,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_dev":{"max_time":1096.45,"sim_time":6201.177064,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_prod":{"max_time":1209.7,"sim_time":6500.201362,"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_lc_signals_rma":{"max_time":1192.48,"sim_time":6450.514108,"passed":0,"total":3,"percent":0.0},"chip_sw_lc_ctrl_transition":{"max_time":3461.66,"sim_time":26812.362043,"passed":11,"total":15,"percent":73.33333333333333}},"passed":20,"total":27,"percent":74.07407407407408},"chip_sw_otp_ctrl_dai_lock":{"tests":{"chip_sw_otp_ctrl_dai_lock":{"max_time":1500.95,"sim_time":6908.084098,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_pwrmgr_external_full_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":618.23,"sim_time":7745.363428999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_random_sleep_all_wake_ups":{"max_time":313.23,"sim_time":3188.480616,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_wake_ups":{"max_time":356.29,"sim_time":2645.042972,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_por_reset":{"max_time":922.22,"sim_time":8157.39907,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_por_reset":{"tests":{"chip_sw_pwrmgr_normal_sleep_por_reset":{"max_time":653.7,"sim_time":4769.096164,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_wake_ups":{"max_time":2137.43,"sim_time":21357.507941,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_deep_sleep_all_reset_reqs":{"max_time":1763.36,"sim_time":15168.303512,"passed":3,"total":3,"percent":100.0},"chip_sw_aon_timer_wdog_bite_reset":{"max_time":988.51,"sim_time":8493.663095,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_normal_sleep_all_reset_reqs":{"max_time":450.11,"sim_time":3941.235688,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"tests":{"chip_sw_pwrmgr_wdog_reset":{"max_time":826.09,"sim_time":3891.905773,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_full_aon_reset":{"max_time":618.23,"sim_time":7745.363428999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_main_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_main_power_glitch_reset":{"max_time":612.23,"sim_time":4140.460623,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_random_sleep_power_glitch_reset":{"max_time":1102.92,"sim_time":10861.246712,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_deep_sleep_power_glitch_reset":{"max_time":644.61,"sim_time":6058.2580259999995,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_power_glitch_reset":{"tests":{"chip_sw_pwrmgr_sleep_power_glitch_reset":{"max_time":295.86,"sim_time":2441.308736,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"tests":{"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":731.13,"sim_time":8361.615456,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1347.85,"sim_time":7021.937940999999,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1721.82,"sim_time":9010.231478,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_pwrmgr_b2b_sleep_reset_req":{"tests":{"chip_sw_pwrmgr_b2b_sleep_reset_req":{"max_time":3273.45,"sim_time":23278.067931,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_sleep_disabled":{"tests":{"chip_sw_pwrmgr_sleep_disabled":{"max_time":451.71,"sim_time":3505.141498,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"chip_sw_rom_access":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":1676.49,"sim_time":20777.684275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rom_ctrl_integrity_check":{"tests":{"chip_sw_rom_ctrl_integrity_check":{"max_time":1676.49,"sim_time":20777.684275,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_non_sys_reset_info":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1721.82,"sim_time":9010.231478,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_random_sleep_all_reset_reqs":{"max_time":731.13,"sim_time":8361.615456,"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_wdog_reset":{"max_time":826.09,"sim_time":3891.905773,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_smoketest":{"max_time":681.19,"sim_time":5781.530673,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":12,"percent":75.0},"chip_sw_rstmgr_sys_reset_info":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":723.74,"sim_time":5046.327985999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_cpu_info":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":885.71,"sim_time":5951.572534,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_req_reset":{"tests":{"chip_sw_rstmgr_sw_req":{"max_time":596.05,"sim_time":3548.028895,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_alert_info":{"tests":{"chip_sw_rstmgr_alert_info":{"max_time":2040.9099999999999,"sim_time":10822.440233,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_sw_rst":{"tests":{"chip_sw_rstmgr_sw_rst":{"max_time":401.01,"sim_time":2981.3870690000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rstmgr_escalation_reset":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"chip_sw_rstmgr_alert_handler_reset_enables":{"tests":{"chip_sw_alert_handler_lpg_reset_toggle":{"max_time":2206.47,"sim_time":8276.274991999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_nmi_irq":{"tests":{"chip_sw_rv_core_ibex_nmi_irq":{"max_time":919.41,"sim_time":4475.495898,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_rnd":{"tests":{"chip_sw_rv_core_ibex_rnd":{"max_time":1055.96,"sim_time":4886.985364,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_address_translation":{"tests":{"chip_sw_rv_core_ibex_address_translation":{"max_time":419.74,"sim_time":3239.2244330000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_icache_scrambled_access":{"tests":{"chip_sw_rv_core_ibex_icache_invalidate":{"max_time":3600.1989358169953,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_core_ibex_fault_dump":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":885.71,"sim_time":5951.572534,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_double_fault":{"tests":{"chip_sw_rstmgr_cpu_info":{"max_time":885.71,"sim_time":5951.572534,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_mcounteren_writable":{"tests":{"chip_sw_rv_core_ibex_mcounteren_writable":{"max_time":332.78,"sim_time":2610.8818960000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_csr_rw":{"tests":{"chip_jtag_csr_rw":{"max_time":2956.25,"sim_time":24148.691358,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_jtag_mem_access":{"tests":{"chip_jtag_mem_access":{"max_time":2729.73,"sim_time":23632.183892,"passed":1,"total":3,"percent":33.333333333333336}},"passed":1,"total":3,"percent":33.333333333333336},"chip_rv_dm_ndm_reset_req":{"tests":{"chip_rv_dm_ndm_reset_req":{"max_time":723.74,"sim_time":5046.327985999999,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"tests":{"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted":{"max_time":450.81,"sim_time":2795.046918,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_rv_dm_access_after_wakeup":{"tests":{"chip_sw_rv_dm_access_after_wakeup":{"max_time":376.05,"sim_time":2889.657318,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_jtag_tap_sel":{"tests":{"chip_tap_straps_rma":{"max_time":750.6,"sim_time":6262.33781,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_rv_dm_lc_disabled":{"tests":{"chip_rv_dm_lc_disabled":{"max_time":211.3,"sim_time":4671.36073,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_plic_all_irqs":{"tests":{"chip_plic_all_irqs_0":{"max_time":971.86,"sim_time":5076.167265,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_10":{"max_time":623.06,"sim_time":3593.2368229999997,"passed":3,"total":3,"percent":100.0},"chip_plic_all_irqs_20":{"max_time":757.71,"sim_time":3554.225145,"passed":3,"total":3,"percent":100.0}},"passed":9,"total":9,"percent":100.0},"chip_sw_plic_sw_irq":{"tests":{"chip_sw_plic_sw_irq":{"max_time":300.45,"sim_time":2299.778476,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_timer":{"tests":{"chip_sw_rv_timer_irq":{"max_time":305.01,"sim_time":2894.718631,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_flash_mode":{"tests":{"rom_e2e_smoke":{"max_time":5264.23,"sim_time":14953.108454,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through":{"tests":{"chip_sw_spi_device_pass_through":{"max_time":713.06,"sim_time":5334.875526,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_device_pass_through_collision":{"tests":{"chip_sw_spi_device_pass_through_collision":{"max_time":415.03,"sim_time":2875.972799,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_tpm":{"tests":{"chip_sw_spi_device_tpm":{"max_time":530.37,"sim_time":3180.583568,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_spi_host_tx_rx":{"tests":{"chip_sw_spi_host_tx_rx":{"max_time":395.59,"sim_time":3009.1360980000004,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_scrambled_access":{"tests":{"chip_sw_sram_ctrl_scrambled_access":{"max_time":855.49,"sim_time":4844.970192,"passed":3,"total":3,"percent":100.0},"chip_sw_sram_ctrl_scrambled_access_jitter_en":{"max_time":766.21,"sim_time":4674.786068,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sleep_sram_ret_contents":{"tests":{"chip_sw_sleep_sram_ret_contents_no_scramble":{"max_time":406.14,"sim_time":3062.025662,"passed":0,"total":3,"percent":0.0},"chip_sw_sleep_sram_ret_contents_scramble":{"max_time":438.62,"sim_time":2773.777588,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":6,"percent":0.0},"chip_sw_sram_execution":{"tests":{"chip_sw_sram_ctrl_execution_main":{"max_time":1120.65,"sim_time":7048.865837,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sram_lc_escalation":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0},"chip_sw_data_integrity_escalation":{"max_time":835.0,"sim_time":5154.707835,"passed":6,"total":6,"percent":100.0}},"passed":100,"total":106,"percent":94.33962264150944},"chip_sw_sysrst_ctrl_reset":{"tests":{"chip_sw_pwrmgr_sysrst_ctrl_reset":{"max_time":1347.85,"sim_time":7021.937940999999,"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_reset":{"max_time":2328.44,"sim_time":22765.62369,"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"chip_sw_sysrst_ctrl_inputs":{"tests":{"chip_sw_sysrst_ctrl_inputs":{"max_time":370.58,"sim_time":3118.550142,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_outputs":{"tests":{"chip_sw_sysrst_ctrl_outputs":{"max_time":453.33,"sim_time":3782.334994,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_sysrst_ctrl_in_irq":{"tests":{"chip_sw_sysrst_ctrl_in_irq":{"max_time":748.29,"sim_time":4613.659363,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_wakeup":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":2328.44,"sim_time":22765.62369,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_sleep_reset":{"tests":{"chip_sw_sysrst_ctrl_reset":{"max_time":2328.44,"sim_time":22765.62369,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ec_rst_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":4519.3,"sim_time":20015.759879999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_flash_wp_l":{"tests":{"chip_sw_sysrst_ctrl_ec_rst_l":{"max_time":4519.3,"sim_time":20015.759879999998,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"tests":{"chip_sw_sysrst_ctrl_ulp_z3_wakeup":{"max_time":789.3,"sim_time":6332.987208,"passed":3,"total":3,"percent":100.0},"chip_sw_adc_ctrl_sleep_debug_cable_wakeup":{"max_time":3600.195131128654,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":6,"percent":50.0},"chip_sw_usbdev_vbus":{"tests":{"chip_sw_usbdev_vbus":{"max_time":313.4,"sim_time":2269.895227,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pullup":{"tests":{"chip_sw_usbdev_pullup":{"max_time":320.28,"sim_time":2502.370187,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_aon_pullup":{"tests":{"chip_sw_usbdev_aon_pullup":{"max_time":536.2,"sim_time":3150.710568,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_setup_rx":{"tests":{"chip_sw_usbdev_setuprx":{"max_time":663.85,"sim_time":3982.027054,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_config_host":{"tests":{"chip_sw_usbdev_config_host":{"max_time":2031.0400000000002,"sim_time":8159.454065999998,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_pincfg":{"tests":{"chip_sw_usbdev_pincfg":{"max_time":9549.11,"sim_time":32140.136356,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_tx_rx":{"tests":{"chip_sw_usbdev_dpi":{"max_time":2929.53,"sim_time":11841.214595000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"chip_sw_usbdev_toggle_restore":{"tests":{"chip_sw_usbdev_toggle_restore":{"max_time":338.76,"sim_time":2775.71711,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":1507,"total":1754,"percent":85.91790193842645},"V2S":{"testpoints":{"chip_sw_aes_masking_off":{"tests":{"chip_sw_aes_masking_off":{"max_time":465.41,"sim_time":3405.707092,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_rv_core_ibex_lockstep_glitch":{"tests":{"chip_sw_rv_core_ibex_lockstep_glitch":{"max_time":259.54,"sim_time":2198.764672,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"V3":{"testpoints":{"chip_sw_coremark":{"tests":{"chip_sw_coremark":{"max_time":18000.197669330053,"sim_time":0.0,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_power_max_load":{"tests":{"chip_sw_power_virus":{"max_time":2019.71,"sim_time":6907.5257520000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"rom_e2e_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":151.47,"sim_time":2159.939,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":144.62,"sim_time":2355.214,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":123.51999999999998,"sim_time":1908.147,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_jtag_inject":{"tests":{"rom_e2e_jtag_inject_test_unlocked0":{"max_time":149.62,"sim_time":2705.620088,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_dev":{"max_time":138.28,"sim_time":2244.354521,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_inject_rma":{"max_time":146.34,"sim_time":2519.230405,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"rom_e2e_self_hash":{"tests":{"rom_e2e_self_hash":{"max_time":75.59941364079714,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_clkmgr_jitter_cycle_measurements":{"tests":{"chip_sw_clkmgr_jitter_frequency":{"max_time":545.84,"sim_time":3110.3675350000003,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_edn_boot_mode":{"tests":{"chip_sw_edn_boot_mode":{"max_time":630.63,"sim_time":2874.8710180000003,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_auto_mode":{"tests":{"chip_sw_edn_auto_mode":{"max_time":1697.43,"sim_time":5447.8293810000005,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_sw_mode":{"tests":{"chip_sw_edn_sw_mode":{"max_time":2229.78,"sim_time":8875.746485,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_edn_kat":{"tests":{"chip_sw_edn_kat":{"max_time":478.02,"sim_time":2297.4550099999997,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_otp_ctrl_escalation":{"tests":{"chip_sw_otp_ctrl_escalation":{"max_time":550.22,"sim_time":3685.3630580000004,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"chip_sw_sensor_ctrl_deep_sleep_wake_up":{"tests":{"chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up":{"max_time":620.8,"sim_time":5700.112363,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"tests":{"chip_sw_pwrmgr_usb_clk_disabled_when_active":{"max_time":693.1,"sim_time":4483.768319,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_sw_all_resets":{"tests":{"chip_sw_pwrmgr_all_reset_reqs":{"max_time":1721.82,"sim_time":9010.231478,"passed":3,"total":3,"percent":100.0}},"passed":3,"total":3,"percent":100.0},"chip_rv_dm_perform_debug":{"tests":{"rom_e2e_jtag_debug_test_unlocked0":{"max_time":151.47,"sim_time":2159.939,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_dev":{"max_time":144.62,"sim_time":2355.214,"passed":0,"total":1,"percent":0.0},"rom_e2e_jtag_debug_rma":{"max_time":123.51999999999998,"sim_time":1908.147,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_rv_dm_access_after_hw_reset":{"tests":{"chip_sw_rv_dm_access_after_escalation_reset":{"max_time":753.68,"sim_time":4777.592352,"passed":2,"total":3,"percent":66.66666666666667}},"passed":2,"total":3,"percent":66.66666666666667},"chip_sw_plic_alerts":{"tests":{"chip_sw_all_escalation_resets":{"max_time":958.89,"sim_time":5847.3686880000005,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"tick_configuration":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.19005527813,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"counter_wrap":{"tests":{"chip_sw_rv_timer_systick_test":{"max_time":7200.19005527813,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_spi_device_output_when_disabled_or_sleeping":{"tests":{"chip_sw_spi_device_pinmux_sleep_retention":{"max_time":350.4,"sim_time":3103.50529,"passed":0,"total":3,"percent":0.0}},"passed":0,"total":3,"percent":0.0},"chip_sw_uart_watermarks":{"tests":{"chip_sw_uart_tx_rx":{"max_time":783.56,"sim_time":3936.859803,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"chip_sw_usbdev_stream":{"tests":{"chip_sw_usbdev_stream":{"max_time":5459.17,"sim_time":18420.266293,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":126,"total":153,"percent":82.3529411764706},"unmapped":{"testpoints":{"Unmapped":{"tests":{"chip_sw_rstmgr_rst_cnsty_escalation":{"max_time":74.56,"sim_time":10.200001,"passed":0,"total":3,"percent":0.0},"chip_sw_otp_ctrl_rot_auth_config":{"max_time":2175.68,"sim_time":17484.277775,"passed":0,"total":1,"percent":0.0},"chip_sw_otp_ctrl_descrambling":{"max_time":472.86,"sim_time":2845.3756940000003,"passed":3,"total":3,"percent":100.0},"chip_sw_pwrmgr_lowpower_cancel":{"max_time":296.42,"sim_time":3121.884354,"passed":0,"total":3,"percent":0.0},"chip_sw_pwrmgr_sleep_wake_5_bug":{"max_time":15.816397010348737,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_flash_erase":{"max_time":1293.89,"sim_time":10010.400001,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_one_frame":{"max_time":10800.201605584472,"sim_time":0.0,"passed":0,"total":3,"percent":0.0},"ate_bootstrap_disjoint":{"max_time":10800.19715839997,"sim_time":0.0,"passed":0,"total":3,"percent":0.0}},"passed":3,"total":22,"percent":13.636363636363637}},"passed":3,"total":22,"percent":13.636363636363637}},"coverage":{"code":{"block":null,"line_statement":93.99,"branch":94.38,"condition_expression":92.41,"toggle":72.06,"fsm":33.33},"assertion":97.34,"functional":98.8},"cov_report_page":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path":[{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"0.chip_sw_rstmgr_rst_cnsty_escalation.96212373366039062063800968263887204041978679116481303103790542417373906499963","seed":96212373366039062063800968263887204041978679116481303103790542417373906499963,"line":364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"1.chip_sw_rstmgr_rst_cnsty_escalation.64279901564762120010038463395769171125777520751504615560302345342409614092828","seed":64279901564762120010038463395769171125777520751504615560302345342409614092828,"line":364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rstmgr_rst_cnsty_escalation","qual_name":"2.chip_sw_rstmgr_rst_cnsty_escalation.45956758609754620662391790120439396663880907064804198725670658177690555130746","seed":45956758609754620662391790120439396663880907064804198725670658177690555130746,"line":364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log","log_context":["UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error":[{"name":"chip_sw_sleep_pin_wake","qual_name":"0.chip_sw_sleep_pin_wake.38849578446644071430205037984140718197566244565983149901250040746574675147171","seed":38849578446644071430205037984140718197566244565983149901250040746574675147171,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_INFO @ 3011.603154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"0.chip_sw_sleep_pin_retention.2061912099091832488974772003821917939398985456834929830711614499661900277232","seed":2061912099091832488974772003821917939398985456834929830711614499661900277232,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log","log_context":["UVM_INFO @ 2742.144552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pinmux_sleep_retention","qual_name":"0.chip_sw_spi_device_pinmux_sleep_retention.51993056390466852558461113279715351522370632953110478168888036592332487647904","seed":51993056390466852558461113279715351522370632953110478168888036592332487647904,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log","log_context":["UVM_INFO @ 2298.389718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.48926971816243057412458425387106110531289079943308816277547897983751330324185","seed":48926971816243057412458425387106110531289079943308816277547897983751330324185,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 6883.198662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.46944469551202614464126579506399348943482695593083307392618498344399176449418","seed":46944469551202614464126579506399348943482695593083307392618498344399176449418,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 3941.235688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_normal_sleep_por_reset.46311307924488053457137244421863887878463609442699759187424973720025123083215","seed":46311307924488053457137244421863887878463609442699759187424973720025123083215,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 4769.096164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"0.chip_sw_sleep_sram_ret_contents_no_scramble.99466393470389541688210960533020234427971584768871252821433449072193362085930","seed":99466393470389541688210960533020234427971584768871252821433449072193362085930,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 2606.818098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"0.chip_sw_sleep_sram_ret_contents_scramble.11935169460040600335664299929828209090231766536282123819825806795877531381081","seed":11935169460040600335664299929828209090231766536282123819825806795877531381081,"line":380,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 2773.777588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.24900586005514435679685506335120787776264800912311728624637804922215426105612","seed":24900586005514435679685506335120787776264800912311728624637804922215426105612,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 2100.304488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.17679030798419991976496338314298149969037329952954537528781962570534288167195","seed":17679030798419991976496338314298149969037329952954537528781962570534288167195,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 5101.860068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.76268417147875385792797177030089405206447506951026702679634579202578074485187","seed":76268417147875385792797177030089405206447506951026702679634579202578074485187,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2645.042972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"0.chip_sw_pwrmgr_lowpower_cancel.52521494600859551587781469995714265763717062917032669333068554346013126307798","seed":52521494600859551587781469995714265763717062917032669333068554346013126307798,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 3121.884354 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_wake_ups.59470752544268976277712447085805989665371678469786573183133892317579573461805","seed":59470752544268976277712447085805989665371678469786573183133892317579573461805,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2842.486752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.74592446378886892009479120886368252578540317835769710490450545269383959158631","seed":74592446378886892009479120886368252578540317835769710490450545269383959158631,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2822.065560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.36582357199847339239492429940128420560571174393125436126179990673637278460023","seed":36582357199847339239492429940128420560571174393125436126179990673637278460023,"line":386,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3838.001832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.6766933511851476621842569539761779459863556541949811033442999609968154574532","seed":6766933511851476621842569539761779459863556541949811033442999609968154574532,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_INFO @ 2523.424464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"1.chip_sw_sleep_pin_retention.108074720017220982366085767198134932880790962789984073854103926838795672693461","seed":108074720017220982366085767198134932880790962789984073854103926838795672693461,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log","log_context":["UVM_INFO @ 3141.699502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pinmux_sleep_retention","qual_name":"1.chip_sw_spi_device_pinmux_sleep_retention.54101920473176355939348941828338528219072742587109373990827018021452117996522","seed":54101920473176355939348941828338528219072742587109373990827018021452117996522,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log","log_context":["UVM_INFO @ 3103.505290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.17065174517013560323502918724575637151065590782261868373385255658920927944010","seed":17065174517013560323502918724575637151065590782261868373385255658920927944010,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 6094.609596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.18152854456281008514143994308973436815548088299719320924032224987445109572040","seed":18152854456281008514143994308973436815548088299719320924032224987445109572040,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 3111.984708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_normal_sleep_por_reset.97565712248962659987173098804158800106246955292448420442232668831124792181082","seed":97565712248962659987173098804158800106246955292448420442232668831124792181082,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 4244.884747 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.70318548967939039164090820496796633619090271532538552913034842095486263707434","seed":70318548967939039164090820496796633619090271532538552913034842095486263707434,"line":402,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_INFO @ 7201.788486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"1.chip_sw_sleep_sram_ret_contents_no_scramble.83716826594634996057141520314441697208501813735000273066452079578129275547316","seed":83716826594634996057141520314441697208501813735000273066452079578129275547316,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 3062.025662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"1.chip_sw_sleep_sram_ret_contents_scramble.62550737481157416656653180629777855056890900489641372236449312045106552234285","seed":62550737481157416656653180629777855056890900489641372236449312045106552234285,"line":380,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 3029.491386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.82295353188131983524214142010247747871506614658162744358668055020940689351204","seed":82295353188131983524214142010247747871506614658162744358668055020940689351204,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 3157.718724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"1.chip_sw_clkmgr_sleep_frequency.37068062959772421137430889874987246136369059871853462196683465466018743845654","seed":37068062959772421137430889874987246136369059871853462196683465466018743845654,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 4660.546556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.71052438136044428429503348178135360063729430727477977391437652251139045141477","seed":71052438136044428429503348178135360063729430727477977391437652251139045141477,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 3238.043276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"1.chip_sw_pwrmgr_lowpower_cancel.53216246996215852246559524769780475290772500467979490665133039160135437670253","seed":53216246996215852246559524769780475290772500467979490665133039160135437670253,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 2824.797224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_wake_ups.40120359575027406282470601780286904087523431346621724183839177442369150651561","seed":40120359575027406282470601780286904087523431346621724183839177442369150651561,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 3188.480616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.14260584114646888774943099860163712432256358774652894136029385833345651997226","seed":14260584114646888774943099860163712432256358774652894136029385833345651997226,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2889.657318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.43268877701023892890993106957163144120144122026781452125056509934477095604274","seed":43268877701023892890993106957163144120144122026781452125056509934477095604274,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_INFO @ 3266.794340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"2.chip_sw_sleep_pin_retention.65917935859515524708729275473724355851824916080895141078545021714169668842913","seed":65917935859515524708729275473724355851824916080895141078545021714169668842913,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/run.log","log_context":["UVM_INFO @ 3384.247182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pinmux_sleep_retention","qual_name":"2.chip_sw_spi_device_pinmux_sleep_retention.13181261664674412585201216736937781880118071492705776173701177043339294230105","seed":13181261664674412585201216736937781880118071492705776173701177043339294230105,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log","log_context":["UVM_INFO @ 2355.823166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.89462889922569805803270869949902505147855521513671905150969492501656896697836","seed":89462889922569805803270869949902505147855521513671905150969492501656896697836,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 8361.615456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.19001464451494237961373631284102595926422594184914779022792290499482010006997","seed":19001464451494237961373631284102595926422594184914779022792290499482010006997,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 3726.651184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_normal_sleep_por_reset.43541224102573351349798847408559338831704087385820741065303525892958116691259","seed":43541224102573351349798847408559338831704087385820741065303525892958116691259,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 5210.286878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.16452861311275298949692290383232824081719024506369933295525403051622374775099","seed":16452861311275298949692290383232824081719024506369933295525403051622374775099,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_INFO @ 3439.834224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.63477402245350138757363734397007902687541745911403173027054427183700432315842","seed":63477402245350138757363734397007902687541745911403173027054427183700432315842,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 3091.283432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"2.chip_sw_sleep_sram_ret_contents_no_scramble.14412927048437713216211878463754064393104417038209378818488134128647247741495","seed":14412927048437713216211878463754064393104417038209378818488134128647247741495,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 2961.227562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"2.chip_sw_sleep_sram_ret_contents_scramble.55099702658303600410849108205114718783835424282714996269049288139441825529083","seed":55099702658303600410849108205114718783835424282714996269049288139441825529083,"line":380,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 3026.223378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.11640076660095196320968078143610375951370624109681203831689694149999458875941","seed":11640076660095196320968078143610375951370624109681203831689694149999458875941,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 2818.185024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"2.chip_sw_clkmgr_sleep_frequency.90867771773562283260478135554929839459200146744169888296503747906784308428998","seed":90867771773562283260478135554929839459200146744169888296503747906784308428998,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 4775.043338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.98945267506315598386343701626793706327496456582812341629832710653515176777470","seed":98945267506315598386343701626793706327496456582812341629832710653515176777470,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2571.918414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"2.chip_sw_pwrmgr_lowpower_cancel.88658014764979436978448979523097396533774239492379764418530922890810108359636","seed":88658014764979436978448979523097396533774239492379764418530922890810108359636,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 3142.661808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_wake_ups.27389833566856169254145410170056152000199165419961269462487119716495414578141","seed":27389833566856169254145410170056152000199165419961269462487119716495414578141,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 3027.178330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.55625308125416629163926912060722582815131614618439140649670704298517248836053","seed":55625308125416629163926912060722582815131614618439140649670704298517248836053,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2915.550048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.13454029869665316468791807131227259314060354759862072807460895960648680886","seed":13454029869665316468791807131227259314060354759862072807460895960648680886,"line":386,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3792.510824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"0.chip_sw_uart_tx_rx_bootstrap.31478921923820500298460193222503991301690150417333702012609847172954033312300","seed":31478921923820500298460193222503991301690150417333702012609847172954033312300,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"0.chip_sw_exit_test_unlocked_bootstrap.73066467285075062058694142367877565237812492992461648380672899917527565043632","seed":73066467285075062058694142367877565237812492992461648380672899917527565043632,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"0.chip_sw_lc_walkthrough_testunlocks.57079904310601295910793864682401571935643703254318476470063414846181052102150","seed":57079904310601295910793864682401571935643703254318476470063414846181052102150,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"0.chip_sw_rv_timer_systick_test.11951911776642959487102339954119906385842459111205603102686595604741392351090","seed":11951911776642959487102339954119906385842459111205603102686595604741392351090,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.12961538285235191680390116900030511006863094867436198078172780541775302841838","seed":12961538285235191680390116900030511006863094867436198078172780541775302841838,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.32147795615281894768190524800781094621942650479170795208015429358015129308542","seed":32147795615281894768190524800781094621942650479170795208015429358015129308542,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":[]},{"name":"chip_sw_keymgr_dpe_sideload_otbn","qual_name":"0.chip_sw_keymgr_dpe_sideload_otbn.74408721035422129451515981764725282064398879815747124228739873483980262920826","seed":74408721035422129451515981764725282064398879815747124228739873483980262920826,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_dpe_sideload_otbn/latest/run.log","log_context":[]},{"name":"chip_sw_coremark","qual_name":"0.chip_sw_coremark.25327317597229247842613777676407382760958487515059231376851998733431403796330","seed":25327317597229247842613777676407382760958487515059231376851998733431403796330,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log","log_context":[]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"0.chip_sw_rv_core_ibex_icache_invalidate.22700997242713493309148582176463954523665212111729113613406321519939673512164","seed":22700997242713493309148582176463954523665212111729113613406321519939673512164,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":[]},{"name":"ate_bootstrap_one_frame","qual_name":"0.ate_bootstrap_one_frame.11484900678268500451271280758626862205164533878646397496359727361139289001620","seed":11484900678268500451271280758626862205164533878646397496359727361139289001620,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_one_frame/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"0.ate_bootstrap_disjoint.112721198131176803638491614143948592137521928610737463529539207877170311823710","seed":112721198131176803638491614143948592137521928610737463529539207877170311823710,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"1.chip_sw_uart_tx_rx_bootstrap.38207024602945306806990047353860108815120908729375814992322430147215490081410","seed":38207024602945306806990047353860108815120908729375814992322430147215490081410,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"1.chip_sw_exit_test_unlocked_bootstrap.46651296443760277833390975048583209173744478871044721213089289540039036150337","seed":46651296443760277833390975048583209173744478871044721213089289540039036150337,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.14226185159959337522930803616254685022294766669980560216022773267989571219668","seed":14226185159959337522930803616254685022294766669980560216022773267989571219668,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"1.chip_sw_rv_timer_systick_test.5645789592615276923993401818569632086463562513296833877894118315195140747679","seed":5645789592615276923993401818569632086463562513296833877894118315195140747679,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.36369070460110201507549063726146726819218184519777755419332443275739570593695","seed":36369070460110201507549063726146726819218184519777755419332443275739570593695,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_keymgr_dpe_sideload_otbn","qual_name":"1.chip_sw_keymgr_dpe_sideload_otbn.89897401763437980745027658831155330979361344621060541347754851031823160862130","seed":89897401763437980745027658831155330979361344621060541347754851031823160862130,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_dpe_sideload_otbn/latest/run.log","log_context":[]},{"name":"chip_tl_errors","qual_name":"1.chip_tl_errors.4162004145393176576344125661770973523294711121928255600141844469116474970843","seed":4162004145393176576344125661770973523294711121928255600141844469116474970843,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log","log_context":[]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"1.chip_sw_rv_core_ibex_icache_invalidate.97317811398512153110578775997443756022737188467149406810557779336249726332889","seed":97317811398512153110578775997443756022737188467149406810557779336249726332889,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":[]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"1.chip_sw_csrng_edn_concurrency_reduced_freq.104656704671159111699909066211074499981095673744862098566391170182439941742436","seed":104656704671159111699909066211074499981095673744862098566391170182439941742436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":[]},{"name":"ate_bootstrap_one_frame","qual_name":"1.ate_bootstrap_one_frame.7049230325950545554885746462134226147354439073717354491366893423504698503960","seed":7049230325950545554885746462134226147354439073717354491366893423504698503960,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_one_frame/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"1.ate_bootstrap_disjoint.99973666493484310056534675442703352533263067552767342246887616039118775665025","seed":99973666493484310056534675442703352533263067552767342246887616039118775665025,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_sw_uart_tx_rx_bootstrap","qual_name":"2.chip_sw_uart_tx_rx_bootstrap.104282338971105775796887733326642694517336859279815071004171452869040104307394","seed":104282338971105775796887733326642694517336859279815071004171452869040104307394,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_exit_test_unlocked_bootstrap","qual_name":"2.chip_sw_exit_test_unlocked_bootstrap.112454354617400133008629071205040284221392095333966196239756367599138789488422","seed":112454354617400133008629071205040284221392095333966196239756367599138789488422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_exit_test_unlocked_bootstrap/latest/run.log","log_context":[]},{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"2.chip_sw_lc_walkthrough_testunlocks.59138345274072192580682593822684266408803483527456479939117666093127957653698","seed":59138345274072192580682593822684266408803483527456479939117666093127957653698,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":[]},{"name":"chip_sw_rv_timer_systick_test","qual_name":"2.chip_sw_rv_timer_systick_test.111611896166008887295644741977033882876059301307823097385432420486489110527836","seed":111611896166008887295644741977033882876059301307823097385432420486489110527836,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_timer_systick_test/latest/run.log","log_context":[]},{"name":"chip_sw_adc_ctrl_sleep_debug_cable_wakeup","qual_name":"2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.22792745819038448173233672960181777820411347050530017911775262986338333512629","seed":22792745819038448173233672960181777820411347050530017911775262986338333512629,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log","log_context":[]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.75504810167919424758133454751998906418740146689575378629190034018760041457510","seed":75504810167919424758133454751998906418740146689575378629190034018760041457510,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":[]},{"name":"chip_sw_keymgr_dpe_sideload_otbn","qual_name":"2.chip_sw_keymgr_dpe_sideload_otbn.22569783873480179753463852637265375883966849056401401239809416463392982895356","seed":22569783873480179753463852637265375883966849056401401239809416463392982895356,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_dpe_sideload_otbn/latest/run.log","log_context":[]},{"name":"chip_sw_rv_core_ibex_icache_invalidate","qual_name":"2.chip_sw_rv_core_ibex_icache_invalidate.89278238649684779036892542468683109857036207383025788428805635428567131278999","seed":89278238649684779036892542468683109857036207383025788428805635428567131278999,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_icache_invalidate/latest/run.log","log_context":[]},{"name":"chip_sw_csrng_edn_concurrency_reduced_freq","qual_name":"2.chip_sw_csrng_edn_concurrency_reduced_freq.63589243107975649055079908270764135322943642483811417932179263535194313094422","seed":63589243107975649055079908270764135322943642483811417932179263535194313094422,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log","log_context":[]},{"name":"ate_bootstrap_one_frame","qual_name":"2.ate_bootstrap_one_frame.104382236746499237968116880891692088454370139775061053897111261852664662748799","seed":104382236746499237968116880891692088454370139775061053897111261852664662748799,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_one_frame/latest/run.log","log_context":[]},{"name":"ate_bootstrap_disjoint","qual_name":"2.ate_bootstrap_disjoint.85779838961053654927190865292712332495277457217684717845814401643915009566663","seed":85779838961053654927190865292712332495277457217684717845814401643915009566663,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_disjoint/latest/run.log","log_context":[]},{"name":"chip_tl_errors","qual_name":"7.chip_tl_errors.105267308060796923898944954239760807118781995493420172639700533976747834700761","seed":105267308060796923898944954239760807118781995493420172639700533976747834700761,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log","log_context":[]}],"UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.45432675142232644339237005753291036855269993394266536610693207266300333122010","seed":45432675142232644339237005753291036855269993394266536610693207266300333122010,"line":392,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["host_rsp:\n","-------------------------------------------------------------------------\n","Name                               Type              Size  Value         \n","-------------------------------------------------------------------------\n"]}],"UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!":[{"name":"chip_sw_rram_rma_unlocked","qual_name":"0.chip_sw_rram_rma_unlocked.49846981403292126334441709693291224578703451115907236910389000153633793379677","seed":49846981403292126334441709693291224578703451115907236910389000153633793379677,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rram_rma_unlocked","qual_name":"1.chip_sw_rram_rma_unlocked.35624676412202226218509953977263847325051529369094507535561495524517784599122","seed":35624676412202226218509953977263847325051529369094507535561495524517784599122,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rram_rma_unlocked","qual_name":"2.chip_sw_rram_rma_unlocked.35519503493172337884851886388571284983678567682902934375510096279715482579023","seed":35519503493172337884851886388571284983678567682902934375510096279715482579023,"line":336,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.63116256253042407616425554242766041032897273120823323828256116362372015542118","seed":63116256253042407616425554242766041032897273120823323828256116362372015542118,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6118.023816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.36572241479230647931205793590459009556458565452752368996380238681713021179251","seed":36572241479230647931205793590459009556458565452752368996380238681713021179251,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6450.514108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.10239782560973931026275785410840970003891411670138233846218617432560675488332","seed":10239782560973931026275785410840970003891411670138233846218617432560675488332,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6509.601445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected:":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.25973505560518439304785427087171780684519463934864708559963121335634411169552","seed":25973505560518439304785427087171780684519463934864708559963121335634411169552,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["\talert_enable:1\n","\talert_raised:0\n","UVM_INFO @ 3685.363058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.16564345031386679768732222964667346879485507345781028224749291040645385560938","seed":16564345031386679768732222964667346879485507345781028224749291040645385560938,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.37050536309570200066379647292991712254511661455668032701714170456188208548338","seed":37050536309570200066379647292991712254511661455668032701714170456188208548338,"line":396,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.82025646046831157383451303145643165204563570612079142411679949007228421662729","seed":82025646046831157383451303145643165204563570612079142411679949007228421662729,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.18052318082614472562595350991274831294813927753583079203148877246419941071318","seed":18052318082614472562595350991274831294813927753583079203148877246419941071318,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.26187675189068325928327523872562977992836129336669323999924404349653148300196","seed":26187675189068325928327523872562977992836129336669323999924404349653148300196,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.14588028750717835858574534596482146696370333036484913931063756940971238309270","seed":14588028750717835858574534596482146696370333036484913931063756940971238309270,"line":396,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.41656413344772124327488710354345801161074175442062255394430882444149905131880","seed":41656413344772124327488710354345801161074175442062255394430882444149905131880,"line":396,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl":[{"name":"chip_sw_lc_ctrl_raw_to_scrap","qual_name":"0.chip_sw_lc_ctrl_raw_to_scrap.67031620453977679757601593335924796417965765744742403675059184789257790144513","seed":67031620453977679757601593335924796417965765744742403675059184789257790144513,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_raw_to_scrap/latest/run.log","log_context":["UVM_INFO @ 9099.122727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.30802864170205590488069064634685490384684680417605397519438671315123144017489","seed":30802864170205590488069064634685490384684680417605397519438671315123144017489,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 17990.884314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.59327604979051694768213059850914971622223057049619492833488095947527972299196","seed":59327604979051694768213059850914971622223057049619492833488095947527972299196,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 19198.246576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.79206095085149638770606057151020027617848290202343989562763628854698330673857","seed":79206095085149638770606057151020027617848290202343989562763628854698330673857,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 11305.914142 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.71476056510419683887961635326475408697708624716868872364246502185756402756000","seed":71476056510419683887961635326475408697708624716868872364246502185756402756000,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 20463.394904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.98264426240355935272404334308036962023624609359866995381103532533573577978902","seed":98264426240355935272404334308036962023624609359866995381103532533573577978902,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 20486.322352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.83345367609938719645091244591815384989430858362054592489979143658913256319098","seed":83345367609938719645091244591815384989430858362054592489979143658913256319098,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 14980.635442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.52037192938200052862317345964535585557548903340729812038917242477447601340929","seed":52037192938200052862317345964535585557548903340729812038917242477447601340929,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 17354.691986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.13474084203970704787708413749772425755777499546655558830526340648701479129021","seed":13474084203970704787708413749772425755777499546655558830526340648701479129021,"line":432,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 20034.414350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.43028616125950113341264834592343479349261880859689691321186186899770638534904","seed":43028616125950113341264834592343479349261880859689691321186186899770638534904,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 12647.241896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.5938540571323161718304079079531122876655957070021427296100524179364815513146","seed":5938540571323161718304079079531122876655957070021427296100524179364815513146,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2441.308736 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2441.308736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.35118835192619677066333263542234809681535792314984263255685076561719474199333","seed":35118835192619677066333263542234809681535792314984263255685076561719474199333,"line":416,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 10861.246712 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 10861.246712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.18326455565316858682689400991659903501883491727978983956449802425427146547293","seed":18326455565316858682689400991659903501883491727978983956449802425427146547293,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2769.365940 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2769.365940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.20064952813357878054965618992363273989126456574169672711330190058625348042751","seed":20064952813357878054965618992363273989126456574169672711330190058625348042751,"line":376,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2734.428220 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2734.428220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.86316072749437289302238742532917033513897225735419508916149885381389859408682","seed":86316072749437289302238742532917033513897225735419508916149885381389859408682,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2855.249702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.97166008452362800709756131970565447655562041831458887240147339610502769420377","seed":97166008452362800709756131970565447655562041831458887240147339610502769420377,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2475.517680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.81474636164224064331803685454521272687363641508533214449543040197448848766689","seed":81474636164224064331803685454521272687363641508533214449543040197448848766689,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2488.529606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.40991954054813405226859870268989423891107334897137185695554867323839782547578","seed":40991954054813405226859870268989423891107334897137185695554867323839782547578,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2116.608055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.115112831148548112750253886871531825297666277134207424548091864395336256560071","seed":115112831148548112750253886871531825297666277134207424548091864395336256560071,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3008.767131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.78739858251875817577858404906966027181121002372541841521408950511010713039937","seed":78739858251875817577858404906966027181121002372541841521408950511010713039937,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2328.182634 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.66590967205237472241955770275848229560044222562843982044470227840731229180533","seed":66590967205237472241955770275848229560044222562843982044470227840731229180533,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2632.136658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.107922608418323362065686644833388070980202609378262681617618999117819278349829","seed":107922608418323362065686644833388070980202609378262681617618999117819278349829,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2442.293275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.708315309776978441880465967471368579782521041583812336512889063228407665826","seed":708315309776978441880465967471368579782521041583812336512889063228407665826,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3073.779320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.63738208792079370468558809380560240760885890951432381827201371303510901696427","seed":63738208792079370468558809380560240760885890951432381827201371303510901696427,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2939.143726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.43708349425808154576405525102192201285422441550514530974012886259696309430727","seed":43708349425808154576405525102192201285422441550514530974012886259696309430727,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3089.930622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.80146589980566630236218127590932076380437829454568960699398738445833065950171","seed":80146589980566630236218127590932076380437829454568960699398738445833065950171,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2294.042984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.12916366543791353198546998249133498457989195371011538563798426239081483770273","seed":12916366543791353198546998249133498457989195371011538563798426239081483770273,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2850.701440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.113368630475006009309285770553354505125774147381298934313642131504435257835379","seed":113368630475006009309285770553354505125774147381298934313642131504435257835379,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2622.612896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.67222826546056686949289237169907583860264108893699970246446668626003631187023","seed":67222826546056686949289237169907583860264108893699970246446668626003631187023,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2361.174772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.7204047137666136307808497821014615734311209177494126149597390987188295357859","seed":7204047137666136307808497821014615734311209177494126149597390987188295357859,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2618.488860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.79912679023461205319407661218489117954454447463459308787616388744476886844358","seed":79912679023461205319407661218489117954454447463459308787616388744476886844358,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2222.027690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.49868234824367555207357001072904883058745377602073977127834278485748917344455","seed":49868234824367555207357001072904883058745377602073977127834278485748917344455,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3237.519814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.109670014029275090554274670996809203629829021631644849903499337604943035773370","seed":109670014029275090554274670996809203629829021631644849903499337604943035773370,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2629.526190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.82970752537894178952323764128560171638400121735616260492486015776640251833208","seed":82970752537894178952323764128560171638400121735616260492486015776640251833208,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2961.051410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.8844838583501241051058486588882622283369549706784373354953927269321268538005","seed":8844838583501241051058486588882622283369549706784373354953927269321268538005,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2025.978159 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.78774619516621022393701571172903366199441993382939981570226668934061905614086","seed":78774619516621022393701571172903366199441993382939981570226668934061905614086,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2399.965500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.84700414922937385408212066713094152023368018849127972359397761413613278333469","seed":84700414922937385408212066713094152023368018849127972359397761413613278333469,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2397.209202 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.39983811286136741485525267084763052228865602674555360412570621798809278065551","seed":39983811286136741485525267084763052228865602674555360412570621798809278065551,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2478.140141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.62417789835332814372836228466516161470917451752721309680548954780668991529086","seed":62417789835332814372836228466516161470917451752721309680548954780668991529086,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2750.984585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.93689299228483392873133154605908140557326445227240648482995679369251653005081","seed":93689299228483392873133154605908140557326445227240648482995679369251653005081,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3192.439540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.52657609265506211674994497409448039147320426787168862953855658945282541174355","seed":52657609265506211674994497409448039147320426787168862953855658945282541174355,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2995.210125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.60833934190647466517687479087121299499608354889960839900001312888579707838039","seed":60833934190647466517687479087121299499608354889960839900001312888579707838039,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2305.577695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.28114716988970526226980683273535411315540180950216981649299812550340641540383","seed":28114716988970526226980683273535411315540180950216981649299812550340641540383,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2521.754360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.12575206034606352877752497379893127476189173080818237886421089125038119921587","seed":12575206034606352877752497379893127476189173080818237886421089125038119921587,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2634.239610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.101462381986951206857666673057288071588343250453951187241340794373090203320117","seed":101462381986951206857666673057288071588343250453951187241340794373090203320117,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3012.664912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.53591696197866438636859239868741612266896130906291619644216985965060267872124","seed":53591696197866438636859239868741612266896130906291619644216985965060267872124,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2947.014032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.55517036800422226001557421211402263239902882732310820437444410345852784344003","seed":55517036800422226001557421211402263239902882732310820437444410345852784344003,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2490.517356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.68901948989177934714544527573873695308476066248112003086865824304841859089729","seed":68901948989177934714544527573873695308476066248112003086865824304841859089729,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2386.273740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.113298498077161584653637400506615059331473394416478712056001255871020933932438","seed":113298498077161584653637400506615059331473394416478712056001255871020933932438,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3071.585249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.115532886749916809147049976794700795840150832280910965076282640770457758388692","seed":115532886749916809147049976794700795840150832280910965076282640770457758388692,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3303.861994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.68003936615990288209912435724843108253498406529728333465599436533577791749184","seed":68003936615990288209912435724843108253498406529728333465599436533577791749184,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2405.171552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.25124305483723839810646351195884699669521267006352453380909504848042385630301","seed":25124305483723839810646351195884699669521267006352453380909504848042385630301,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2628.243150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.39249980226580413453293203865946202041086792429947576955618184695702121390923","seed":39249980226580413453293203865946202041086792429947576955618184695702121390923,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2592.734104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.96124784074885529765736211512720414627785620514884663505057225177056828185267","seed":96124784074885529765736211512720414627785620514884663505057225177056828185267,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2687.574843 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.65765360653894556212814895987887926450968732124382280559103256374431973921321","seed":65765360653894556212814895987887926450968732124382280559103256374431973921321,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2615.516635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.17616316657991770635222841201089973808506999893227773533265929043743752646630","seed":17616316657991770635222841201089973808506999893227773533265929043743752646630,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2748.877176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.99317909146373833601079781381439249136960976370059175778042829339747052293523","seed":99317909146373833601079781381439249136960976370059175778042829339747052293523,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2675.549146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.33976457335680832479039976198574234255538299335468098908087395304854724800432","seed":33976457335680832479039976198574234255538299335468098908087395304854724800432,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2492.269375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.35239152538464765444540957178687299821124522561395134483069430810944926322771","seed":35239152538464765444540957178687299821124522561395134483069430810944926322771,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2413.841485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.22371232683164399787873268937444309059364741630547190062064383896898969222934","seed":22371232683164399787873268937444309059364741630547190062064383896898969222934,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3017.777449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.15994741451804027694867444153496893651103755896566750609706274600099955008168","seed":15994741451804027694867444153496893651103755896566750609706274600099955008168,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2263.177736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.54565225089824029917676531866905802423354231628320261719819762365474436907200","seed":54565225089824029917676531866905802423354231628320261719819762365474436907200,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2561.958017 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.29807583279060575564779619605840206026283988369312101137240428728753082946096","seed":29807583279060575564779619605840206026283988369312101137240428728753082946096,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2806.374120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.57734799489514853832184153098089366186875833563147764554936033015655823944858","seed":57734799489514853832184153098089366186875833563147764554936033015655823944858,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2948.332410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.42328036999207903180577027807630779036808882473840439272746888780909396975231","seed":42328036999207903180577027807630779036808882473840439272746888780909396975231,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2695.201901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.42713058914668076402721591616981968023630538857659731786452491450036029242864","seed":42713058914668076402721591616981968023630538857659731786452491450036029242864,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2193.673580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.97702408136081172622659945987797548810135793522062184038849186303419330055991","seed":97702408136081172622659945987797548810135793522062184038849186303419330055991,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2741.196018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.112626509488067717822614566638939329789193456523140435024509997837111792133167","seed":112626509488067717822614566638939329789193456523140435024509997837111792133167,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2516.532915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.70910993045637770481853340184236431799432977034398893628585964880697668885930","seed":70910993045637770481853340184236431799432977034398893628585964880697668885930,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2924.174212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.112818313211558938291139717262722413875598281559918502222615463770682050566659","seed":112818313211558938291139717262722413875598281559918502222615463770682050566659,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2818.751480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.106733450636034551566980066325309024292193994655988240016727248050937360277666","seed":106733450636034551566980066325309024292193994655988240016727248050937360277666,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2984.998152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.8932858050748802626292942611339881905036634230365701770156412106547485872132","seed":8932858050748802626292942611339881905036634230365701770156412106547485872132,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3219.701176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.99790582648276452790728456273686602139041165570757333263041876023002239362750","seed":99790582648276452790728456273686602139041165570757333263041876023002239362750,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2999.155367 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.103495777857171813981741879286702057015078175350972015291609185913080335628346","seed":103495777857171813981741879286702057015078175350972015291609185913080335628346,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2924.227951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.68074272502810932949185955814917719571899522717466025035356932895583288945157","seed":68074272502810932949185955814917719571899522717466025035356932895583288945157,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2455.691269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.107098329518120143312436990508217509489357776180191188440677949684914575175723","seed":107098329518120143312436990508217509489357776180191188440677949684914575175723,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2793.618995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.48261835494183453929681683610738716715986872236165745660488279141899240969723","seed":48261835494183453929681683610738716715986872236165745660488279141899240969723,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2827.996009 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.104006909778313061261779349194451658948370252595644892553857009020841703287615","seed":104006909778313061261779349194451658948370252595644892553857009020841703287615,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2743.269853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.63307550260843357489327169734913529291671023748306479623248059006703925285989","seed":63307550260843357489327169734913529291671023748306479623248059006703925285989,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2645.399758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.9558195701640141201164722937200478313651707863813852870095779030899498540524","seed":9558195701640141201164722937200478313651707863813852870095779030899498540524,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2412.201806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.107129341794938888456924382714211627542992290734289877637492910621490143565143","seed":107129341794938888456924382714211627542992290734289877637492910621490143565143,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2453.613676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.47733918427680265341712842687898757825273525287009456011389907533814202329046","seed":47733918427680265341712842687898757825273525287009456011389907533814202329046,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3051.480817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.48644739110116378536364559385166638359077713383772264251634230405846503858496","seed":48644739110116378536364559385166638359077713383772264251634230405846503858496,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2769.298866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663691935500069492267515543081393151486323300722363264634137100010241944380","seed":3663691935500069492267515543081393151486323300722363264634137100010241944380,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2636.980214 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.93871233107863076578943403642530929896008948990632790405235310430478856808801","seed":93871233107863076578943403642530929896008948990632790405235310430478856808801,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3117.734722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.78926423862378031189673408581764349867350185647681150056532055968394374946751","seed":78926423862378031189673408581764349867350185647681150056532055968394374946751,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2109.980485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.36513944932085673139596769412523142018864727884422000366555955130996775663931","seed":36513944932085673139596769412523142018864727884422000366555955130996775663931,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2173.086645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.47249693048104455405138165759415341115818170766186290646063211369348787599195","seed":47249693048104455405138165759415341115818170766186290646063211369348787599195,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2802.877624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.112736469101913484294395807428344501456030860129954102207834732007369300361396","seed":112736469101913484294395807428344501456030860129954102207834732007369300361396,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2731.255851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.87576047518094365454684118993364059591736848903442252951524819943576432190009","seed":87576047518094365454684118993364059591736848903442252951524819943576432190009,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2824.567230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.57532456429972590187533732390462901520860589623579673665328510005254030073614","seed":57532456429972590187533732390462901520860589623579673665328510005254030073614,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2663.848160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.25621928053206857894578241519521838161436885708402903479262041263052990310000","seed":25621928053206857894578241519521838161436885708402903479262041263052990310000,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2589.650656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.114152870584931885578176073420822639060208998587382925940611892091991209507981","seed":114152870584931885578176073420822639060208998587382925940611892091991209507981,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2832.091212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.68879279416495222236136184103830654453168576979575878594500878481023398662881","seed":68879279416495222236136184103830654453168576979575878594500878481023398662881,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3224.163648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.86549003483655728165952513371489588949226500168375948329722710158560311412160","seed":86549003483655728165952513371489588949226500168375948329722710158560311412160,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2133.927610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.78690671924630444086002172511764778168679415451699625951933487196915695074843","seed":78690671924630444086002172511764778168679415451699625951933487196915695074843,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2833.123330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.115723712410801914324513003530276045423503875308626009452474951566590990450793","seed":115723712410801914324513003530276045423503875308626009452474951566590990450793,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2389.001688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.34629084283039268105276679637881949373740542156452720892186669318175443171630","seed":34629084283039268105276679637881949373740542156452720892186669318175443171630,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2562.745645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.43959759145730004446426194867825729575760822602829673960746096653815550628237","seed":43959759145730004446426194867825729575760822602829673960746096653815550628237,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2280.511237 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.71955223992441937097861138121074798129175230497819229422127764079462360839809","seed":71955223992441937097861138121074798129175230497819229422127764079462360839809,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2783.416964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.26619205074892683893929593150799811661035600062256677830860674651616718242894","seed":26619205074892683893929593150799811661035600062256677830860674651616718242894,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3106.287018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.49697096538837663399318041284156719668407650515688598023979305830499293681760","seed":49697096538837663399318041284156719668407650515688598023979305830499293681760,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3112.971280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.84717000271356714561405149196694139209003250234891495977063699949457397261679","seed":84717000271356714561405149196694139209003250234891495977063699949457397261679,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2666.970011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.26815246008358205384466447149760650737816764545456490174047714803984529775526","seed":26815246008358205384466447149760650737816764545456490174047714803984529775526,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2359.375426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.54049015554992523099425345851660993282625767491882161545096068835813295038603","seed":54049015554992523099425345851660993282625767491882161545096068835813295038603,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2392.630428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.2775390456334229697551975274002280215632568224574354594719571462932602574870","seed":2775390456334229697551975274002280215632568224574354594719571462932602574870,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 2747.720178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.21488395368927284638372441726038930858239532917317703832057938829106950177082","seed":21488395368927284638372441726038930858239532917317703832057938829106950177082,"line":481,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 2638.767616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_reverse_ping_in_deep_sleep","qual_name":"1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.13770921437459870993681368786736420493234237416952229207707055800748376148696","seed":13770921437459870993681368786736420493234237416952229207707055800748376148696,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log","log_context":["UVM_INFO @ 9659.043880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.53340074632876241707539176934807942557685905449123227857664427714658052231429","seed":53340074632876241707539176934807942557685905449123227857664427714658052231429,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 2726.039442 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"1.chip_sw_alert_handler_entropy.84299587564975748647969933393985899846608400969607036892430193967931710438764","seed":84299587564975748647969933393985899846608400969607036892430193967931710438764,"line":493,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 2926.350090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"2.chip_sw_alert_handler_entropy.84507881003331434145895610773299233435546788320980973888711937682935560416021","seed":84507881003331434145895610773299233435546788320980973888711937682935560416021,"line":493,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 2924.803044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.113067865094451906900952908755071528668524206248404860107388090455875228442918","seed":113067865094451906900952908755071528668524206248404860107388090455875228442918,"line":411,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.8063331464966091321048806453269470626013782741860241715868943037816191050233","seed":8063331464966091321048806453269470626013782741860241715868943037816191050233,"line":415,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"2.chip_sw_hmac_multistream.54009686144710335599712570928063631055516812427364073118221678376292939457202","seed":54009686144710335599712570928063631055516812427364073118221678376292939457202,"line":426,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_tl_errors","qual_name":"0.chip_tl_errors.21009252037528927066872999990729211359444802716416860657316588696990783130659","seed":21009252037528927066872999990729211359444802716416860657316588696990783130659,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33257) { a_addr: 'h10554  a_data: 'h9c6b04eb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1927f  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1769.734066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"1.chip_csr_mem_rw_with_rand_reset.77051950812120436638453880697681959601049262239925078531970040216586963720634","seed":77051950812120436638453880697681959601049262239925078531970040216586963720634,"line":285,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32093) { a_addr: 'h10670  a_data: 'he089cce8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h18a23  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2003.718024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"2.chip_tl_errors.67606217079939764986242414012326769884423057980868473651581180382038876768777","seed":67606217079939764986242414012326769884423057980868473651581180382038876768777,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31661) { a_addr: 'h10578  a_data: 'h7b4fb700  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h192b5  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2432.645232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"3.chip_tl_errors.34765065434680866366224659657927416342984968051036928692053678931320282194188","seed":34765065434680866366224659657927416342984968051036928692053678931320282194188,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32661) { a_addr: 'h104f8  a_data: 'h2c99e933  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2c  a_opcode: 'h4  a_user: 'h1a558  d_param: 'h0  d_source: 'h2c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2041.589474 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.67609306979328870122297282019645636613052692163061702122571852202792628214523","seed":67609306979328870122297282019645636613052692163061702122571852202792628214523,"line":285,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31751) { a_addr: 'h1060c  a_data: 'h7181d682  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1868a  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1908.951225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"4.chip_tl_errors.23494480227717595965991435801289858370322548909280706006700062618179453995505","seed":23494480227717595965991435801289858370322548909280706006700062618179453995505,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32193) { a_addr: 'h10570  a_data: 'h2241e5ee  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1865c  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1842.112330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"4.chip_csr_mem_rw_with_rand_reset.2867159934244867193622755101655679378400931415410467656881747727841363101473","seed":2867159934244867193622755101655679378400931415410467656881747727841363101473,"line":285,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32233) { a_addr: 'h10504  a_data: 'h780ceca8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h19e49  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1958.291960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"5.chip_tl_errors.40092812168326912944263896375060777759013082979959566008202896321163728423438","seed":40092812168326912944263896375060777759013082979959566008202896321163728423438,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33599) { a_addr: 'h1077c  a_data: 'he474c26f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h19509  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2135.330139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"8.chip_tl_errors.62076069368785275050797889590079839486215550985055239425623797590419716626272","seed":62076069368785275050797889590079839486215550985055239425623797590419716626272,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32311) { a_addr: 'h10594  a_data: 'h27952f98  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h28  a_opcode: 'h4  a_user: 'h18a38  d_param: 'h0  d_source: 'h28  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2450.690975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"9.chip_tl_errors.2699191845529934496688731508368680368056263903346032794708108504327716550577","seed":2699191845529934496688731508368680368056263903346032794708108504327716550577,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31803) { a_addr: 'h10600  a_data: 'ha1630ea0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1c  a_opcode: 'h4  a_user: 'h19eb1  d_param: 'h0  d_source: 'h1c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2198.230300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"10.chip_tl_errors.19988932413433364786593400264398349966499823627872115970508284445730980698512","seed":19988932413433364786593400264398349966499823627872115970508284445730980698512,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34189) { a_addr: 'h10594  a_data: 'h61987f20  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h18a4f  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2166.357318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"11.chip_tl_errors.16012105918884370860684978170341160273491541543644046227247949377177924231642","seed":16012105918884370860684978170341160273491541543644046227247949377177924231642,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31853) { a_addr: 'h104a8  a_data: 'hbae133d1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1a942  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2034.712106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"13.chip_tl_errors.101574694688019404419996600386644518422628861661862451134367105610583694559240","seed":101574694688019404419996600386644518422628861661862451134367105610583694559240,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32453) { a_addr: 'h105a8  a_data: 'h1e127797  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1ae39  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2013.888249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"14.chip_tl_errors.20674780585444142245136078060929653369832206714630901228875628860091010255047","seed":20674780585444142245136078060929653369832206714630901228875628860091010255047,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34419) { a_addr: 'h1072c  a_data: 'h7939939b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h19967  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1756.883128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"15.chip_tl_errors.49598757842431115670553624177068248065043350186739223249249063814937548278156","seed":49598757842431115670553624177068248065043350186739223249249063814937548278156,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@31861) { a_addr: 'h10724  a_data: 'hef8fac34  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h18d83  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1985.103762 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"16.chip_tl_errors.42949713765089566806445580450559300080946831546166203224722851225843250293118","seed":42949713765089566806445580450559300080946831546166203224722851225843250293118,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33499) { a_addr: 'h107d8  a_data: 'h748bf551  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h4  a_user: 'h1b1d5  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1930.869992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"18.chip_tl_errors.61368318002726549780368199276511580053933320155534169106209426458817250337678","seed":61368318002726549780368199276511580053933320155534169106209426458817250337678,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@42187) { a_addr: 'h10698  a_data: 'h769670cf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h4  a_user: 'h19e43  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1983.992776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"19.chip_tl_errors.19993798184498132657259881774770241833221932096250450223559758105577843157721","seed":19993798184498132657259881774770241833221932096250450223559758105577843157721,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@40341) { a_addr: 'h10568  a_data: 'h1c70e649  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1b631  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2463.480060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"20.chip_tl_errors.25990696457087669303427686297483329997421635770895199171494289202447271815133","seed":25990696457087669303427686297483329997421635770895199171494289202447271815133,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32167) { a_addr: 'h10568  a_data: 'he60ddf6d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h1b61c  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2119.186925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"21.chip_tl_errors.23376103736805684059997557363523771918242730416584851536802276981657900681649","seed":23376103736805684059997557363523771918242730416584851536802276981657900681649,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@32293) { a_addr: 'h1068c  a_data: 'h591593c7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h1b626  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1887.114000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"22.chip_tl_errors.38689713872264741581227478260946377913362088940509805296368627049670608684190","seed":38689713872264741581227478260946377913362088940509805296368627049670608684190,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34715) { a_addr: 'h10518  a_data: 'hf15481bf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1a2ab  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1566.552455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"23.chip_tl_errors.92362500660971327422167897307239119277660986053545314209883527120112461398058","seed":92362500660971327422167897307239119277660986053545314209883527120112461398058,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33385) { a_addr: 'h105b4  a_data: 'hdc69d065  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h192d8  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1679.944035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"24.chip_tl_errors.113531138850273134971480027911621263338929477529505775136230929457423122397534","seed":113531138850273134971480027911621263338929477529505775136230929457423122397534,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@41197) { a_addr: 'h10458  a_data: 'hcfc9b416  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h4  a_user: 'h18d69  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2026.892388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"25.chip_tl_errors.63725008025724186969688003328208173369806000115919886612560593904266912772360","seed":63725008025724186969688003328208173369806000115919886612560593904266912772360,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33355) { a_addr: 'h10374  a_data: 'h63f71198  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h192e4  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1761.304056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"26.chip_tl_errors.19551024485886369815578371102248577782273841998090704159690757206156793819713","seed":19551024485886369815578371102248577782273841998090704159690757206156793819713,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@38195) { a_addr: 'h104fc  a_data: 'h89eb67ed  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h1a999  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1970.373858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"27.chip_tl_errors.108051955757710631214246455382861035398117410401993946209771146216035605666212","seed":108051955757710631214246455382861035398117410401993946209771146216035605666212,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@33599) { a_addr: 'h10654  a_data: 'h5e4d199f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h19e1c  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 1878.171216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"28.chip_tl_errors.52721090861770911181246619264433906701118669747675806827034962823725758267538","seed":52721090861770911181246619264433906701118669747675806827034962823725758267538,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@35349) { a_addr: 'h10794  a_data: 'h5bf08365  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1811c  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2222.489102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"chip_tl_errors","qual_name":"29.chip_tl_errors.48863162684648440247321002031965509006198158925229067468066548310320081264625","seed":48863162684648440247321002031965509006198158925229067468066548310320081264625,"line":281,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@34029) { a_addr: 'h1051c  a_data: 'hd89590b1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1ae07  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{\"Fetch from CSR\"} .\n","UVM_INFO @ 2206.270799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.":[{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.25305715209753481974458935854550940708605215317360487671705321085369446328772","seed":25305715209753481974458935854550940708605215317360487671705321085369446328772,"line":399,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 7765.692280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"1.chip_sw_clkmgr_reset_frequency.42378926733946191171274521768608764441263108196143095855181708553047702145899","seed":42378926733946191171274521768608764441263108196143095855181708553047702145899,"line":399,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 8623.861724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"2.chip_sw_clkmgr_reset_frequency.93647509347279540472043138394355539351749180652822822793327603455732378587899","seed":93647509347279540472043138394355539351749180652822822793327603455732378587899,"line":399,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 11740.424088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.50963939664217158106112128369122097565522715357464641481715479332485485295762","seed":50963939664217158106112128369122097565522715357464641481715479332485485295762,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3110.367535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.81024094832309757805994307097591096591240322368852760239507904407059633938560","seed":81024094832309757805994307097591096591240322368852760239507904407059633938560,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3724.490990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.72361038912257199517413058308181555373371481640044978193480307666452654975361","seed":72361038912257199517413058308181555373371481640044978193480307666452654975361,"line":406,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3187.138022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!":[{"name":"chip_jtag_mem_access","qual_name":"0.chip_jtag_mem_access.27417654345686052482104361129101401347112685655336681056449661611200922795888","seed":27417654345686052482104361129101401347112685655336681056449661611200922795888,"line":5364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 2675.349560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_mem_access","qual_name":"1.chip_jtag_mem_access.57153334729737306476649534065101190395204540970447098834111247144875147578763","seed":57153334729737306476649534065101190395204540970447098834111247144875147578763,"line":5364,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log","log_context":["UVM_INFO @ 2608.121427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.66829218261630139387984051326083438205654815937889566903332832489381682522812","seed":66829218261630139387984051326083438205654815937889566903332832489381682522812,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.68312019868561034296664874160946178609129250192231706607915401035852489024911","seed":68312019868561034296664874160946178609129250192231706607915401035852489024911,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=194832) is running. Waiting for it to complete on the server (server_pid=194937)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.107244305052244528525944327214217774059522984820210048438430555310505572369036","seed":107244305052244528525944327214217774059522984820210048438430555310505572369036,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=208629) is running. Waiting for it to complete on the server (server_pid=194937)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.31652317906553539520582876737929920681099381991106837033491078155481687152008","seed":31652317906553539520582876737929920681099381991106837033491078155481687152008,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.74639394527202867658011268313538124737567216780367309261321588388588928281536","seed":74639394527202867658011268313538124737567216780367309261321588388588928281536,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1144305) is running. Waiting for it to complete on the server (server_pid=194937)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.3402711061636496157904609292800949026985504918173014756896329833959151822449","seed":3402711061636496157904609292800949026985504918173014756896329833959151822449,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=376475) is running. Waiting for it to complete on the server (server_pid=194937)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected *":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.88486860906616017123237525001546276693062723179878354959966476992423281752055","seed":88486860906616017123237525001546276693062723179878354959966476992423281752055,"line":299,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 4671.360730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.53825767302498187021037755658715523936414374394467946643753710240603256867205","seed":53825767302498187021037755658715523936414374394467946643753710240603256867205,"line":285,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 2103.177992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.100049080044024991943158331278469331670046029876774222090036510939163603284340","seed":100049080044024991943158331278469331670046029876774222090036510939163603284340,"line":285,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 1623.868561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.100242373163093593585708282167689580767975634597922517513219562678620390796039","seed":100242373163093593585708282167689580767975634597922517513219562678620390796039,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 9521.900548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.60906740328042768407490295336332110260998877132569086961965775948125639625298","seed":60906740328042768407490295336332110260998877132569086961965775948125639625298,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 14550.102725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.68155249107406162170122924371545719679347490889342077329726424979095824157654","seed":68155249107406162170122924371545719679347490889342077329726424979095824157654,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 14638.642963 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.32954966473768207626577302819748568008306608571682410083745912714245549783409","seed":32954966473768207626577302819748568008306608571682410083745912714245549783409,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.54717769915003374853161074116937517150310310177781020392707430406338802812184","seed":54717769915003374853161074116937517150310310177781020392707430406338802812184,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.87638225127216021856624976439935721543299581252392424271671072928477614258376","seed":87638225127216021856624976439935721543299581252392424271671072928477614258376,"line":338,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*])":[{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.78735286409741498914704978195191611185290817158332056446461050881946481441401","seed":78735286409741498914704978195191611185290817158332056446461050881946481441401,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["UVM_INFO @ 2159.939000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.73052860963881584150128950851212387479027898504526836934882958226123654926731","seed":73052860963881584150128950851212387479027898504526836934882958226123654926731,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["UVM_INFO @ 2355.214000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.20689271526751278708719939170246607896675494306269959593420112499292045175613","seed":20689271526751278708719939170246607896675494306269959593420112499292045175613,"line":352,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["UVM_INFO @ 1908.147000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl":[{"name":"rom_raw_unlock","qual_name":"0.rom_raw_unlock.78707062661782101778652598648799515560086459273084287960625039844046323009815","seed":78707062661782101778652598648799515560086459273084287960625039844046323009815,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 10795.114639 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.16236532851762197495115857426470336780332806531562423588976202792512307870636","seed":16236532851762197495115857426470336780332806531562423588976202792512307870636,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 8191.578596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.21106912909673806416410586446756701645128559981033720084160283192207212700333","seed":21106912909673806416410586446756701645128559981033720084160283192207212700333,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3086.696970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.19516881764070171105738909989249470812455559306174033510251928732528464040373","seed":19516881764070171105738909989249470812455559306174033510251928732528464040373,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 2875.972799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"1.chip_sw_lc_ctrl_rand_to_scrap.27006315265905696210192774120522848211268821789190509802698099611082107314447","seed":27006315265905696210192774120522848211268821789190509802698099611082107314447,"line":365,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_INFO @ 26175.114952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcTokenError!":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock","qual_name":"1.chip_sw_lc_ctrl_volatile_raw_unlock.86441860922697921491472491265490403066884469990322869936157344547599798637581","seed":86441860922697921491472491265490403066884469990322869936157344547599798637581,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 26219.845362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(buf_intg_err == '0)'":[{"name":"chip_sw_sysrst_ctrl_outputs","qual_name":"1.chip_sw_sysrst_ctrl_outputs.31426626826942932465028514636950194524505279166716667428336357575495059807292","seed":31426626826942932465028514636950194524505279166716667428336357575495059807292,"line":408,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log","log_context":["UVM_ERROR @ 3782.334994 us: (rram_phy_rd.sv:697) [ASSERT FAILED] IntgError\n","UVM_INFO @ 3782.334994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:445)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.88916390356321383612702225648239052189314693030384749804886199470530692340301","seed":88916390356321383612702225648239052189314693030384749804886199470530692340301,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3021.530130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz","qual_name":"2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.68550740454841431887721999783636076813777320315381481874838254928572080260171","seed":68550740454841431887721999783636076813777320315381481874838254928572080260171,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log","log_context":["UVM_INFO @ 25769.138084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.70191623890003309311946735388881502882020566820610435197741069059915282663748","seed":70191623890003309311946735388881502882020566820610435197741069059915282663748,"line":370,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2897.259542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rv_jtag_o == '0)'":[{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.34735464534166278941705783870420325696864190682438617086493266480743989806625","seed":34735464534166278941705783870420325696864190682438617086493266480743989806625,"line":380,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["UVM_ERROR @ 3212.480072 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A\n","UVM_INFO @ 3212.480072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:1004) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration.":[{"name":"rom_volatile_raw_unlock","qual_name":"2.rom_volatile_raw_unlock.73138994457544398933594696314032324942243247968473759841351664731589295847866","seed":73138994457544398933594696314032324942243247968473759841351664731589295847866,"line":363,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_volatile_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 2394.673676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.rram_ctrl_core.region_cfg_regwen_* reset value: *":[{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"2.chip_csr_mem_rw_with_rand_reset.36965546948923364953230639259842548684430316950364284090527197830710692774252","seed":36965546948923364953230639259842548684430316950364284090527197830710692774252,"line":310,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 7769.337224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIor* (num=39)":[{"name":"chip_padctrl_attributes","qual_name":"5.chip_padctrl_attributes.46636084051359852750003981493278715120741856674900375887794109053236275514348","seed":46636084051359852750003981493278715120741856674900375887794109053236275514348,"line":344,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_padctrl_attributes/latest/run.log","log_context":["UVM_INFO @ 1525.641657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"6.chip_sw_all_escalation_resets.108337699326223054517873859785862328763315840949438271918070206370618071280817","seed":108337699326223054517873859785862328763315840949438271918070206370618071280817,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2461.985752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"45.chip_sw_all_escalation_resets.71744198334224831127236300967308781445093602084287110046770903247991811138843","seed":71744198334224831127236300967308781445093602084287110046770903247991811138843,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3089.062192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"58.chip_sw_all_escalation_resets.62275407516572810122208638207591887306388939218290483984021252432593358581530","seed":62275407516572810122208638207591887306388939218290483984021252432593358581530,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2872.889614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_ctrl_transition","qual_name":"7.chip_sw_lc_ctrl_transition.37905164699127351392140376749982017259912145036205120405632419944668220398869","seed":37905164699127351392140376749982017259912145036205120405632419944668220398869,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 26281.051020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"8.chip_sw_lc_ctrl_transition.105998370779422793875366768738771103907674838779028347583266379739016073848109","seed":105998370779422793875366768738771103907674838779028347583266379739016073848109,"line":410,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 38048.045228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"10.chip_sw_lc_ctrl_transition.55514851854463121014659638075633602198444492277592113683206548120905460986756","seed":55514851854463121014659638075633602198444492277592113683206548120905460986756,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 25784.418014 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_ctrl_transition","qual_name":"11.chip_sw_lc_ctrl_transition.65490240606230703988915706625984116841517067137135323289508038201317199035324","seed":65490240606230703988915706625984116841517067137135323289508038201317199035324,"line":368,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_lc_ctrl_transition/latest/run.log","log_context":["UVM_INFO @ 26114.751947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly":[{"name":"chip_sw_all_escalation_resets","qual_name":"47.chip_sw_all_escalation_resets.79875480830984718452331595163314819061229413956865396357468937672317972078276","seed":79875480830984718452331595163314819061229413956865396357468937672317972078276,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2968.851468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.113155359089261295993420905789704417139373494171830647791248460228275011336125","seed":113155359089261295993420905789704417139373494171830647791248460228275011336125,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2939.216504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"93.chip_sw_all_escalation_resets.103689761735444690948687549623177940178135094393514478609725600835376990153310","seed":103689761735444690948687549623177940178135094393514478609725600835376990153310,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/93.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3078.716648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1654,"total":1945,"percent":85.03856041131105}