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[`34ceb5e`](https://github.com/lowrisc/opentitan/tree/34ceb5eb568742f75f01ee23de994ad9f65eae82)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-22T09:08:29Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":7.88,"sim_time":2111.8853369999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":8.99,"sim_time":2452.515051,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":8.67,"sim_time":2389.5184750000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":8.44,"sim_time":2343.26262,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.05,"sim_time":6154.816196000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.8,"sim_time":2037.204278,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":105.68,"sim_time":68130.16724699999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":4.03,"sim_time":2614.777392,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":4.44,"sim_time":2080.151934,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.8,"sim_time":2037.204278,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":4.03,"sim_time":2614.777392,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":490.71,"sim_time":172645.53006,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":567.07,"sim_time":200584.26818900002,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":736.31,"sim_time":240098.731299,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":1535.02,"sim_time":777770.794418,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":8.66,"sim_time":2510.529552,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":5.68,"sim_time":2113.940751,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":12.41,"sim_time":5573.205094,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":9.02,"sim_time":2611.699395,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":930.86,"sim_time":2451479.464086,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":51.48,"sim_time":35304.358992,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":811.01,"sim_time":316066.041694,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.49,"sim_time":2012.5730589999998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.83,"sim_time":2016.676237,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.83,"sim_time":2095.072976,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.83,"sim_time":2095.072976,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.05,"sim_time":6154.816196000001,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.8,"sim_time":2037.204278,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":4.03,"sim_time":2614.777392,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":29.05,"sim_time":10201.438285,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.05,"sim_time":6154.816196000001,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":7.8,"sim_time":2037.204278,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":4.03,"sim_time":2614.777392,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":29.05,"sim_time":10201.438285,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":327,"total":334,"percent":97.90419161676647},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":76.48,"sim_time":42031.374200000006,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":145.66,"sim_time":42411.871747000005,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":145.66,"sim_time":42411.871747000005,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":17.78,"sim_time":5566.863367,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.46,"branch":99.52,"condition_expression":98.01,"toggle":100.0,"fsm":96.15},"assertion":98.95,"functional":86.55},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"9.sysrst_ctrl_combo_detect_with_pre_cond.93816749827055494157055692822463676895558410636221455677151003251237108652655","seed":93816749827055494157055692822463676895558410636221455677151003251237108652655,"line":672,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 13572741935 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 13592741935 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_ERROR @ 13617763070 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4]) \n","UVM_INFO @ 13617763070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"10.sysrst_ctrl_ultra_low_pwr.19213815872363748569421390982816028721409521520932152424066001879582086128701","seed":19213815872363748569421390982816028721409521520932152424066001879582086128701,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2263204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 451493204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i\n","UVM_INFO @ 750808204523 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 750857098177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"29.sysrst_ctrl_combo_detect_with_pre_cond.109890452597600366332379756746685366476961315453333198611182304413754988167671","seed":109890452597600366332379756746685366476961315453333198611182304413754988167671,"line":681,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 35217987768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32\n","UVM_INFO @ 35218017768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1a\n","UVM_INFO @ 36197477768 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2\n","UVM_INFO @ 36212360334 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1d\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"73.sysrst_ctrl_combo_detect_with_pre_cond.107866974772148723049309746019105560324288183262413577434929876141996721846959","seed":107866974772148723049309746019105560324288183262413577434929876141996721846959,"line":689,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 61301776295 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 61301776295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"94.sysrst_ctrl_combo_detect_with_pre_cond.68775085117043917245544803856279586743022834779301798937653087536453901448031","seed":68775085117043917245544803856279586743022834779301798937653087536453901448031,"line":682,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 25378060154 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 25398060154 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 35602666885 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d\n","UVM_INFO @ 35602809741 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x14\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"39.sysrst_ctrl_combo_detect_with_pre_cond.70549130989144228703681665503993648172959384791904242951799176469972759762827","seed":70549130989144228703681665503993648172959384791904242951799176469972759762827,"line":697,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 63888041057 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4 \n","UVM_INFO @ 63888041057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"93.sysrst_ctrl_combo_detect_with_pre_cond.53566656191988263385592430529580151821009600346046128037491492063549879670515","seed":53566656191988263385592430529580151821009600346046128037491492063549879670515,"line":673,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13430623910 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4 \n","UVM_INFO @ 13430623910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":403,"total":410,"percent":98.29268292682927}