{"block":{"name":"sysrst_ctrl","variant":null,"commit":"00981352642fb65ef2b6c47143a0f6bb31fd4a97","commit_short":"0098135","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/00981352642fb65ef2b6c47143a0f6bb31fd4a97","revision_info":"GitHub Revision: [`0098135`](https://github.com/lowrisc/opentitan/tree/00981352642fb65ef2b6c47143a0f6bb31fd4a97)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-29T03:59:48Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":6.95,"sim_time":2108.943553,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":8.53,"sim_time":2483.189304,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":5.54,"sim_time":2247.438813,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":8.15,"sim_time":2299.912667,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":18.72,"sim_time":6049.800955,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.35,"sim_time":2030.1441810000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":49.46,"sim_time":51448.647849,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":2.69,"sim_time":2146.526335,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":6.9,"sim_time":2041.5828289999997,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.35,"sim_time":2030.1441810000003,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":2.69,"sim_time":2146.526335,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":424.24,"sim_time":183760.843793,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":331.71,"sim_time":149127.037479,"passed":94,"total":100,"percent":94.0}},"passed":94,"total":100,"percent":94.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":247.67,"sim_time":158699.475827,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":2112.41,"sim_time":1696610.989781,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":6.89,"sim_time":2509.888508,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":7.26,"sim_time":2232.495171,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":2201.35,"sim_time":980288.3664579999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":9.61,"sim_time":2613.0068739999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":318.69,"sim_time":1603951.152375,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":30.95,"sim_time":37137.133971,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":876.33,"sim_time":2100155.830294,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":6.53,"sim_time":2011.766116,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.2,"sim_time":2019.539366,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.29,"sim_time":2063.780706,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":8.29,"sim_time":2063.780706,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":18.72,"sim_time":6049.800955,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.35,"sim_time":2030.1441810000003,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":2.69,"sim_time":2146.526335,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.98,"sim_time":9276.036789000002,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":18.72,"sim_time":6049.800955,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.35,"sim_time":2030.1441810000003,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":2.69,"sim_time":2146.526335,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.98,"sim_time":9276.036789000002,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":327,"total":334,"percent":97.90419161676647},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":56.4,"sim_time":22010.929678,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":111.12,"sim_time":42469.840522,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":111.12,"sim_time":42469.840522,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":22.94,"sim_time":324828.368479,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0}},"coverage":{"code":{"block":null,"line_statement":99.24,"branch":99.22,"condition_expression":97.88,"toggle":100.0,"fsm":93.59},"assertion":98.58,"functional":84.03},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_stress_all","qual_name":"0.sysrst_ctrl_stress_all.89611053897395236165594449154701288074393309388233260379269398900542264382350","seed":89611053897395236165594449154701288074393309388233260379269398900542264382350,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 4175342598 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i\n","UVM_INFO @ 5590342598 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 5596164649 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq\n","UVM_INFO @ 7595384649 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"7.sysrst_ctrl_combo_detect_with_pre_cond.107435292131126946179939522683804984903958381912575917427097073124730004720724","seed":107435292131126946179939522683804984903958381912575917427097073124730004720724,"line":677,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 24879517231 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 24879517231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*])":[{"name":"sysrst_ctrl_stress_all_with_rand_reset","qual_name":"7.sysrst_ctrl_stress_all_with_rand_reset.44108768471261564729432672656640391644014836795651113285486326776625411193600","seed":44108768471261564729432672656640391644014836795651113285486326776625411193600,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4323952870 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 4323952870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"23.sysrst_ctrl_combo_detect_with_pre_cond.100274293148239450274624936491780352599095215100223639979728421667793408848085","seed":100274293148239450274624936491780352599095215100223639979728421667793408848085,"line":691,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 61659008486 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c\n","UVM_INFO @ 61659133487 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x27\n","UVM_INFO @ 62036412657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 62051412657 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"28.sysrst_ctrl_combo_detect_with_pre_cond.92869893255548071455091879685111867589130617559313967684168764290537491802736","seed":92869893255548071455091879685111867589130617559313967684168764290537491802736,"line":732,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 76242803442 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4 \n","UVM_INFO @ 76242803442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"58.sysrst_ctrl_combo_detect_with_pre_cond.82238396997111224746906163738347208940706161048076390149896450698209266245168","seed":82238396997111224746906163738347208940706161048076390149896450698209266245168,"line":714,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 54150029242 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 54150029242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"65.sysrst_ctrl_combo_detect_with_pre_cond.35152157957072473423670938137331946782009962368021610990983265378460726625977","seed":35152157957072473423670938137331946782009962368021610990983265378460726625977,"line":680,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 27026587401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4]) \n","UVM_INFO @ 27026587401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"67.sysrst_ctrl_combo_detect_with_pre_cond.48602420040868464563443895002854484572732456752512140895197106194568007957549","seed":48602420040868464563443895002854484572732456752512140895197106194568007957549,"line":675,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 12647795054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 12667795054 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 22818448172 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x18\n","UVM_INFO @ 22818479423 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x11\n"]}]}},"passed":402,"total":410,"percent":98.04878048780488}