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(uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.88720664925551756463229302360676657392925058087474346437376592992937018433018","seed":88720664925551756463229302360676657392925058087474346437376592992937018433018,"line":392,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 7596.239388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.31797607669272311721879306393598060382162322952004526161799336428559133189357","seed":31797607669272311721879306393598060382162322952004526161799336428559133189357,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 3608.219688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"0.chip_sw_pwrmgr_normal_sleep_por_reset.43057536461901900320503017198031156361419701062533585999182642041267316982422","seed":43057536461901900320503017198031156361419701062533585999182642041267316982422,"line":388,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 5206.532364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.92330832115706569228042957018592520835089209418988036788523510172621933740531","seed":92330832115706569228042957018592520835089209418988036788523510172621933740531,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_INFO @ 3049.447932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"0.chip_sw_sleep_sram_ret_contents_no_scramble.98521233360268889665062829312635564516370332263169366581035878547438573719179","seed":98521233360268889665062829312635564516370332263169366581035878547438573719179,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 2672.104588 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"0.chip_sw_sleep_sram_ret_contents_scramble.54398946065432314320068870051428821504799785709098733286217249305089131617934","seed":54398946065432314320068870051428821504799785709098733286217249305089131617934,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 2985.983104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.35419911622257773298925900629193523064205752043362447020986410447366312583131","seed":35419911622257773298925900629193523064205752043362447020986410447366312583131,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 2137.378616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"0.chip_sw_clkmgr_sleep_frequency.26222839689909308251593664584216509693566782898465999066102528325659650024219","seed":26222839689909308251593664584216509693566782898465999066102528325659650024219,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 4103.415856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.46378593550938493454244903875980426485520958803486894686590838795110786434425","seed":46378593550938493454244903875980426485520958803486894686590838795110786434425,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2737.000644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"0.chip_sw_pwrmgr_lowpower_cancel.102502918372103772172952957246592142756151537427557961753214276594118179362577","seed":102502918372103772172952957246592142756151537427557961753214276594118179362577,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 3220.828680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"0.chip_sw_pwrmgr_random_sleep_all_wake_ups.98842895864555287162021928619235541284633019625535874432522755037403434406671","seed":98842895864555287162021928619235541284633019625535874432522755037403434406671,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2974.187080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"0.chip_sw_rv_dm_access_after_wakeup.6420790560338049292241505667486082574715753163395854280888147528847891644335","seed":6420790560338049292241505667486082574715753163395854280888147528847891644335,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2378.991184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"0.chip_sw_power_sleep_load.6951314585919056385038722071290678431762899555903520227176477720416914088895","seed":6951314585919056385038722071290678431762899555903520227176477720416914088895,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 4041.732684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"1.chip_sw_sleep_pin_wake.54832611349767483354928678852216070569629818340921333682676933383169324709261","seed":54832611349767483354928678852216070569629818340921333682676933383169324709261,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_INFO @ 2705.709392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"1.chip_sw_sleep_pin_retention.97075498774032672183237014997466135345457304674925447266850196888143238824478","seed":97075498774032672183237014997466135345457304674925447266850196888143238824478,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log","log_context":["UVM_INFO @ 3163.562766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pinmux_sleep_retention","qual_name":"1.chip_sw_spi_device_pinmux_sleep_retention.13440774591118336459367068506809569919289914097254446960745013993241687972282","seed":13440774591118336459367068506809569919289914097254446960745013993241687972282,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log","log_context":["UVM_INFO @ 2802.886632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.22175907826992160843249985660405789144451663749890740621463119357020418351119","seed":22175907826992160843249985660405789144451663749890740621463119357020418351119,"line":392,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 7001.690478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.101894816592580623195133349142482927235399999195449851075195070740754643471361","seed":101894816592580623195133349142482927235399999195449851075195070740754643471361,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 3216.645696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"1.chip_sw_pwrmgr_normal_sleep_por_reset.29040070691958303579074882606866144812138536933934524115559050871608090132689","seed":29040070691958303579074882606866144812138536933934524115559050871608090132689,"line":388,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 5103.499448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.93484772907573933403604267836120884131983283159187841422879144244872994799269","seed":93484772907573933403604267836120884131983283159187841422879144244872994799269,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_INFO @ 3897.852496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_pings.72322119230582962313265447924785961931046530298606634849220007322143719063837","seed":72322119230582962313265447924785961931046530298606634849220007322143719063837,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 2993.263336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"1.chip_sw_sleep_sram_ret_contents_no_scramble.16544331895456870888451771238714934133502347706053562954056272264880676809548","seed":16544331895456870888451771238714934133502347706053562954056272264880676809548,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 3409.384972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"1.chip_sw_sleep_sram_ret_contents_scramble.31970840545899203724959648611890016432032191931940523451220107640381359738096","seed":31970840545899203724959648611890016432032191931940523451220107640381359738096,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 2864.139114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.55594651187896361983354592827672727094917092939959847025556138842868599403726","seed":55594651187896361983354592827672727094917092939959847025556138842868599403726,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 2685.272840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"1.chip_sw_clkmgr_sleep_frequency.105708457536462583786713891731302889805054907537848384661639407678222629870273","seed":105708457536462583786713891731302889805054907537848384661639407678222629870273,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 4083.255944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.81574761498982992634033006142336509546815616523003216246022567437340065175978","seed":81574761498982992634033006142336509546815616523003216246022567437340065175978,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 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---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"1.chip_sw_pwrmgr_random_sleep_all_wake_ups.45552773859167073794255802920820446760328260079730584476801875821304987708827","seed":45552773859167073794255802920820446760328260079730584476801875821304987708827,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2439.794972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"1.chip_sw_rv_dm_access_after_wakeup.86993171589905504009633871262473884738783868424547998263703928938991775672355","seed":86993171589905504009633871262473884738783868424547998263703928938991775672355,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2180.658528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_wake","qual_name":"2.chip_sw_sleep_pin_wake.103727039290473523871204170877465888676670076675937644102266440268999343152620","seed":103727039290473523871204170877465888676670076675937644102266440268999343152620,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_wake/latest/run.log","log_context":["UVM_INFO @ 2773.767192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_pin_retention","qual_name":"2.chip_sw_sleep_pin_retention.30307960775832409306698271576226743443329977245417009850271689706891009492840","seed":30307960775832409306698271576226743443329977245417009850271689706891009492840,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_retention/latest/run.log","log_context":["UVM_INFO @ 3340.093974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pinmux_sleep_retention","qual_name":"2.chip_sw_spi_device_pinmux_sleep_retention.107102461890495700857881171380643747675585108839668690085329002619224266398037","seed":107102461890495700857881171380643747675585108839668690085329002619224266398037,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log","log_context":["UVM_INFO @ 2891.651056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.42687813882861618586895418504575543186570759703707227183252615368040280224163","seed":42687813882861618586895418504575543186570759703707227183252615368040280224163,"line":392,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 7139.882682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_reset_reqs","qual_name":"2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.34684361286165844753116945465893786947744689036637608878512972097258141550345","seed":34684361286165844753116945465893786947744689036637608878512972097258141550345,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log","log_context":["UVM_INFO @ 4200.914184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_por_reset","qual_name":"2.chip_sw_pwrmgr_normal_sleep_por_reset.39462187780568950300631478028972015148195552573444837113425700684529056013646","seed":39462187780568950300631478028972015148195552573444837113425700684529056013646,"line":388,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log","log_context":["UVM_INFO @ 4836.259080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.48389748844869700635035385671343756394427521638679776286135639855989461098760","seed":48389748844869700635035385671343756394427521638679776286135639855989461098760,"line":418,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_INFO @ 9596.430986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_no_scramble","qual_name":"2.chip_sw_sleep_sram_ret_contents_no_scramble.11274159757763741047365854245385958582176906537852319842399333734460430734972","seed":11274159757763741047365854245385958582176906537852319842399333734460430734972,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest/run.log","log_context":["UVM_INFO @ 3398.253516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_sleep_sram_ret_contents_scramble","qual_name":"2.chip_sw_sleep_sram_ret_contents_scramble.87840933567304560152546353529262645095324036529102034665096008479691837302951","seed":87840933567304560152546353529262645095324036529102034665096008479691837302951,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_sram_ret_contents_scramble/latest/run.log","log_context":["UVM_INFO @ 2887.944536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup","qual_name":"2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.94526656414887530515491247685990808736730332441395758413379850807136942631442","seed":94526656414887530515491247685990808736730332441395758413379850807136942631442,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest/run.log","log_context":["UVM_INFO @ 2630.977522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_sleep_frequency","qual_name":"2.chip_sw_clkmgr_sleep_frequency.12120465704283357138884158470093581247719045300941518468740537646680527396637","seed":12120465704283357138884158470093581247719045300941518468740537646680527396637,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_sleep_frequency/latest/run.log","log_context":["UVM_INFO @ 4760.357724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_normal_sleep_all_wake_ups","qual_name":"2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.24066189028863610808965302515138499051343005267269556329148810060011514268124","seed":24066189028863610808965302515138499051343005267269556329148810060011514268124,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2959.482288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_lowpower_cancel","qual_name":"2.chip_sw_pwrmgr_lowpower_cancel.28260358495238517494569240262964812896819071626710707937567892584496422809157","seed":28260358495238517494569240262964812896819071626710707937567892584496422809157,"line":372,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log","log_context":["UVM_INFO @ 3104.490704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_pwrmgr_random_sleep_all_wake_ups","qual_name":"2.chip_sw_pwrmgr_random_sleep_all_wake_ups.51973989337672156847811180476954436179412860456765463969928584373757059479344","seed":51973989337672156847811180476954436179412860456765463969928584373757059479344,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log","log_context":["UVM_INFO @ 2509.038264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rv_dm_access_after_wakeup","qual_name":"2.chip_sw_rv_dm_access_after_wakeup.5127971529590386067408495463793419531547635125283394150531090761367752266306","seed":5127971529590386067408495463793419531547635125283394150531090761367752266306,"line":390,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log","log_context":["UVM_INFO @ 2861.146584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_power_sleep_load","qual_name":"2.chip_sw_power_sleep_load.10930080614342755869531497309092683581852871227737062955492266715538823848123","seed":10930080614342755869531497309092683581852871227737062955492266715538823848123,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_sleep_load/latest/run.log","log_context":["UVM_INFO @ 3699.519992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty":[{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"0.chip_sw_spi_device_pass_through_collision.22811602167771388420136277437353553899484212918270235070005105539141294062328","seed":22811602167771388420136277437353553899484212918270235070005105539141294062328,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3037.657496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"1.chip_sw_spi_device_pass_through_collision.20663295967102474824302717562191437513796792161371052889427550551998745792343","seed":20663295967102474824302717562191437513796792161371052889427550551998745792343,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3061.472618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_spi_device_pass_through_collision","qual_name":"2.chip_sw_spi_device_pass_through_collision.6133436670535673244844355499119556323993093817224433255387529803529871461343","seed":6133436670535673244844355499119556323993093817224433255387529803529871461343,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log","log_context":["UVM_INFO @ 3092.087512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred!":[{"name":"chip_sw_rram_rma_unlocked","qual_name":"0.chip_sw_rram_rma_unlocked.55065578840644606706976725631587807067705564873919267923409562718632518691122","seed":55065578840644606706976725631587807067705564873919267923409562718632518691122,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rram_rma_unlocked","qual_name":"1.chip_sw_rram_rma_unlocked.104607477243989792506230767877687004893383453257778808544955465952938358236597","seed":104607477243989792506230767877687004893383453257778808544955465952938358236597,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_rram_rma_unlocked","qual_name":"2.chip_sw_rram_rma_unlocked.72553136572751690934250711440157030612606170165887463874128262104079591017475","seed":72553136572751690934250711440157030612606170165887463874128262104079591017475,"line":337,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rram_rma_unlocked/latest/run.log","log_context":["UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *":[{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"0.chip_sw_otp_ctrl_lc_signals_rma.27456890769609242453517221501199134731776135982086397697139903087493660068383","seed":27456890769609242453517221501199134731776135982086397697139903087493660068383,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 5709.142300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"1.chip_sw_otp_ctrl_lc_signals_rma.63632215004899288680416262768217388195329413761010655658005707882235160639076","seed":63632215004899288680416262768217388195329413761010655658005707882235160639076,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6732.567464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_otp_ctrl_lc_signals_rma","qual_name":"2.chip_sw_otp_ctrl_lc_signals_rma.20543024098799413749911216589832812127382028672928894555771990719399750602147","seed":20543024098799413749911216589832812127382028672928894555771990719399750602147,"line":404,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log","log_context":["UVM_INFO @ 6643.309516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'":[{"name":"chip_sw_otp_ctrl_escalation","qual_name":"0.chip_sw_otp_ctrl_escalation.103039486054982184887829904796203753585676862525204878302808887729922204183331","seed":103039486054982184887829904796203753585676862525204878302808887729922204183331,"line":380,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log","log_context":["UVM_ERROR @ 2787.225254 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2787.225254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"7.chip_sw_all_escalation_resets.85592105003340560831130688943723924389331804180876372981412651400877075671420","seed":85592105003340560831130688943723924389331804180876372981412651400877075671420,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2192.569858 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2192.569858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"27.chip_sw_all_escalation_resets.55835850285588271747765022959273574648128608285548266698165659811465834593063","seed":55835850285588271747765022959273574648128608285548266698165659811465834593063,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3002.651648 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3002.651648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"60.chip_sw_all_escalation_resets.12897717775312591340499672823247620466265035591905959082130415835303197315274","seed":12897717775312591340499672823247620466265035591905959082130415835303197315274,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 3372.058464 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 3372.058464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"63.chip_sw_all_escalation_resets.94499040578567516217714947668621541821154219228577701566388446186050904060780","seed":94499040578567516217714947668621541821154219228577701566388446186050904060780,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_ERROR @ 2529.823632 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A\n","UVM_INFO @ 2529.823632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"Error-[NOA] Null object access":[{"name":"chip_sw_otp_ctrl_rot_auth_config","qual_name":"0.chip_sw_otp_ctrl_rot_auth_config.6207319797513935812076996667714112342361642758816956279859236681259747035652","seed":6207319797513935812076996667714112342361642758816956279859236681259747035652,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2000058772465761951114261252534559278975453153703308036903970055020455105666","seed":2000058772465761951114261252534559278975453153703308036903970055020455105666,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_test_unlocked0","qual_name":"0.rom_e2e_jtag_inject_test_unlocked0.73114431518653855234497699688079377654168882977932074091442648745592770532966","seed":73114431518653855234497699688079377654168882977932074091442648745592770532966,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_dev","qual_name":"0.rom_e2e_jtag_inject_dev.61821335088894314492170696917139625441189435177872954051625545775560018650907","seed":61821335088894314492170696917139625441189435177872954051625545775560018650907,"line":379,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"rom_e2e_jtag_inject_rma","qual_name":"0.rom_e2e_jtag_inject_rma.46261062240619655044079066174134679928135425625156726360425875472475155673041","seed":46261062240619655044079066174134679928135425625156726360425875472475155673041,"line":381,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.5015445600600733274806943652805464709403776222662767872872466646616297835385","seed":5015445600600733274806943652805464709403776222662767872872466646616297835385,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]},{"name":"chip_sw_rv_dm_ndm_reset_req_when_cpu_halted","qual_name":"2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.87271247477450680508603820045720533200531770978330434185562331483742776163440","seed":87271247477450680508603820045720533200531770978330434185562331483742776163440,"line":403,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log","log_context":["src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108\n","  The object at dereference depth 1 is being used before it was \n","  constructed/allocated.\n","  Please make sure that the object is allocated before using it. \n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl":[{"name":"chip_sw_lc_ctrl_test_locked0_to_scrap","qual_name":"0.chip_sw_lc_ctrl_test_locked0_to_scrap.102998562918424545294523843744119158742122877209543238406622997793357380596331","seed":102998562918424545294523843744119158742122877209543238406622997793357380596331,"line":375,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log","log_context":["UVM_INFO @ 8275.319965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_ctrl_rand_to_scrap","qual_name":"1.chip_sw_lc_ctrl_rand_to_scrap.38315968147227968057794468218268967972812205091320436751272912784822324683172","seed":38315968147227968057794468218268967972812205091320436751272912784822324683172,"line":375,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log","log_context":["UVM_INFO @ 10919.279352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_lc_walkthrough_dev","qual_name":"0.chip_sw_lc_walkthrough_dev.38983780446723440008378895039924678732090326921128993799880245514291334859980","seed":38983780446723440008378895039924678732090326921128993799880245514291334859980,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 16420.516426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"0.chip_sw_lc_walkthrough_prod.87454361496454265038014947737152889878684061984304385088611492874327096475421","seed":87454361496454265038014947737152889878684061984304385088611492874327096475421,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 18714.958076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"0.chip_sw_lc_walkthrough_rma.11393654782917525798963635367287591031231749907061483338079358243364089047012","seed":11393654782917525798963635367287591031231749907061483338079358243364089047012,"line":405,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 12461.577400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"1.chip_sw_lc_walkthrough_dev.53855833042062655147832400778468750036332068610989394360392775910463769108693","seed":53855833042062655147832400778468750036332068610989394360392775910463769108693,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 17905.967996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"1.chip_sw_lc_walkthrough_prod.100324615628206238569483796495039987935093570296810154511367308260810800938391","seed":100324615628206238569483796495039987935093570296810154511367308260810800938391,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 17859.453570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"1.chip_sw_lc_walkthrough_rma.100325503858027682328646139823238780479362097020784332120390039806808331246319","seed":100325503858027682328646139823238780479362097020784332120390039806808331246319,"line":405,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 13069.596559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_dev","qual_name":"2.chip_sw_lc_walkthrough_dev.97658848693658254948719679703541642337402786487833892185740824636463562153682","seed":97658848693658254948719679703541642337402786487833892185740824636463562153682,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_dev/latest/run.log","log_context":["UVM_INFO @ 17005.065700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_prod","qual_name":"2.chip_sw_lc_walkthrough_prod.106067322371738993215121556723435781575964478299454187663404433245839801322963","seed":106067322371738993215121556723435781575964478299454187663404433245839801322963,"line":433,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_prod/latest/run.log","log_context":["UVM_INFO @ 21359.253780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_lc_walkthrough_rma","qual_name":"2.chip_sw_lc_walkthrough_rma.90157219195537465601418862989016960391237103745100186726658766716675215810118","seed":90157219195537465601418862989016960391237103745100186726658766716675215810118,"line":405,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_walkthrough_rma/latest/run.log","log_context":["UVM_INFO @ 11272.773778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'":[{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"0.chip_sw_pwrmgr_sleep_power_glitch_reset.70578031173165924867065585182495342784562734181525940642222746556980627022070","seed":70578031173165924867065585182495342784562734181525940642222746556980627022070,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2907.806520 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2907.806520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"1.chip_sw_pwrmgr_sleep_power_glitch_reset.33405783724376722916279117586277030404809923357394582830904551783038876926798","seed":33405783724376722916279117586277030404809923357394582830904551783038876926798,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 2925.223108 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 2925.223108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_pwrmgr_sleep_power_glitch_reset","qual_name":"2.chip_sw_pwrmgr_sleep_power_glitch_reset.109156501576528691715518427093598869549459793294620677481418281605743791488886","seed":109156501576528691715518427093598869549459793294620677481418281605743791488886,"line":377,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log","log_context":["UVM_ERROR @ 3378.571532 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A\n","UVM_INFO @ 3378.571532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:550)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"0.chip_sw_alert_test.26737069733860727553371092849490328210310134476998856048216749688154741037393","seed":26737069733860727553371092849490328210310134476998856048216749688154741037393,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 2772.364997 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_alerts.84295578437276288234858553977075040604259462597852671212106394828760454544586","seed":84295578437276288234858553977075040604259462597852671212106394828760454544586,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2553.699025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"1.chip_sw_alert_handler_lpg_sleep_mode_alerts.30891779320679450334204171879729001039740601658206784083314317406784119053728","seed":30891779320679450334204171879729001039740601658206784083314317406784119053728,"line":378,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2547.531247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2539429307170447639270545554056049373339618708940631989313920569451549916403","seed":2539429307170447639270545554056049373339618708940631989313920569451549916403,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3094.207250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"3.chip_sw_alert_handler_lpg_sleep_mode_alerts.102104393806248665137805808291504941500515956354168072792998449774516329560736","seed":102104393806248665137805808291504941500515956354168072792998449774516329560736,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2493.610040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"4.chip_sw_alert_handler_lpg_sleep_mode_alerts.108174248083605770666567854795752112189639546762544506677158283120670497739666","seed":108174248083605770666567854795752112189639546762544506677158283120670497739666,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2225.863780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"5.chip_sw_alert_handler_lpg_sleep_mode_alerts.106950667781900457617062992597579699032861472613195070766683932466644778820103","seed":106950667781900457617062992597579699032861472613195070766683932466644778820103,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2438.932971 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"6.chip_sw_alert_handler_lpg_sleep_mode_alerts.23283731448571228159381747410670698515687978448058917147575278524496073055391","seed":23283731448571228159381747410670698515687978448058917147575278524496073055391,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2363.078190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"7.chip_sw_alert_handler_lpg_sleep_mode_alerts.24306329996532681481399747526586859335220939633929075654011428338243800715787","seed":24306329996532681481399747526586859335220939633929075654011428338243800715787,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2417.945692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"8.chip_sw_alert_handler_lpg_sleep_mode_alerts.81485594528582967464191617851169452518771038038512081073729869086159413470971","seed":81485594528582967464191617851169452518771038038512081073729869086159413470971,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3112.193519 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"9.chip_sw_alert_handler_lpg_sleep_mode_alerts.30357215254903058318595574038692551401094035182134687316964528471297639429455","seed":30357215254903058318595574038692551401094035182134687316964528471297639429455,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2742.566482 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"10.chip_sw_alert_handler_lpg_sleep_mode_alerts.102922024966954173839706408381885693819898300022866509469074516907365293696603","seed":102922024966954173839706408381885693819898300022866509469074516907365293696603,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3038.385340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"11.chip_sw_alert_handler_lpg_sleep_mode_alerts.100667501240359830708668786889471481793323776622955806308219050022867846833765","seed":100667501240359830708668786889471481793323776622955806308219050022867846833765,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2196.271880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"12.chip_sw_alert_handler_lpg_sleep_mode_alerts.56168006380551403104634377795808733240903635280407227398111796613376099903906","seed":56168006380551403104634377795808733240903635280407227398111796613376099903906,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2460.505077 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"13.chip_sw_alert_handler_lpg_sleep_mode_alerts.96992706698395065655385604657693697166103639335819551631580817799601481635464","seed":96992706698395065655385604657693697166103639335819551631580817799601481635464,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2600.396780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"14.chip_sw_alert_handler_lpg_sleep_mode_alerts.46570492770943321303299677962045090324274078598201115614641687724549683577375","seed":46570492770943321303299677962045090324274078598201115614641687724549683577375,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2367.103120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"15.chip_sw_alert_handler_lpg_sleep_mode_alerts.50320220891477281845403796764732459279607079262243953082790878234108744120338","seed":50320220891477281845403796764732459279607079262243953082790878234108744120338,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2983.566096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"16.chip_sw_alert_handler_lpg_sleep_mode_alerts.60526355911155939420357633330060787637477529825748512280777633253593846652924","seed":60526355911155939420357633330060787637477529825748512280777633253593846652924,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2932.693902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1132500119113396416196926728125746807586438291390592898027263141223757636643","seed":1132500119113396416196926728125746807586438291390592898027263141223757636643,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2558.622840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"18.chip_sw_alert_handler_lpg_sleep_mode_alerts.109678864756688676946597472563525106549453012552392660358605133332400273513678","seed":109678864756688676946597472563525106549453012552392660358605133332400273513678,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2836.152820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"19.chip_sw_alert_handler_lpg_sleep_mode_alerts.59672349239410250880552409794297847145979721486404907824130962699955485288600","seed":59672349239410250880552409794297847145979721486404907824130962699955485288600,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2147.809139 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"20.chip_sw_alert_handler_lpg_sleep_mode_alerts.97540924636301362959380643887151038125290644572792198268645513221958814921127","seed":97540924636301362959380643887151038125290644572792198268645513221958814921127,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3032.628100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"21.chip_sw_alert_handler_lpg_sleep_mode_alerts.90836774566568873768903709731152858394645173985256655058407665948675931183653","seed":90836774566568873768903709731152858394645173985256655058407665948675931183653,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2868.491700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"22.chip_sw_alert_handler_lpg_sleep_mode_alerts.70918636619649439377780800928023713595703326871055054454742218223652300122825","seed":70918636619649439377780800928023713595703326871055054454742218223652300122825,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2884.217168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"23.chip_sw_alert_handler_lpg_sleep_mode_alerts.91455738225818558859198323827166670543808824844955666575507494526366067942506","seed":91455738225818558859198323827166670543808824844955666575507494526366067942506,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2388.313331 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"24.chip_sw_alert_handler_lpg_sleep_mode_alerts.94414147925153674831939940674128409082717093888738587213670041571650886510361","seed":94414147925153674831939940674128409082717093888738587213670041571650886510361,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2666.672462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"25.chip_sw_alert_handler_lpg_sleep_mode_alerts.96803626678531935783556088479963706808047236206372844310366897992951287004994","seed":96803626678531935783556088479963706808047236206372844310366897992951287004994,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2907.849000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"26.chip_sw_alert_handler_lpg_sleep_mode_alerts.11958487817841671014408136889807777783053539786841145678957738746922196843016","seed":11958487817841671014408136889807777783053539786841145678957738746922196843016,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2878.051854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"27.chip_sw_alert_handler_lpg_sleep_mode_alerts.57172178348821940439064975966175693090430213178665235926289238010174023804520","seed":57172178348821940439064975966175693090430213178665235926289238010174023804520,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2637.530575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"28.chip_sw_alert_handler_lpg_sleep_mode_alerts.38020633198975302090274320901492553236355838703805476417507651519874731368684","seed":38020633198975302090274320901492553236355838703805476417507651519874731368684,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3036.728958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"29.chip_sw_alert_handler_lpg_sleep_mode_alerts.27412985559988856536423858475545019415590652656649862846077794619949434462472","seed":27412985559988856536423858475545019415590652656649862846077794619949434462472,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2779.808102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"30.chip_sw_alert_handler_lpg_sleep_mode_alerts.56475142937641645502010567255338837910570045390348107955295396770281560366141","seed":56475142937641645502010567255338837910570045390348107955295396770281560366141,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2269.012440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"31.chip_sw_alert_handler_lpg_sleep_mode_alerts.100275242963054085155617240784842843943172076164200965885558417466912067725230","seed":100275242963054085155617240784842843943172076164200965885558417466912067725230,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2945.191537 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"32.chip_sw_alert_handler_lpg_sleep_mode_alerts.8820754147373558134753450331481801487678930752671781891636159420251764452042","seed":8820754147373558134753450331481801487678930752671781891636159420251764452042,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2555.106568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"33.chip_sw_alert_handler_lpg_sleep_mode_alerts.98659587942276483517587741949096393611042632841007440837375578193292344271711","seed":98659587942276483517587741949096393611042632841007440837375578193292344271711,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2310.767917 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"34.chip_sw_alert_handler_lpg_sleep_mode_alerts.68906588857013059586661420392643528719709493325103852027644966326435075522631","seed":68906588857013059586661420392643528719709493325103852027644966326435075522631,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2664.971364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"35.chip_sw_alert_handler_lpg_sleep_mode_alerts.57996131131555206576171606334408240826271772478938091662104871622969144549035","seed":57996131131555206576171606334408240826271772478938091662104871622969144549035,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3020.759153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"36.chip_sw_alert_handler_lpg_sleep_mode_alerts.85775500077397588359024459943509713870125194844496820904902748002425436775142","seed":85775500077397588359024459943509713870125194844496820904902748002425436775142,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2574.181730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"37.chip_sw_alert_handler_lpg_sleep_mode_alerts.40471019186241765990911406683225406287107575972427661913631246576024880464805","seed":40471019186241765990911406683225406287107575972427661913631246576024880464805,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2840.832981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"38.chip_sw_alert_handler_lpg_sleep_mode_alerts.86396169995210336304467545485754242227415432167627884590319079930961897554608","seed":86396169995210336304467545485754242227415432167627884590319079930961897554608,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2350.040800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"39.chip_sw_alert_handler_lpg_sleep_mode_alerts.48142573495714529769040049928885550739425401399432149905533920720135797386418","seed":48142573495714529769040049928885550739425401399432149905533920720135797386418,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2566.118936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"40.chip_sw_alert_handler_lpg_sleep_mode_alerts.39933266105023262521820936278107407241520704236134734279642702634065288416128","seed":39933266105023262521820936278107407241520704236134734279642702634065288416128,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2946.013514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420453093657752063374894825883219737904406039913171286387405781958827813741","seed":2420453093657752063374894825883219737904406039913171286387405781958827813741,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2941.394578 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"42.chip_sw_alert_handler_lpg_sleep_mode_alerts.52422206040239092603394860669861698474468427034877138755082608224325067854576","seed":52422206040239092603394860669861698474468427034877138755082608224325067854576,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2457.184912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"43.chip_sw_alert_handler_lpg_sleep_mode_alerts.101821267196716020762445849539759046832288604764859207169775978859655045901964","seed":101821267196716020762445849539759046832288604764859207169775978859655045901964,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2686.644860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"44.chip_sw_alert_handler_lpg_sleep_mode_alerts.32679573957740362487136586185290692883458082103179721403492737299895022655019","seed":32679573957740362487136586185290692883458082103179721403492737299895022655019,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2750.158500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"45.chip_sw_alert_handler_lpg_sleep_mode_alerts.59214407907933400427042796998958657568812773422021909638154610835069234007189","seed":59214407907933400427042796998958657568812773422021909638154610835069234007189,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2141.283194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"46.chip_sw_alert_handler_lpg_sleep_mode_alerts.65687548358281395024274279658371118533415013763823076847490952622882928489415","seed":65687548358281395024274279658371118533415013763823076847490952622882928489415,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2790.257378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"47.chip_sw_alert_handler_lpg_sleep_mode_alerts.92577628816580362127599266513356946708662634947724413541628456486982680203724","seed":92577628816580362127599266513356946708662634947724413541628456486982680203724,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2733.465900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"48.chip_sw_alert_handler_lpg_sleep_mode_alerts.108916201325484869621512188076215163312946241918451645091528618733827669812576","seed":108916201325484869621512188076215163312946241918451645091528618733827669812576,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2265.189888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"49.chip_sw_alert_handler_lpg_sleep_mode_alerts.74595750727926574666836898669646394198742368779301274629576012200156848154595","seed":74595750727926574666836898669646394198742368779301274629576012200156848154595,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2594.300895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"50.chip_sw_alert_handler_lpg_sleep_mode_alerts.38103871153665266052892119408076657277622424517503244230421656892885753166523","seed":38103871153665266052892119408076657277622424517503244230421656892885753166523,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2438.680964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"51.chip_sw_alert_handler_lpg_sleep_mode_alerts.110208215624388488332201690377434323081420403219898125136538809200871330491881","seed":110208215624388488332201690377434323081420403219898125136538809200871330491881,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2984.168408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"52.chip_sw_alert_handler_lpg_sleep_mode_alerts.53328910237194419193021631856682056225734504313723821284919732486954799527779","seed":53328910237194419193021631856682056225734504313723821284919732486954799527779,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2489.365504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"53.chip_sw_alert_handler_lpg_sleep_mode_alerts.30018651080510648563980613791713324291062980539637049201406140822353125344645","seed":30018651080510648563980613791713324291062980539637049201406140822353125344645,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3086.512286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"54.chip_sw_alert_handler_lpg_sleep_mode_alerts.49149639887196239728668739341381907993555215764073583025595631217961375139773","seed":49149639887196239728668739341381907993555215764073583025595631217961375139773,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2678.469343 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"55.chip_sw_alert_handler_lpg_sleep_mode_alerts.70914415761357658569054819388623841775026192758622204150441753604401457313938","seed":70914415761357658569054819388623841775026192758622204150441753604401457313938,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2896.595737 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"56.chip_sw_alert_handler_lpg_sleep_mode_alerts.19849887090232785452337546099264907201925753628169969422200488817335852802083","seed":19849887090232785452337546099264907201925753628169969422200488817335852802083,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2705.889765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"57.chip_sw_alert_handler_lpg_sleep_mode_alerts.42702478756567201667060921778010590083391941861066950836763206789809566015261","seed":42702478756567201667060921778010590083391941861066950836763206789809566015261,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2311.267248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"58.chip_sw_alert_handler_lpg_sleep_mode_alerts.22061690152869197554491801814312098159405757688594103566318907425273836299765","seed":22061690152869197554491801814312098159405757688594103566318907425273836299765,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2400.128968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"59.chip_sw_alert_handler_lpg_sleep_mode_alerts.93519788208734333916982456600032987652826633698214245616325528561823337382450","seed":93519788208734333916982456600032987652826633698214245616325528561823337382450,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2520.835852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"60.chip_sw_alert_handler_lpg_sleep_mode_alerts.79805663844469098885186231099017384567594672633261241432998831320424811459012","seed":79805663844469098885186231099017384567594672633261241432998831320424811459012,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2828.998286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"61.chip_sw_alert_handler_lpg_sleep_mode_alerts.33305969147740697359242770050550146462949330471292748106025090816464438154176","seed":33305969147740697359242770050550146462949330471292748106025090816464438154176,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2372.457221 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"62.chip_sw_alert_handler_lpg_sleep_mode_alerts.67268135830766859075415090227819433288970062550429390209763541305356527436881","seed":67268135830766859075415090227819433288970062550429390209763541305356527436881,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2543.126838 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"63.chip_sw_alert_handler_lpg_sleep_mode_alerts.23561946173602619193527854758415058154449034205198030679365835326437878064517","seed":23561946173602619193527854758415058154449034205198030679365835326437878064517,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2638.766220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"64.chip_sw_alert_handler_lpg_sleep_mode_alerts.6584026107685491706118716166317734928535773404756591053933260048623526044016","seed":6584026107685491706118716166317734928535773404756591053933260048623526044016,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2709.248688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"65.chip_sw_alert_handler_lpg_sleep_mode_alerts.96581819107861044511200094178211670274321664694115778361918517129400765812285","seed":96581819107861044511200094178211670274321664694115778361918517129400765812285,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2551.042704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"66.chip_sw_alert_handler_lpg_sleep_mode_alerts.113577115173944445678920512103951382721550256511514706758270640281876668931200","seed":113577115173944445678920512103951382721550256511514706758270640281876668931200,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2757.351750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"67.chip_sw_alert_handler_lpg_sleep_mode_alerts.32111519109655294715365597324586548480456846912423151827983942880870436117887","seed":32111519109655294715365597324586548480456846912423151827983942880870436117887,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2751.110956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"68.chip_sw_alert_handler_lpg_sleep_mode_alerts.76099317022342792598305148167808466779276459289008375640838368772026831347498","seed":76099317022342792598305148167808466779276459289008375640838368772026831347498,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2589.997362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"69.chip_sw_alert_handler_lpg_sleep_mode_alerts.103365286261724456737855166537784023342299362187590938783244037682260782878018","seed":103365286261724456737855166537784023342299362187590938783244037682260782878018,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2999.572784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"70.chip_sw_alert_handler_lpg_sleep_mode_alerts.65626816653275525735032555644304049864846148507210534249530303988032563040694","seed":65626816653275525735032555644304049864846148507210534249530303988032563040694,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2729.767628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"71.chip_sw_alert_handler_lpg_sleep_mode_alerts.19519534048120080578834601902647313495547822007612881448821403920501494674484","seed":19519534048120080578834601902647313495547822007612881448821403920501494674484,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2933.577718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"72.chip_sw_alert_handler_lpg_sleep_mode_alerts.37927448115378726732817357254655261531888552663668504506970293755706463812566","seed":37927448115378726732817357254655261531888552663668504506970293755706463812566,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2565.065120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"73.chip_sw_alert_handler_lpg_sleep_mode_alerts.107979332081777914733725317510435858559909827007630128985800255520012344434820","seed":107979332081777914733725317510435858559909827007630128985800255520012344434820,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2279.831138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"74.chip_sw_alert_handler_lpg_sleep_mode_alerts.53472447074038994184945664781478291660533081669557715989229057843161149126930","seed":53472447074038994184945664781478291660533081669557715989229057843161149126930,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2359.805970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"75.chip_sw_alert_handler_lpg_sleep_mode_alerts.76148861388092365559007257653234768841247544934546325680065101480734410203469","seed":76148861388092365559007257653234768841247544934546325680065101480734410203469,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2697.226184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"76.chip_sw_alert_handler_lpg_sleep_mode_alerts.69417540400148028236494088413343302928631148071916815378041595221438781639564","seed":69417540400148028236494088413343302928631148071916815378041595221438781639564,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2268.896560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"77.chip_sw_alert_handler_lpg_sleep_mode_alerts.11598635810829411571300231012226853696165503039055393607007671997719448087711","seed":11598635810829411571300231012226853696165503039055393607007671997719448087711,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2847.030165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"78.chip_sw_alert_handler_lpg_sleep_mode_alerts.72783207187846719920199355212570933230835237556390880588779504213907956369633","seed":72783207187846719920199355212570933230835237556390880588779504213907956369633,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2860.720477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"79.chip_sw_alert_handler_lpg_sleep_mode_alerts.28879231169890076707266941710053194746063436019364400225307191073137922902689","seed":28879231169890076707266941710053194746063436019364400225307191073137922902689,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2954.890477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"80.chip_sw_alert_handler_lpg_sleep_mode_alerts.72974980415209024785712209541530499957037873175289871036403433040011533752260","seed":72974980415209024785712209541530499957037873175289871036403433040011533752260,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2746.180965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"81.chip_sw_alert_handler_lpg_sleep_mode_alerts.96106491369783119897814353678922808326023731695934550856663867654985092187666","seed":96106491369783119897814353678922808326023731695934550856663867654985092187666,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2726.762920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"82.chip_sw_alert_handler_lpg_sleep_mode_alerts.84116083933167247559681854605584819494155546525385866260742743791530786869349","seed":84116083933167247559681854605584819494155546525385866260742743791530786869349,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2671.925330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"83.chip_sw_alert_handler_lpg_sleep_mode_alerts.40147133863141249623360544837572535877959880241398762688082194036190699190519","seed":40147133863141249623360544837572535877959880241398762688082194036190699190519,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2273.995200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"84.chip_sw_alert_handler_lpg_sleep_mode_alerts.114443002545544741678622691003885993523417563738773826773626693093873616110681","seed":114443002545544741678622691003885993523417563738773826773626693093873616110681,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2381.101160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"85.chip_sw_alert_handler_lpg_sleep_mode_alerts.74740230332331815607058074778763749980459662542349574415730158541884566106878","seed":74740230332331815607058074778763749980459662542349574415730158541884566106878,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2584.154885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"86.chip_sw_alert_handler_lpg_sleep_mode_alerts.96454292000557714357647856521792975104479698645006477865236817105194244822220","seed":96454292000557714357647856521792975104479698645006477865236817105194244822220,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2645.906401 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"87.chip_sw_alert_handler_lpg_sleep_mode_alerts.70233969989581949609921155590550459662617724484430066422197376314614206645900","seed":70233969989581949609921155590550459662617724484430066422197376314614206645900,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 3059.893810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"88.chip_sw_alert_handler_lpg_sleep_mode_alerts.85791624993186489337429272380743193854965999590042745611888905898230310431775","seed":85791624993186489337429272380743193854965999590042745611888905898230310431775,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2826.946668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_alerts","qual_name":"89.chip_sw_alert_handler_lpg_sleep_mode_alerts.23182017693158737841335239881069066995324364394167262103566916785374949659446","seed":23182017693158737841335239881069066995324364394167262103566916785374949659446,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log","log_context":["UVM_INFO @ 2284.647962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error":[{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"0.chip_sw_alert_handler_lpg_sleep_mode_pings.22707195998524228063768897843605966265290366672294864000379099918044664207153","seed":22707195998524228063768897843605966265290366672294864000379099918044664207153,"line":373,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 2857.207118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"0.chip_sw_alert_handler_entropy.7729100713093136524387039184287564821131288872678469488866063663373635435279","seed":7729100713093136524387039184287564821131288872678469488866063663373635435279,"line":482,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 3177.551130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"1.chip_sw_alert_handler_entropy.111321463174015570659973444082490887688266101919732132420402790249874059941111","seed":111321463174015570659973444082490887688266101919732132420402790249874059941111,"line":480,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 3036.817488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_lpg_sleep_mode_pings","qual_name":"2.chip_sw_alert_handler_lpg_sleep_mode_pings.59841556866413263777931825027256776005995445506051381724290530652591770052952","seed":59841556866413263777931825027256776005995445506051381724290530652591770052952,"line":374,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log","log_context":["UVM_INFO @ 2711.140408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_alert_handler_entropy","qual_name":"2.chip_sw_alert_handler_entropy.42307067868209607740763837227129724037616857477663831095767364282344193373737","seed":42307067868209607740763837227129724037616857477663831095767364282344193373737,"line":486,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_entropy/latest/run.log","log_context":["UVM_INFO @ 2808.685704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns":[{"name":"chip_sw_hmac_multistream","qual_name":"0.chip_sw_hmac_multistream.108893977112406312588064226006589671879516108744942077880328151487596256712538","seed":108893977112406312588064226006589671879516108744942077880328151487596256712538,"line":438,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"chip_sw_hmac_multistream","qual_name":"1.chip_sw_hmac_multistream.1677185280684821971639720990211974090856346363220530469672805394459060366763","seed":1677185280684821971639720990211974090856346363220530469672805394459060366763,"line":417,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_multistream/latest/run.log","log_context":["\n","UVM_INFO @ 12010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state.":[{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"0.chip_sw_clkmgr_reset_frequency.105176193141082123180237514465052456275896570616689217958717191064391771686732","seed":105176193141082123180237514465052456275896570616689217958717191064391771686732,"line":400,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 8269.215580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"1.chip_sw_clkmgr_reset_frequency.87399203381325632133594297713093491951901720984167465813765451486921392630663","seed":87399203381325632133594297713093491951901720984167465813765451486921392630663,"line":400,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 8489.889352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_reset_frequency","qual_name":"2.chip_sw_clkmgr_reset_frequency.113139486781264357610421642623739777718800071817518434193165256879831375715579","seed":113139486781264357610421642623739777718800071817518434193165256879831375715579,"line":400,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_reset_frequency/latest/run.log","log_context":["UVM_INFO @ 10901.361078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected":[{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"0.chip_sw_clkmgr_jitter_frequency.47209138677038209823593774393284286681800991839260019163663763318675984624211","seed":47209138677038209823593774393284286681800991839260019163663763318675984624211,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 2942.803294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"1.chip_sw_clkmgr_jitter_frequency.9706987445483685896445128134264325024065180057713634166313658790039995609592","seed":9706987445483685896445128134264325024065180057713634166313658790039995609592,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3729.951394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_clkmgr_jitter_frequency","qual_name":"2.chip_sw_clkmgr_jitter_frequency.72275414951768846368694258336823381719665125234122666224027422032502958673594","seed":72275414951768846368694258336823381719665125234122666224027422032502958673594,"line":407,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_clkmgr_jitter_frequency/latest/run.log","log_context":["UVM_INFO @ 3221.665705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts!":[{"name":"chip_jtag_csr_rw","qual_name":"0.chip_jtag_csr_rw.13329131707569199205027097571423284481783749008310239538670846379564402212159","seed":13329131707569199205027097571423284481783749008310239538670846379564402212159,"line":5365,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 2453.262155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_jtag_csr_rw","qual_name":"1.chip_jtag_csr_rw.115196616460107493524577012923565796652239461258620065580487835440953470666107","seed":115196616460107493524577012923565796652239461258620065580487835440953470666107,"line":5365,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log","log_context":["UVM_INFO @ 2107.351688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"0.chip_sw_pwrmgr_sleep_wake_5_bug.33701644078026486253096539427740497272056354352416842694536933912298650229857","seed":33701644078026486253096539427740497272056354352416842694536933912298650229857,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"0.rom_e2e_self_hash.1127641348218638005609007368551437785038992584485950201230745703918851913114","seed":1127641348218638005609007368551437785038992584485950201230745703918851913114,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=194986) is running. Waiting for it to complete on the server (server_pid=194999)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"1.chip_sw_pwrmgr_sleep_wake_5_bug.41112187701573258466259125526348269899355538154851526284500529708828157168905","seed":41112187701573258466259125526348269899355538154851526284500529708828157168905,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=200451) is running. Waiting for it to complete on the server (server_pid=194999)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"1.rom_e2e_self_hash.28270094507096393055577479049010177662367947611953844084017935631841760670423","seed":28270094507096393055577479049010177662367947611953844084017935631841760670423,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log","log_context":["Another command (pid=197744) is running. Waiting for it to complete on the server (server_pid=194999)...\n","Another command (pid=222215) is running. Waiting for it to complete on the server (server_pid=194999)...\n","Another command (pid=230241) is running. Waiting for it to complete on the server (server_pid=194999)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"chip_sw_pwrmgr_sleep_wake_5_bug","qual_name":"2.chip_sw_pwrmgr_sleep_wake_5_bug.71739143655630275092592012077405712163516378177713987165254727670484846678436","seed":71739143655630275092592012077405712163516378177713987165254727670484846678436,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log","log_context":["\n","---- STDERR ----\n","Another command (pid=1129369) is running. Waiting for it to complete on the server (server_pid=194999)...\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]},{"name":"rom_e2e_self_hash","qual_name":"2.rom_e2e_self_hash.28575050401488180074716423012715096190401976471310447700538057203397615490368","seed":28575050401488180074716423012715096190401976471310447700538057203397615490368,"line":null,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_e2e_self_hash/latest/run.log","log_context":["---- STDOUT ----\n","\n","---- STDERR ----\n","WARNING: Target pattern parsing failed.\n","ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD\n","ERROR: Build did NOT complete successfully\n","\n","_run_cmd -> had a non-zero return code of 1.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1\n"]}],"UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected *":[{"name":"chip_rv_dm_lc_disabled","qual_name":"0.chip_rv_dm_lc_disabled.39522241646485607056482137695475307880179074782029398076997008483908930771626","seed":39522241646485607056482137695475307880179074782029398076997008483908930771626,"line":292,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 1578.363522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *":[{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"0.chip_sw_ast_clk_rst_inputs.70493660393319810547206088070301748393554940587141672053617982756530800064128","seed":70493660393319810547206088070301748393554940587141672053617982756530800064128,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 12919.607400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"1.chip_sw_ast_clk_rst_inputs.115026292034192164684150306039781094454294327132233149035732216918400887147894","seed":115026292034192164684150306039781094454294327132233149035732216918400887147894,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 9125.866604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_ast_clk_rst_inputs","qual_name":"2.chip_sw_ast_clk_rst_inputs.34546505182461439799648849886490139204112624715203163098721837712005980176079","seed":34546505182461439799648849886490139204112624715203163098721837712005980176079,"line":391,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log","log_context":["UVM_INFO @ 9197.715063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1)":[{"name":"ate_bootstrap_flash_erase","qual_name":"0.ate_bootstrap_flash_erase.34990120406394427616209032874782468098131535155655983318461870144299407778508","seed":34990120406394427616209032874782468098131535155655983318461870144299407778508,"line":339,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"1.ate_bootstrap_flash_erase.36010050122997563315849183477826244281048140860349801648590203271892262089024","seed":36010050122997563315849183477826244281048140860349801648590203271892262089024,"line":339,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"ate_bootstrap_flash_erase","qual_name":"2.ate_bootstrap_flash_erase.31471489855731773912929273670297202699396085036546607454143948132781572190234","seed":31471489855731773912929273670297202699396085036546607454143948132781572190234,"line":339,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.ate_bootstrap_flash_erase/latest/run.log","log_context":["UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*])":[{"name":"rom_e2e_jtag_debug_test_unlocked0","qual_name":"0.rom_e2e_jtag_debug_test_unlocked0.32128394245119258940506753887706297601663257393927984850232600320857772398315","seed":32128394245119258940506753887706297601663257393927984850232600320857772398315,"line":359,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log","log_context":["UVM_INFO @ 2072.481000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_jtag_debug_dev","qual_name":"0.rom_e2e_jtag_debug_dev.15384388182690979752609321501471036190954183409755220708769863973205852676646","seed":15384388182690979752609321501471036190954183409755220708769863973205852676646,"line":359,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log","log_context":["UVM_INFO @ 2202.908500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"rom_e2e_jtag_debug_rma","qual_name":"0.rom_e2e_jtag_debug_rma.3490132146927883977528278432969363144216641718148827182004417150409673570211","seed":3490132146927883977528278432969363144216641718148827182004417150409673570211,"line":359,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log","log_context":["UVM_INFO @ 1696.532500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:711) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).":[{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"0.chip_csr_mem_rw_with_rand_reset.115516967111396483834348888708438660483614800849238802985200458502685679133221","seed":115516967111396483834348888708438660483614800849238802985200458502685679133221,"line":288,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":[" TL item was: req: (cip_tl_seq_item@37430) { a_addr: 'h11000000  a_data: 'h6cf81162  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h0  a_user: 'h25e87  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  } \n"," Reasons for predicted error: '{}.\n","UVM_INFO @ 1672.844935 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly":[{"name":"chip_same_csr_outstanding","qual_name":"1.chip_same_csr_outstanding.108680183784646657688124887402340013429380152738683955060666917609607371846508","seed":108680183784646657688124887402340013429380152738683955060666917609607371846508,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @ 8616.528660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_same_csr_outstanding","qual_name":"3.chip_same_csr_outstanding.21653378363829682222185201879906461264133329813203557453297776205596590233263","seed":21653378363829682222185201879906461264133329813203557453297776205596590233263,"line":282,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @ 5270.252780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"9.chip_sw_all_escalation_resets.97209608513445295667674403633804144669632541940148769490363735439245123175853","seed":97209608513445295667674403633804144669632541940148769490363735439245123175853,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3462.569852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"22.chip_sw_all_escalation_resets.93127676308760665721757955974823234984948877941068124366348549114444098436276","seed":93127676308760665721757955974823234984948877941068124366348549114444098436276,"line":382,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2862.802464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!":[{"name":"chip_sw_lc_walkthrough_testunlocks","qual_name":"1.chip_sw_lc_walkthrough_testunlocks.20692060361578296504688230271472975667900091503003261882902040412298676410284","seed":20692060361578296504688230271472975667900091503003261882902040412298676410284,"line":405,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_testunlocks/latest/run.log","log_context":["UVM_INFO @ 36277.587852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:370)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"1.chip_sw_alert_test.37087463261982431318510388852744249055469555683186213942639405740352221026367","seed":37087463261982431318510388852744249055469555683186213942639405740352221026367,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3002.746725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"chip_rv_dm_lc_disabled","qual_name":"1.chip_rv_dm_lc_disabled.57501030506515253521433000633486987876412672159770260598118646527940283552856","seed":57501030506515253521433000633486987876412672159770260598118646527940283552856,"line":306,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 4164.652635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_rv_dm_lc_disabled","qual_name":"2.chip_rv_dm_lc_disabled.49020886838813451771273743356832628827650536987058313561393520048398821159015","seed":49020886838813451771273743356832628827650536987058313561393520048398821159015,"line":292,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log","log_context":["UVM_INFO @ 1979.486206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement":[{"name":"rom_raw_unlock","qual_name":"1.rom_raw_unlock.28281012034715214830166952302328248846561890411417808318263724996858361353475","seed":28281012034715214830166952302328248846561890411417808318263724996858361353475,"line":398,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log","log_context":["UVM_INFO @ 22052.127678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *!":[{"name":"chip_sw_alert_test","qual_name":"2.chip_sw_alert_test.30040172896889386388789116535665831870264407049361593694626353869395281460757","seed":30040172896889386388789116535665831870264407049361593694626353869395281460757,"line":371,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log","log_context":["UVM_INFO @ 3165.206774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Offending '(rv_jtag_o == '0)'":[{"name":"chip_sw_rv_dm_access_after_escalation_reset","qual_name":"2.chip_sw_rv_dm_access_after_escalation_reset.18442561557072124160715753198158147102068075532544852895319225531036239923109","seed":18442561557072124160715753198158147102068075532544852895319225531036239923109,"line":387,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log","log_context":["UVM_ERROR @ 3036.712152 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A\n","UVM_INFO @ 3036.712152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.pinmux.mio_pad_sleep_mode_* reset value: *":[{"name":"chip_csr_mem_rw_with_rand_reset","qual_name":"3.chip_csr_mem_rw_with_rand_reset.7815433258321522023339832232848141911300581105969081721578189138403070737024","seed":7815433258321522023339832232848141911300581105969081721578189138403070737024,"line":296,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 4806.600584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got *":[{"name":"chip_sw_all_escalation_resets","qual_name":"21.chip_sw_all_escalation_resets.34162778549528900812223434192661904294042837917777100791560860223338349019906","seed":34162778549528900812223434192661904294042837917777100791560860223338349019906,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3014.636520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"96.chip_sw_all_escalation_resets.40047204399286878079635009950800108581762659792400391573708436682575045507203","seed":40047204399286878079635009950800108581762659792400391573708436682575045507203,"line":383,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/96.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3333.006825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault":[{"name":"chip_sw_all_escalation_resets","qual_name":"28.chip_sw_all_escalation_resets.62855488024399325779194428883626854165033974441546388948709386828642046646438","seed":62855488024399325779194428883626854165033974441546388948709386828642046646438,"line":375,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3465.241440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"59.chip_sw_all_escalation_resets.69765084418966615124505751529787336839952099279290393788631025517575286551583","seed":69765084418966615124505751529787336839952099279290393788631025517575286551583,"line":375,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/59.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 2658.789240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"chip_sw_all_escalation_resets","qual_name":"71.chip_sw_all_escalation_resets.101912159911030985519005206942625121113447615455317777105200553064235898833980","seed":101912159911030985519005206942625121113447615455317777105200553064235898833980,"line":375,"log_path":"/nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/71.chip_sw_all_escalation_resets/latest/run.log","log_context":["UVM_INFO @ 3355.808370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":1679,"total":1945,"percent":86.32390745501286}