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[`1e1dace`](https://github.com/lowrisc/opentitan/tree/1e1dace7680251f88ab11adedd8766222f333962)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-05T08:56:33Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":328.45,"sim_time":135213.094875,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.31,"sim_time":20.224016,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":2.9,"sim_time":439.13933299999997,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":23.66,"sim_time":3249.257563,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":1.92,"sim_time":96.30208900000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":3.6,"sim_time":2994.296264,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":2.9,"sim_time":439.13933299999997,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":1.92,"sim_time":96.30208900000001,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.94,"sim_time":29.311097,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.91,"sim_time":26.956477,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":40,"total":40,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.15,"sim_time":83.161534,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.06,"sim_time":5.010336000000001,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":1.02,"sim_time":3.349168,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":4.13,"sim_time":1796.6564099999998,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":4.13,"sim_time":1796.6564099999998,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":21.12,"sim_time":7433.750517,"passed":15,"total":15,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.35,"sim_time":207.40739000000002,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":38.9,"sim_time":9191.44534,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":13.68,"sim_time":20537.722368000002,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":39.98,"sim_time":25781.656236000003,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":39.98,"sim_time":25781.656236000003,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":24.4,"sim_time":2221.046914,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":24.4,"sim_time":2221.046914,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":24.4,"sim_time":2221.046914,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":24.4,"sim_time":2221.046914,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":24.4,"sim_time":2221.046914,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":32.33,"sim_time":35827.187482,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":59.5,"sim_time":24153.698994,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":59.5,"sim_time":24153.698994,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":59.5,"sim_time":24153.698994,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":37.67,"sim_time":4789.415179,"passed":15,"total":15,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":14.6,"sim_time":1507.757427,"passed":15,"total":15,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":59.5,"sim_time":24153.698994,"passed":15,"total":15,"percent":100.0},"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":39,"total":40,"percent":97.5},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":507.37,"sim_time":431988.039071,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":15.83,"sim_time":3518.1386230000003,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":15.83,"sim_time":3518.1386230000003,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"flash_mode_ignore_cmds":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":535.87,"sim_time":443435.313858,"passed":15,"total":15,"percent":100.0}},"passed":15,"total":15,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":328.45,"sim_time":135213.094875,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":625.48,"sim_time":347703.347964,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":10800.13962460123,"sim_time":0.0,"passed":14,"total":15,"percent":93.33333333333333}},"passed":14,"total":15,"percent":93.33333333333333},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.08,"sim_time":15.035183000000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.08,"sim_time":15.509072,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":6.34,"sim_time":945.658861,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":6.34,"sim_time":945.658861,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.31,"sim_time":20.224016,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.9,"sim_time":439.13933299999997,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":1.92,"sim_time":96.30208900000001,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.63,"sim_time":194.702526,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.31,"sim_time":20.224016,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.9,"sim_time":439.13933299999997,"passed":5,"total":5,"perce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(uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.55225824183256183935072583109125357984287752394408373859315316473233766796802","seed":55225824183256183935072583109125357984287752394408373859315316473233766796802,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3651543 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3651543 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[959])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.88893091843037629014095698339211331038935235280996138215927419748585483079192","seed":88893091843037629014095698339211331038935235280996138215927419748585483079192,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3119429 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3119429 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[966])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.8267517093512320068797089149532606649004566039178402449645882928613068652043","seed":8267517093512320068797089149532606649004566039178402449645882928613068652043,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    757427 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    757427 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[945])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.7212005638073558696507550760158436541176892125399956848683411754584864945308","seed":7212005638073558696507550760158436541176892125399956848683411754584864945308,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2534658 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2534658 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.112669583487947503458301684481782530012654986244126861856239875967704597373414","seed":112669583487947503458301684481782530012654986244126861856239875967704597373414,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3512707 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3512707 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.24427933061407272944397760326126002006197064422933878913032788764566203566964","seed":24427933061407272944397760326126002006197064422933878913032788764566203566964,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1115094 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1115094 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1001])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.48297783579419737491991084605989164128585249416661381256587940748592899851144","seed":48297783579419737491991084605989164128585249416661381256587940748592899851144,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    912000 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    912000 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[917])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.44115995945060499934169533602629796197484331998620256040078837699263399030149","seed":44115995945060499934169533602629796197484331998620256040078837699263399030149,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1042229 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1042229 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[959])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.113847715651204141179752034274847213138432801787415492936158140866753450184105","seed":113847715651204141179752034274847213138432801787415492936158140866753450184105,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4077151 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4077151 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[934])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.45997120281385262273964156396320312229495321604111231145814245754529037432537","seed":45997120281385262273964156396320312229495321604111231145814245754529037432537,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3775031 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3775031 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.46977300942771679732872530431563612751599726519961561167797050629299822807828","seed":46977300942771679732872530431563612751599726519961561167797050629299822807828,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3156638 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3156638 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[960])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.110916869282235811660137173232511544482182352550997977221500662998504283525890","seed":110916869282235811660137173232511544482182352550997977221500662998504283525890,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3276634 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3276634 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[924])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.103687834138302429978732413618283242389829228675424606216349053665373120459657","seed":103687834138302429978732413618283242389829228675424606216349053665373120459657,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1233617 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1233617 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[911])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.1338573559897920319023162335496252749110254273665103784994211878956279103509","seed":1338573559897920319023162335496252749110254273665103784994211878956279103509,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    952440 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    952440 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.74913214648271990222370009945900867277303459220424160184318487015571458705423","seed":74913214648271990222370009945900867277303459220424160184318487015571458705423,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4055781 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4055781 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[987])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.89633452709380840803962795069283437553144708162475347971138884406077711610791","seed":89633452709380840803962795069283437553144708162475347971138884406077711610791,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    984301 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    984301 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[937])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.105663183364836944133898452725840585757662098844386436591936940353750861430793","seed":105663183364836944133898452725840585757662098844386436591936940353750861430793,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    887535 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    887535 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[970])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.72647191936509020710669924938691912485358662667109667537358553572174616166034","seed":72647191936509020710669924938691912485358662667109667537358553572174616166034,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   7266352 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   7266352 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1000])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.61496191456819728232224145986055569118272249330919181532096605729839783134143","seed":61496191456819728232224145986055569118272249330919181532096605729839783134143,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1716463 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1716463 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[957])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.72724794180165772115586247654228644072555809221009308962659673550411343414650","seed":72724794180165772115586247654228644072555809221009308962659673550411343414650,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1094135 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1094135 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.9745227678863462368398467525487649739159901908107373726056609962706536053132","seed":9745227678863462368398467525487649739159901908107373726056609962706536053132,"line":76,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1196168 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x338 [1100111000] vs 0x0 [0]) \n","UVM_ERROR @   1250168 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x160 [101100000] vs 0x0 [0]) \n","UVM_ERROR @   1286168 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x36 [110110] vs 0x0 [0]) \n","UVM_ERROR @   1362168 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x71 [1110001] vs 0x0 [0]) \n"]}],"Job timed out after * minutes":[{"name":"spi_device_stress_all","qual_name":"14.spi_device_stress_all.99369913964215627160699880329683495518681469203166596477091152172511830521459","seed":99369913964215627160699880329683495518681469203166596477091152172511830521459,"line":null,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest/run.log","log_context":[]}],"UVM_ERROR (spi_device_scoreboard.sv:2513) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *":[{"name":"spi_device_flash_all","qual_name":"15.spi_device_flash_all.6095332399889890860066687288516368092984605701441484241481353069334824117631","seed":6095332399889890860066687288516368092984605701441484241481353069334824117631,"line":98,"log_path":"/nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest/run.log","log_context":["UVM_INFO @ 4955781748 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/14\n","UVM_INFO @ 4955781748 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 6/14\n","UVM_INFO @ 5505262748 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/14\n","UVM_INFO @ 5505262748 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 7/14\n"]}]}},"passed":393,"total":416,"percent":94.47115384615384}