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[`1e1dace`](https://github.com/lowrisc/opentitan/tree/1e1dace7680251f88ab11adedd8766222f333962)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-05T08:56:33Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":8.01,"sim_time":2110.332949,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":9.49,"sim_time":2479.1212400000004,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":9.46,"sim_time":2406.5486090000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":9.63,"sim_time":2316.442713,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.51,"sim_time":6091.021712000001,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.9,"sim_time":2033.2795730000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":33.33,"sim_time":71832.223581,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":8.21,"sim_time":2135.7136729999997,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":8.44,"sim_time":2079.036583,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":7.9,"sim_time":2033.2795730000003,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":8.21,"sim_time":2135.7136729999997,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":327.54,"sim_time":101662.95833499999,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":495.12000000000006,"sim_time":162893.344968,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":868.78,"sim_time":285196.611632,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":1405.1,"sim_time":488455.00353600003,"passed":35,"total":50,"percent":70.0}},"passed":35,"total":50,"percent":70.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":9.84,"sim_time":2512.152358,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.51,"sim_time":2035.6979509999999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":12.95,"sim_time":3742.058281,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":9.65,"sim_time":2612.8016150000003,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":9.66,"sim_time":4178.841898,"passed":3,"total":25,"percent":12.0}},"passed":3,"total":25,"percent":12.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":58.59,"sim_time":38437.005937,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":202.23,"sim_time":268038.727023,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.88,"sim_time":2012.8136359999996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":8.08,"sim_time":2013.6162,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.8,"sim_time":2149.972021,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_e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(cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_edge_detect","qual_name":"0.sysrst_ctrl_edge_detect.32582451012597799899664457478082374778909662928407868944442059529350737494775","seed":32582451012597799899664457478082374778909662928407868944442059529350737494775,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4999174045 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4999174045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"1.sysrst_ctrl_ultra_low_pwr.100277061935162485728308865578373394593479718308648157063317805165669184212563","seed":100277061935162485728308865578373394593479718308648157063317805165669184212563,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5614069687 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5614069687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"1.sysrst_ctrl_stress_all.8011547460940473093954605193690603791867898714505245599262572196644788659554","seed":8011547460940473093954605193690603791867898714505245599262572196644788659554,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 412299164159 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 412299164159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"3.sysrst_ctrl_stress_all.67711752742140442079047061054249546153165337083409630668990343212996689539997","seed":67711752742140442079047061054249546153165337083409630668990343212996689539997,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 5645501266 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5645501266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.61990969031017351486329651775714515168274998022426723657920940083894496434526","seed":61990969031017351486329651775714515168274998022426723657920940083894496434526,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3723185828 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3723185828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"5.sysrst_ctrl_ultra_low_pwr.82628995766021140890267654207577658583246063850920373961914242648218178153108","seed":82628995766021140890267654207577658583246063850920373961914242648218178153108,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 266270488689 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 266270488689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"6.sysrst_ctrl_ultra_low_pwr.19080547599565164759104868479753171970269258297018890286991255871735534076470","seed":19080547599565164759104868479753171970269258297018890286991255871735534076470,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4138028482 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4138028482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"6.sysrst_ctrl_edge_detect.27075928732319531125581334111553276847476006399192195081967742003998477224968","seed":27075928732319531125581334111553276847476006399192195081967742003998477224968,"line":672,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3883852920 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3883852920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"6.sysrst_ctrl_stress_all.54407346156065168512381950338571007275649121019402853312378547773188234393357","seed":54407346156065168512381950338571007275649121019402853312378547773188234393357,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 9018291295 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 9018291295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"7.sysrst_ctrl_ultra_low_pwr.35407969043020998001877963563043722596007430874773011845682588058790923978006","seed":35407969043020998001877963563043722596007430874773011845682588058790923978006,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5524903921 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5524903921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"8.sysrst_ctrl_ultra_low_pwr.87378228485590402947791243669496484955763575623837601278835973940526020543920","seed":87378228485590402947791243669496484955763575623837601278835973940526020543920,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3064689493 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3064689493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"9.sysrst_ctrl_ultra_low_pwr.7044909884861454891555702865011183704637498962640624757394919538759488617594","seed":7044909884861454891555702865011183704637498962640624757394919538759488617594,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4155958805 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4155958805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"10.sysrst_ctrl_ultra_low_pwr.48740347367190983154354296543912430397611631930470251561985456804149868291557","seed":48740347367190983154354296543912430397611631930470251561985456804149868291557,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 6056743184 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 6056743184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"10.sysrst_ctrl_edge_detect.85541705264937237826806910494980607387883027795149972782788351257330758894974","seed":85541705264937237826806910494980607387883027795149972782788351257330758894974,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 265809634547 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 265809634547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"12.sysrst_ctrl_ultra_low_pwr.102659366837520339583703099843103957877180780613055918008785103536518833098943","seed":102659366837520339583703099843103957877180780613055918008785103536518833098943,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2563512569 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2563512569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"13.sysrst_ctrl_ultra_low_pwr.42254838955560131804347382851312087357561376580032741159629878110992696418360","seed":42254838955560131804347382851312087357561376580032741159629878110992696418360,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3258970547 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3258970547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"13.sysrst_ctrl_edge_detect.30361399244993440118335382748388567427777719957409100482178645949980156805168","seed":30361399244993440118335382748388567427777719957409100482178645949980156805168,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4198397723 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4198397723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"15.sysrst_ctrl_ultra_low_pwr.89952938158438436271940688915042834829194292028577802290938544929171518085332","seed":89952938158438436271940688915042834829194292028577802290938544929171518085332,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4178841898 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4178841898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"17.sysrst_ctrl_ultra_low_pwr.70659865493825253538227022661972958199930678993621370411968828592852217568808","seed":70659865493825253538227022661972958199930678993621370411968828592852217568808,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3814114527 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3814114527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"17.sysrst_ctrl_edge_detect.94717998844818656839401411346594756632840204093123954053745470639911205315766","seed":94717998844818656839401411346594756632840204093123954053745470639911205315766,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2663548477 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2663548477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"18.sysrst_ctrl_ultra_low_pwr.59731471718554932378607835148779375357183995136143891485266558886583131557086","seed":59731471718554932378607835148779375357183995136143891485266558886583131557086,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2648466814 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2648466814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"19.sysrst_ctrl_ultra_low_pwr.86461458535723202448131981540909338876302106051610270628423187178992033734837","seed":86461458535723202448131981540909338876302106051610270628423187178992033734837,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4925031809 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4925031809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"20.sysrst_ctrl_ultra_low_pwr.33736022459297062906664884001419859492997112454294127475417430078661104813472","seed":33736022459297062906664884001419859492997112454294127475417430078661104813472,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3820993440 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3820993440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"20.sysrst_ctrl_edge_detect.108937870653259482042675704159235815758123182538671673796056006738787170994504","seed":108937870653259482042675704159235815758123182538671673796056006738787170994504,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2335239159 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2335239159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"21.sysrst_ctrl_ultra_low_pwr.109974311830138032542902900784701069080244311343831174985256198357945080497951","seed":109974311830138032542902900784701069080244311343831174985256198357945080497951,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2698052326 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2698052326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"21.sysrst_ctrl_edge_detect.104920726710560339265102861249610448032581968911161150880758387904930574210173","seed":104920726710560339265102861249610448032581968911161150880758387904930574210173,"line":664,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2645326386 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2645326386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"22.sysrst_ctrl_ultra_low_pwr.105649609462106364794109580537450693977051440236938233051108741841155216369605","seed":105649609462106364794109580537450693977051440236938233051108741841155216369605,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5872719587 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5872719587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"23.sysrst_ctrl_ultra_low_pwr.98236865226091304246185922000537146675814055522638410179049391364858837452976","seed":98236865226091304246185922000537146675814055522638410179049391364858837452976,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3851836426 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3851836426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"29.sysrst_ctrl_edge_detect.41060744140143936065453655162404328776581332706821025417316670038955718679142","seed":41060744140143936065453655162404328776581332706821025417316670038955718679142,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 138128219871 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 138128219871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"33.sysrst_ctrl_edge_detect.54391393258631163142016366793010917758172138674577813382010958773793528602469","seed":54391393258631163142016366793010917758172138674577813382010958773793528602469,"line":680,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 5526527164 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5526527164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"38.sysrst_ctrl_edge_detect.11617486005191188827822626016449787673527844347562142526672248863821701014770","seed":11617486005191188827822626016449787673527844347562142526672248863821701014770,"line":664,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3069363184 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3069363184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"39.sysrst_ctrl_edge_detect.81183260325530306364253026585726554170651476883209205023604245095094859976471","seed":81183260325530306364253026585726554170651476883209205023604245095094859976471,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2937590438 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2937590438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"40.sysrst_ctrl_edge_detect.42560717685675680812918536464975786104113782804976370352268313961590457017113","seed":42560717685675680812918536464975786104113782804976370352268313961590457017113,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3074097551 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3074097551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"41.sysrst_ctrl_edge_detect.581730297219438152698480232382277147832085592838008347326233075196969661193","seed":581730297219438152698480232382277147832085592838008347326233075196969661193,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2681572658 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2681572658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"46.sysrst_ctrl_edge_detect.105115143482377232557004398086173624229526235993419897788963767382541630254631","seed":105115143482377232557004398086173624229526235993419897788963767382541630254631,"line":665,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2964499685 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2964499685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"48.sysrst_ctrl_edge_detect.14731142382791991226063242948324260474138309145801587099817947889345059183157","seed":14731142382791991226063242948324260474138309145801587099817947889345059183157,"line":689,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4918032644 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4918032644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"2.sysrst_ctrl_ultra_low_pwr.91752229307290806166242877928392306823005121395745297924108989745178630296941","seed":91752229307290806166242877928392306823005121395745297924108989745178630296941,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3495062437 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 3495062437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"14.sysrst_ctrl_ultra_low_pwr.8181370712855311177104511487951858159707567587825220564136786161593766119702","seed":8181370712855311177104511487951858159707567587825220564136786161593766119702,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4711410920 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 4711410920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"16.sysrst_ctrl_ultra_low_pwr.46585807814141784990537542869954186664244920624458726450386154588806731852552","seed":46585807814141784990537542869954186664244920624458726450386154588806731852552,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2571181381 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_ERROR @ 4156507905 ps: (cip_base_scoreboard.sv:256) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 4156507905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"24.sysrst_ctrl_ultra_low_pwr.49965418780260804690756435423444891885277038158681197015287858286677859773990","seed":49965418780260804690756435423444891885277038158681197015287858286677859773990,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5171831101 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 5171831101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.":[{"name":"sysrst_ctrl_sec_cm","qual_name":"4.sysrst_ctrl_sec_cm.101758565308565091446532746165878228578563133981516967259914911279128592135708","seed":101758565308565091446532746165878228578563133981516967259914911279128592135708,"line":698,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest/run.log","log_context":["UVM_INFO @ 23999423415 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 12/20\n","UVM_INFO @ 23999428415 ps: (prim_onehot_check_if.sv:103) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\\prim_onehot_check_if_proxy::inject_fault ] onehot_fault_type: OnehotFault\n","UVM_INFO @ 23999428415 ps: (prim_onehot_check_if.sv:107) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\\prim_onehot_check_if_proxy::inject_fault ] Forcing tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i from 0 to 0, tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i from 0 to 2708138614799 and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i from 0 to 27\n","UVM_INFO @ 25999423415 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 13/20\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"28.sysrst_ctrl_combo_detect_with_pre_cond.58656971322771614992128436181524423510539038902878141395614699937947609925424","seed":58656971322771614992128436181524423510539038902878141395614699937947609925424,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13525283380 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 13525283380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"79.sysrst_ctrl_combo_detect_with_pre_cond.3790906758820066697813473797120420559225453840209120709511087186870397272114","seed":3790906758820066697813473797120420559225453840209120709511087186870397272114,"line":676,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 25523467449 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 25523467449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"51.sysrst_ctrl_combo_detect_with_pre_cond.26534425866309048413938235928183273779734331426796421720406144363447688415029","seed":26534425866309048413938235928183273779734331426796421720406144363447688415029,"line":674,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 14250981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0\n","UVM_INFO @ 14480981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 14500981454 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 24578585063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x32\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"65.sysrst_ctrl_combo_detect_with_pre_cond.69284831679855084967502457038553854415036351405498189240354085472412092868064","seed":69284831679855084967502457038553854415036351405498189240354085472412092868064,"line":680,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 34034015893 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 \n","UVM_INFO @ 34034015893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"70.sysrst_ctrl_combo_detect_with_pre_cond.115317855514493296735780516075915901010771951270892442002556220728104801955763","seed":115317855514493296735780516075915901010771951270892442002556220728104801955763,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13050096539 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 \n","UVM_INFO @ 13050096539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"69.sysrst_ctrl_combo_detect_with_pre_cond.33569831947270182209338661130902385397209016417943627296274573422822310842841","seed":33569831947270182209338661130902385397209016417943627296274573422822310842841,"line":674,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 15744980630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 15764980630 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 25975636076 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d\n","UVM_INFO @ 25975667327 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2b\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"84.sysrst_ctrl_combo_detect_with_pre_cond.9272741925791678457991698026853635653744912516438878350278969268599047593155","seed":9272741925791678457991698026853635653744912516438878350278969268599047593155,"line":683,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 32673186821 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8]) \n","UVM_INFO @ 32673186821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"95.sysrst_ctrl_combo_detect_with_pre_cond.40276828212474452176558291546456420188369565279862006254849854519392596908033","seed":40276828212474452176558291546456420188369565279862006254849854519392596908033,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 15073123644 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4 \n","UVM_INFO @ 15073123644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":361,"total":410,"percent":88.04878048780488}