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(cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"0.sysrst_ctrl_ultra_low_pwr.15005637766197199742413112200772022032219806673021378067661823664565182688852","seed":15005637766197199742413112200772022032219806673021378067661823664565182688852,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3730808050 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3730808050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"1.sysrst_ctrl_ultra_low_pwr.30257771214700025303421380502009632969783902907686726176151317757729240551816","seed":30257771214700025303421380502009632969783902907686726176151317757729240551816,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 1162104487236 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 1162104487236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"1.sysrst_ctrl_edge_detect.78662381835332111156200677893065948747823019998765560202639728316100986022687","seed":78662381835332111156200677893065948747823019998765560202639728316100986022687,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 131673663811 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 131673663811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"1.sysrst_ctrl_stress_all.94478845390830475750403863291665976713380700063663306121995346201090216409001","seed":94478845390830475750403863291665976713380700063663306121995346201090216409001,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 8133375192 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 8133375192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"2.sysrst_ctrl_ultra_low_pwr.68149762026419746348963533145880934435680289847233388167419170162154046997023","seed":68149762026419746348963533145880934435680289847233388167419170162154046997023,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 288173902733 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 288173902733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"3.sysrst_ctrl_ultra_low_pwr.42417986140519104555705066927443081697385875764388732410482293757583086717200","seed":42417986140519104555705066927443081697385875764388732410482293757583086717200,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5786733252 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5786733252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.74943604858940895907411191044390584074963312913235177324656051699409590262537","seed":74943604858940895907411191044390584074963312913235177324656051699409590262537,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4451401434 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4451401434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"4.sysrst_ctrl_edge_detect.110931227661585915387970070251974948690885418480633890601473929493992159338769","seed":110931227661585915387970070251974948690885418480633890601473929493992159338769,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 274686292268 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 274686292268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"4.sysrst_ctrl_stress_all.23979042933360754776917906374497442155935461680600275358501903824743542590047","seed":23979042933360754776917906374497442155935461680600275358501903824743542590047,"line":717,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 171186451581 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 171186451581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"5.sysrst_ctrl_ultra_low_pwr.104385044766451131848422077698120554324798576794621747966358497207642186358809","seed":104385044766451131848422077698120554324798576794621747966358497207642186358809,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3522801640 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3522801640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"5.sysrst_ctrl_stress_all.54391860415239498090413231539231826025997780031494518530851496915294642292620","seed":54391860415239498090413231539231826025997780031494518530851496915294642292620,"line":673,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 13324492736 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 13324492736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"6.sysrst_ctrl_ultra_low_pwr.57177025926103128284281888640521999008065259866931660780337228498244789872317","seed":57177025926103128284281888640521999008065259866931660780337228498244789872317,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4688632927 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4688632927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"6.sysrst_ctrl_edge_detect.41699183619248441618205835028402888396620221422907647137115840255939672808779","seed":41699183619248441618205835028402888396620221422907647137115840255939672808779,"line":665,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2336189236 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2336189236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"7.sysrst_ctrl_ultra_low_pwr.17098999072689831801190262885988115987677468989465488482737440053433292752861","seed":17098999072689831801190262885988115987677468989465488482737440053433292752861,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5945248516 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5945248516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"8.sysrst_ctrl_ultra_low_pwr.50715360720793578104338862510345197692881967769582782111593636965490521750518","seed":50715360720793578104338862510345197692881967769582782111593636965490521750518,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 1535340178482 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 1535340178482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"8.sysrst_ctrl_edge_detect.63174577431875594004245840159678810311643738971381373524756000325410025278504","seed":63174577431875594004245840159678810311643738971381373524756000325410025278504,"line":688,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4626640721 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4626640721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_stress_all","qual_name":"8.sysrst_ctrl_stress_all.113440564619625765140571928204438237170254370314818163872815552429368912682642","seed":113440564619625765140571928204438237170254370314818163872815552429368912682642,"line":721,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest/run.log","log_context":["UVM_ERROR @ 186824325782 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 186824325782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"10.sysrst_ctrl_edge_detect.19628769098319593105920259212092045329197590172090716754213773620015643583026","seed":19628769098319593105920259212092045329197590172090716754213773620015643583026,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2258705210 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2258705210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"11.sysrst_ctrl_ultra_low_pwr.22635832571989592373771338319385340108790408004687258917313113715643303669698","seed":22635832571989592373771338319385340108790408004687258917313113715643303669698,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 1614148896230 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 1614148896230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"12.sysrst_ctrl_ultra_low_pwr.76949745375203313131877562126137788367090453887455341506362049520155953525931","seed":76949745375203313131877562126137788367090453887455341506362049520155953525931,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 63329781834 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 63329781834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"12.sysrst_ctrl_edge_detect.74999537861084749353909148568672987998732646000995572285376088931967951563129","seed":74999537861084749353909148568672987998732646000995572285376088931967951563129,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 294174533772 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 294174533772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"13.sysrst_ctrl_ultra_low_pwr.7099900256153694835477891131043135635858897297827496213749108190307878483209","seed":7099900256153694835477891131043135635858897297827496213749108190307878483209,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2631393791 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2631393791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"15.sysrst_ctrl_ultra_low_pwr.64925670554555677882635562597706396182820855885202285248804799108736290274542","seed":64925670554555677882635562597706396182820855885202285248804799108736290274542,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5598822169 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5598822169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"15.sysrst_ctrl_edge_detect.38676946421059384411010200161831801326436396515708215224634140984255822144707","seed":38676946421059384411010200161831801326436396515708215224634140984255822144707,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2345144286 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2345144286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"16.sysrst_ctrl_ultra_low_pwr.106070350675377282079915955272285943733639073851097941165633682020631540760620","seed":106070350675377282079915955272285943733639073851097941165633682020631540760620,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 2824071179 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2824071179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"16.sysrst_ctrl_edge_detect.108827100267568333892031439815962718580612609908431986127661848609382791649436","seed":108827100267568333892031439815962718580612609908431986127661848609382791649436,"line":664,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2572071390 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2572071390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"18.sysrst_ctrl_ultra_low_pwr.33116314298786964030373952387297282255667543378982407217552077991147205569691","seed":33116314298786964030373952387297282255667543378982407217552077991147205569691,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4023420460 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4023420460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"19.sysrst_ctrl_ultra_low_pwr.31727339478168919019019685376441157276950729995482547952756942232030824573367","seed":31727339478168919019019685376441157276950729995482547952756942232030824573367,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4083075941 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4083075941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"20.sysrst_ctrl_ultra_low_pwr.53638284432424223296927123342828688149465107017910165561988562183160674062846","seed":53638284432424223296927123342828688149465107017910165561988562183160674062846,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3222409582 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3222409582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"21.sysrst_ctrl_ultra_low_pwr.41119709332012749242252345502337136334737853561538122755185592434863248868257","seed":41119709332012749242252345502337136334737853561538122755185592434863248868257,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3948445185 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3948445185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"21.sysrst_ctrl_edge_detect.7285071804432871682577032084111873904641045213602207237706715011432087116862","seed":7285071804432871682577032084111873904641045213602207237706715011432087116862,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2696595972 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2696595972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"22.sysrst_ctrl_ultra_low_pwr.50483613960674380185346038703237166498373912635216500977647910654283948019615","seed":50483613960674380185346038703237166498373912635216500977647910654283948019615,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3269782246 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3269782246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"22.sysrst_ctrl_edge_detect.50492911405450378603484715816765782753437025105357966907780134050194745520587","seed":50492911405450378603484715816765782753437025105357966907780134050194745520587,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 3322070800 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 3322070800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"23.sysrst_ctrl_edge_detect.17251174408436458693090722133478896171291823822031215595993281831705359893437","seed":17251174408436458693090722133478896171291823822031215595993281831705359893437,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2819591865 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2819591865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"24.sysrst_ctrl_ultra_low_pwr.101940285372725851137068758963904559274564762438867015936619438650268656178896","seed":101940285372725851137068758963904559274564762438867015936619438650268656178896,"line":662,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5976194893 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5976194893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"24.sysrst_ctrl_edge_detect.108603809085300442332707130991222934229084084679055104106334415569590076131047","seed":108603809085300442332707130991222934229084084679055104106334415569590076131047,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2324982895 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2324982895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"30.sysrst_ctrl_edge_detect.15417780123815808765240436584797129575403672844259524276665522288877219484448","seed":15417780123815808765240436584797129575403672844259524276665522288877219484448,"line":663,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2663280859 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2663280859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"36.sysrst_ctrl_edge_detect.66748375452741723809698213151371616554373930182051782864753687297414235160526","seed":66748375452741723809698213151371616554373930182051782864753687297414235160526,"line":670,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 600418349338 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 600418349338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"37.sysrst_ctrl_edge_detect.23808147541175805271462678004763137158862009828750056370205714210123307003848","seed":23808147541175805271462678004763137158862009828750056370205714210123307003848,"line":669,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 480958401126 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 480958401126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"39.sysrst_ctrl_edge_detect.56054766897013111891187798274146597290277597163118038861730071544486173048391","seed":56054766897013111891187798274146597290277597163118038861730071544486173048391,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 4306882015 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4306882015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"40.sysrst_ctrl_edge_detect.111805841421237860555410381811988552183824769491582198143124293114188017281748","seed":111805841421237860555410381811988552183824769491582198143124293114188017281748,"line":666,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2259534598 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2259534598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"41.sysrst_ctrl_edge_detect.95974723421194769030165930193193875899247643061188528414027745005341184872345","seed":95974723421194769030165930193193875899247643061188528414027745005341184872345,"line":664,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2923942505 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2923942505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"47.sysrst_ctrl_edge_detect.78088946775088963692845008662094436827604900308390693834728084909568012357046","seed":78088946775088963692845008662094436827604900308390693834728084909568012357046,"line":668,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2756950217 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2756950217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"48.sysrst_ctrl_edge_detect.78924000111034408677382562797089456849061858154578269926241480100634973762176","seed":78924000111034408677382562797089456849061858154578269926241480100634973762176,"line":667,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2417704579 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2417704579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"0.sysrst_ctrl_combo_detect_with_pre_cond.25257956779307126912308220400244319652280063932414020619496289903913794477716","seed":25257956779307126912308220400244319652280063932414020619496289903913794477716,"line":677,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 27066444300 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-4 \n","UVM_INFO @ 27066444300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"2.sysrst_ctrl_combo_detect_with_pre_cond.39344087478222057957707812497988456734936953266486238856812635536491234288322","seed":39344087478222057957707812497988456734936953266486238856812635536491234288322,"line":691,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 44131634522 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 44131634522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"60.sysrst_ctrl_combo_detect_with_pre_cond.85918652035473376040345216856806971107163768372632750963145836099116569716181","seed":85918652035473376040345216856806971107163768372632750963145836099116569716181,"line":711,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 64623594221 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d\n","UVM_INFO @ 64623656720 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25\n","UVM_INFO @ 65127288163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 65127288163 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"9.sysrst_ctrl_ultra_low_pwr.68834280606330269372894116813879474897137432185331074617154088860485984276027","seed":68834280606330269372894116813879474897137432185331074617154088860485984276027,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2364611692 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_ERROR @ 3865262049 ps: (cip_base_scoreboard.sv:256) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error\n","UVM_INFO @ 3865262049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.":[{"name":"sysrst_ctrl_tl_intg_err","qual_name":"11.sysrst_ctrl_tl_intg_err.82117303213284967128409741172737254722551988227390399033053348938574624318682","seed":82117303213284967128409741172737254722551988227390399033053348938574624318682,"line":672,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 6040453421 ps: (cip_base_vseq__tl_errors.svh:409) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_intg_err_vseq 3/10\n","UVM_INFO @ 6060547555 ps: (cip_tl_seq_item.sv:117) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:\n","\t a_addr: 0x445cd074\n"," -> 0x444c5074\t a_opcode: 0x4\n"]},{"name":"sysrst_ctrl_tl_intg_err","qual_name":"21.sysrst_ctrl_tl_intg_err.42170614417079185698336583758367066423713537791425873511972586931655959489046","seed":42170614417079185698336583758367066423713537791425873511972586931655959489046,"line":731,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 18334686619 ps: (cip_base_vseq__tl_errors.svh:409) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_intg_err_vseq 9/10\n","UVM_INFO @ 18348020059 ps: (cip_tl_seq_item.sv:132) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below:\n","\t a_data: 0x381937a6\n"," -> 0xb89937a6\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"61.sysrst_ctrl_combo_detect_with_pre_cond.62242387952283516978584788923426388520495820828752879494453730376218980103984","seed":62242387952283516978584788923426388520495820828752879494453730376218980103984,"line":732,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 63382284687 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 63402284687 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 73538563854 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31\n","UVM_INFO @ 73538625078 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x17\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"90.sysrst_ctrl_combo_detect_with_pre_cond.98897853887759673811526702300821353632589289547096820984004626880775403766052","seed":98897853887759673811526702300821353632589289547096820984004626880775403766052,"line":716,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 69457619512 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 69477619512 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 79539611856 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a\n","UVM_INFO @ 79539753270 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32\n"]}]}},"passed":358,"total":410,"percent":87.3170731707317}