{"block":{"name":"sysrst_ctrl","variant":null,"commit":"66cdfd3b2ea9ec890f6607a4d4809562fc70f272","commit_short":"66cdfd3","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/66cdfd3b2ea9ec890f6607a4d4809562fc70f272","revision_info":"GitHub Revision: [`66cdfd3`](https://github.com/lowrisc/opentitan/tree/66cdfd3b2ea9ec890f6607a4d4809562fc70f272)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-19T01:30:47Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":7.02,"sim_time":2109.126158,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":9.53,"sim_time":2474.0183119999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":8.28,"sim_time":2420.119611,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":5.18,"sim_time":2551.8412080000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.81,"sim_time":4053.1631060000004,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.64,"sim_time":2037.632253,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":55.73,"sim_time":76273.067597,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":7.15,"sim_time":2103.894131,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":9.13,"sim_time":2088.769888,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":8.64,"sim_time":2037.632253,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":7.15,"sim_time":2103.894131,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":427.25,"sim_time":187477.561984,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":378.14,"sim_time":151400.369266,"passed":93,"total":100,"percent":93.0}},"passed":93,"total":100,"percent":93.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":453.62,"sim_time":228270.173539,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":578.14,"sim_time":537094.188817,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":9.05,"sim_time":2510.4645210000003,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.96,"sim_time":2137.883442,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":751.97,"sim_time":702421.547898,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":8.94,"sim_time":2610.1671189999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":20.2,"sim_time":78529.88035699999,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":93.2,"sim_time":35790.586291,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":248.88,"sim_time":72169.34427599999,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.35,"sim_time":2013.540694,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":7.93,"sim_time":2011.9252839999997,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.61,"sim_time":2042.5715370000003,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":9.61,"sim_time":2042.5715370000003,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.81,"sim_time":4053.1631060000004,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.64,"sim_time":2037.632253,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":7.15,"sim_time":2103.894131,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":31.52,"sim_time":8177.604442,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":4.81,"sim_time":4053.1631060000004,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":8.64,"sim_time":2037.632253,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":7.15,"sim_time":2103.894131,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":31.52,"sim_time":8177.604442,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":325,"total":334,"percent":97.30538922155688},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":92.58,"sim_time":42011.304651,"passed":4,"total":5,"percent":80.0},"sysrst_ctrl_tl_intg_err":{"max_time":115.49,"sim_time":42480.762301,"passed":24,"total":25,"percent":96.0}},"passed":28,"total":30,"percent":93.33333333333333},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":115.49,"sim_time":42480.762301,"passed":24,"total":25,"percent":96.0}},"passed":24,"total":25,"percent":96.0}},"passed":28,"total":30,"percent":93.33333333333333},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":20.08,"sim_time":6064.414317,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.5,"branch":99.59,"condition_expression":97.63,"toggle":100.0,"fsm":96.15},"assertion":98.96,"functional":86.85},"cov_report_page":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.":[{"name":"sysrst_ctrl_sec_cm","qual_name":"0.sysrst_ctrl_sec_cm.11066575364625768941005445679495239283363651111666100459237756258371670549775","seed":11066575364625768941005445679495239283363651111666100459237756258371670549775,"line":671,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest/run.log","log_context":["UVM_INFO @ 8001724651 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 4/20\n","UVM_INFO @ 8001729651 ps: (prim_onehot_check_if.sv:103) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\\prim_onehot_check_if_proxy::inject_fault ] onehot_fault_type: OnehotEnableFault\n","UVM_INFO @ 8001729651 ps: (prim_onehot_check_if.sv:107) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\\prim_onehot_check_if_proxy::inject_fault ] Forcing tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i from 0 to 0, tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i from 0 to 2097152 and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i from 0 to 1\n","UVM_INFO @ 8001739651 ps: (prim_onehot_check_if.sv:124) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\\prim_onehot_check_if_proxy::restore_fault ] Restoring original value of tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i (0), tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i (0) and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i (0)\n"]},{"name":"sysrst_ctrl_tl_intg_err","qual_name":"14.sysrst_ctrl_tl_intg_err.18260327183356638761437766555983023078898820275600703526325891542771905076204","seed":18260327183356638761437766555983023078898820275600703526325891542771905076204,"line":824,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest/run.log","log_context":["UVM_INFO @ 42508592994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"5.sysrst_ctrl_ultra_low_pwr.4435149198056572177236087645212072746184822463141912174149674109105718447351","seed":4435149198056572177236087645212072746184822463141912174149674109105718447351,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_INFO @ 2436878834 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i\n","UVM_INFO @ 7641878834 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check\n","UVM_INFO @ 7655245971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n"]}],"UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *":[{"name":"sysrst_ctrl_ec_pwr_on_rst","qual_name":"6.sysrst_ctrl_ec_pwr_on_rst.56077792150881796775046021569877347625758826625165068235297267516153897688499","seed":56077792150881796775046021569877347625758826625165068235297267516153897688499,"line":661,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest/run.log","log_context":["UVM_INFO @ 2945416039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"32.sysrst_ctrl_combo_detect_with_pre_cond.55923367003107363612042538520411966127008372597103271879185670282867170181272","seed":55923367003107363612042538520411966127008372597103271879185670282867170181272,"line":721,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 61610170203 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 61610170203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"74.sysrst_ctrl_combo_detect_with_pre_cond.74033244904905711255443405972652931106736505211220479367736380175563152416159","seed":74033244904905711255443405972652931106736505211220479367736380175563152416159,"line":684,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 25466411861 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 25466411861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"34.sysrst_ctrl_combo_detect_with_pre_cond.55537908126320061971201736256588263487786206892173011483516605627516785518899","seed":55537908126320061971201736256588263487786206892173011483516605627516785518899,"line":679,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 30140534810 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xc9\n","UVM_INFO @ 30140631584 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29\n","UVM_INFO @ 30543520880 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 30543520880 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"46.sysrst_ctrl_combo_detect_with_pre_cond.42638891743460042575196984899943584381433831669416789120107180773078837963125","seed":42638891743460042575196984899943584381433831669416789120107180773078837963125,"line":672,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 14106686778 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4 \n","UVM_INFO @ 14106686778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:111) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_l2h_expected == *) Unexpected L2H transition of ec_rst_l_o":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"67.sysrst_ctrl_combo_detect_with_pre_cond.111053630075949352573839928942489482303760529884218004840189565049434064307931","seed":111053630075949352573839928942489482303760529884218004840189565049434064307931,"line":771,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 97439092723 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 97459092723 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 107521703463 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19\n","UVM_INFO @ 107521828464 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xd\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"70.sysrst_ctrl_combo_detect_with_pre_cond.5008799035346167634083805378719259619362043624551158444897356766251428553559","seed":5008799035346167634083805378719259619362043624551158444897356766251428553559,"line":679,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 14732527548 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o \n","UVM_INFO @ 14732527548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"99.sysrst_ctrl_combo_detect_with_pre_cond.57659488346412832175524036244059032713054801172949111386458627197378629977967","seed":57659488346412832175524036244059032713054801172949111386458627197378629977967,"line":675,"log_path":"/nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13176513386 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4 \n","UVM_INFO @ 13176513386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":399,"total":410,"percent":97.3170731707317}