{"block":{"name":"uart","variant":null,"commit":"66cdfd3b2ea9ec890f6607a4d4809562fc70f272","commit_short":"66cdfd3","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/66cdfd3b2ea9ec890f6607a4d4809562fc70f272","revision_info":"GitHub Revision: [`66cdfd3`](https://github.com/lowrisc/opentitan/tree/66cdfd3b2ea9ec890f6607a4d4809562fc70f272)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-19T01:30:47Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/uart/data/uart_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"uart_smoke":{"max_time":42.33,"sim_time":11095.037567,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"uart_csr_hw_reset":{"max_time":0.9,"sim_time":16.057443,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"uart_csr_rw":{"max_time":0.92,"sim_time":77.697234,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"uart_csr_bit_bash":{"max_time":2.57,"sim_time":1465.149126,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"uart_csr_aliasing":{"max_time":0.92,"sim_time":27.119529,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"uart_csr_mem_rw_with_rand_reset":{"max_time":1.33,"sim_time":80.439401,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"uart_csr_rw":{"max_time":0.92,"sim_time":77.697234,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":0.92,"sim_time":27.119529,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":23,"total":23,"percent":100.0},"V2":{"testpoints":{"base_random_seq":{"tests":{"uart_tx_rx":{"max_time":125.81000000000002,"sim_time":71296.54370200001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"parity":{"tests":{"uart_smoke":{"max_time":42.33,"sim_time":11095.037567,"passed":10,"total":10,"percent":100.0},"uart_tx_rx":{"max_time":125.81000000000002,"sim_time":71296.54370200001,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"parity_error":{"tests":{"uart_intr":{"max_time":70.39,"sim_time":54320.042137000004,"passed":10,"total":10,"percent":100.0},"uart_rx_parity_err":{"max_time":77.36,"sim_time":53357.167329,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"watermark":{"tests":{"uart_tx_rx":{"max_time":125.81000000000002,"sim_time":71296.54370200001,"passed":10,"total":10,"percent":100.0},"uart_intr":{"max_time":70.39,"sim_time":54320.042137000004,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"fifo_full":{"tests":{"uart_fifo_full":{"max_time":222.44,"sim_time":134561.544667,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_overflow":{"tests":{"uart_fifo_overflow":{"max_time":130.13,"sim_time":114146.56276,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"fifo_reset":{"tests":{"uart_fifo_reset":{"max_time":411.42,"sim_time":118793.25755,"passed":200,"total":200,"percent":100.0}},"passed":200,"total":200,"percent":100.0},"rx_frame_err":{"tests":{"uart_intr":{"max_time":70.39,"sim_time":54320.042137000004,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_break_err":{"tests":{"uart_intr":{"max_time":70.39,"sim_time":54320.042137000004,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_timeout":{"tests":{"uart_intr":{"max_time":70.39,"sim_time":54320.042137000004,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"perf":{"tests":{"uart_perf":{"max_time":471.84,"sim_time":18488.637345,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sys_loopback":{"tests":{"uart_loopback":{"max_time":15.93,"sim_time":6764.187592,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"line_loopback":{"tests":{"uart_loopback":{"max_time":15.93,"sim_time":6764.187592,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_noise_filter":{"tests":{"uart_noise_filter":{"max_time":84.1,"sim_time":61189.80005699999,"passed":0,"total":10,"percent":0.0}},"passed":0,"total":10,"percent":0.0},"rx_start_bit_filter":{"tests":{"uart_rx_start_bit_filter":{"max_time":63.31000000000001,"sim_time":36473.251845,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tx_overide":{"tests":{"uart_tx_ovrd":{"max_time":21.7,"sim_time":12423.040036,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"rx_oversample":{"tests":{"uart_rx_oversample":{"max_time":46.85,"sim_time":7073.02464,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"long_b2b_transfer":{"tests":{"uart_long_xfer_wo_dly":{"max_time":1120.49,"sim_time":183097.58209799998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"uart_stress_all":{"max_time":805.39,"sim_time":252277.495782,"passed":9,"total":10,"percent":90.0}},"passed":9,"total":10,"percent":90.0},"alert_test":{"tests":{"uart_alert_test":{"max_time":0.89,"sim_time":20.233364,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"uart_intr_test":{"max_time":0.92,"sim_time":17.696663,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"uart_tl_errors":{"max_time":2.84,"sim_time":169.210378,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"uart_tl_errors":{"max_time":2.84,"sim_time":169.210378,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.9,"sim_time":16.057443,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.92,"sim_time":77.697234,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":0.92,"sim_time":27.119529,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.07,"sim_time":54.363316,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"uart_csr_hw_reset":{"max_time":0.9,"sim_time":16.057443,"passed":1,"total":1,"percent":100.0},"uart_csr_rw":{"max_time":0.92,"sim_time":77.697234,"passed":5,"total":5,"percent":100.0},"uart_csr_aliasing":{"max_time":0.92,"sim_time":27.119529,"passed":1,"total":1,"percent":100.0},"uart_same_csr_outstanding":{"max_time":1.07,"sim_time":54.363316,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":386,"total":397,"percent":97.22921914357683},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"uart_sec_cm":{"max_time":1.2,"sim_time":130.617363,"passed":5,"total":5,"percent":100.0},"uart_tl_intg_err":{"max_time":1.85,"sim_time":269.164567,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"uart_tl_intg_err":{"max_time":1.85,"sim_time":269.164567,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"uart_stress_all_with_rand_reset":{"max_time":70.01,"sim_time":9114.556378000001,"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"passed":17,"total":20,"percent":85.0}},"coverage":{"code":{"block":null,"line_statement":99.48,"branch":98.14,"condition_expression":98.25,"toggle":74.67,"fsm":null},"assertion":98.85,"functional":99.23},"cov_report_page":"/nightly/current_run/scratch/master/uart-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.32207725007555051749651128309644669433959282602726542687296883223995079735398","seed":32207725007555051749651128309644669433959282602726542687296883223995079735398,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 32357575954 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 32703175954 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 32712495954 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 32712495954 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"1.uart_noise_filter.45391765456046407211790467800440953992164650259776937068742459562204520591085","seed":45391765456046407211790467800440953992164650259776937068742459562204520591085,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/1.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 4786219034 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 6038019034 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6038019034 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 7317259034 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n"]},{"name":"uart_noise_filter","qual_name":"3.uart_noise_filter.9899257021041977296320589799922181339407307516546185382998337747507389540013","seed":9899257021041977296320589799922181339407307516546185382998337747507389540013,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/3.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1823195124 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n","UVM_ERROR @ 1823236790 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 1823340955 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (6 [0x6] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 1823382621 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all","qual_name":"5.uart_stress_all.91293355584586094001321787421123924647955955158810115814711203191407694251394","seed":91293355584586094001321787421123924647955955158810115814711203191407694251394,"line":97,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 33613594993 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 33613594993 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 33615489673 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 33615510725 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_noise_filter","qual_name":"6.uart_noise_filter.58611371600622669409708826991344843203975702804007014002910209710501379612200","seed":58611371600622669409708826991344843203975702804007014002910209710501379612200,"line":80,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/6.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @  68586388 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @  68586388 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 125670178 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 247004482 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n"]},{"name":"uart_noise_filter","qual_name":"9.uart_noise_filter.48660535755798097201979903587398778480137942554895274894444977465964217308314","seed":48660535755798097201979903587398778480137942554895274894444977465964217308314,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/9.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1844903080 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 3686128570 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 3686128570 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 4739849740 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"18.uart_stress_all_with_rand_reset.97081910980147157081561512557523016642545964649962730318237464904013559217705","seed":97081910980147157081561512557523016642545964649962730318237464904013559217705,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 220310115 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_INFO @ 272649075 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/114\n","UVM_INFO @ 392869113 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/114\n","UVM_INFO @ 434165829 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/114\n"]}],"UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_noise_filter","qual_name":"2.uart_noise_filter.76873862368861516414508795886132501997052992557774981836692015691686828618809","seed":76873862368861516414508795886132501997052992557774981836692015691686828618809,"line":82,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/2.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 7612774697 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 7613474697 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (34 [0x22] vs 111 [0x6f]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 7613674697 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 7614074697 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (34 [0x22] vs 61 [0x3d]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"4.uart_noise_filter.14019854777778275078673929606489949785933057964821731768487281674664041103366","seed":14019854777778275078673929606489949785933057964821731768487281674664041103366,"line":85,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 18163226876 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 18163518545 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 18163601879 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 18163685213 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata\n"]}],"UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr":[{"name":"uart_stress_all_with_rand_reset","qual_name":"4.uart_stress_all_with_rand_reset.56466667803501681841587465387514023704470716488594078698941099848415558578549","seed":56466667803501681841587465387514023704470716488594078698941099848415558578549,"line":157,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 12324636939 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/607\n","UVM_ERROR @ 12445449439 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 12445574439 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 12445886939 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata\n"]},{"name":"uart_noise_filter","qual_name":"5.uart_noise_filter.103389516562100658074028245309805998225300100816866134582625750487242884646484","seed":103389516562100658074028245309805998225300100816866134582625750487242884646484,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/5.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 2091491692 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 2100063172 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr\n","UVM_ERROR @ 2100063172 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr\n","UVM_ERROR @ 2243992607 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"7.uart_noise_filter.53167136170656821856602121536578266153714931291657369414844809850846947557228","seed":53167136170656821856602121536578266153714931291657369414844809850846947557228,"line":81,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/7.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 1432751794 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1438449514 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 1438449514 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 1441821634 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]},{"name":"uart_noise_filter","qual_name":"8.uart_noise_filter.25099313781378674982314718008488142219235703012219691948370695677506757792045","seed":25099313781378674982314718008488142219235703012219691948370695677506757792045,"line":88,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/8.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19130985628 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19130985628 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 \n","UVM_ERROR @ 19169768119 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 2\n","UVM_ERROR @ 19169788953 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]},{"name":"uart_stress_all_with_rand_reset","qual_name":"17.uart_stress_all_with_rand_reset.73101975698930645828174574623949476882472077756854180192816657357297445660018","seed":73101975698930645828174574623949476882472077756854180192816657357297445660018,"line":166,"log_path":"/nightly/current_run/scratch/master/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6099056116 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 6157936116 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n","UVM_INFO @ 6261536116 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/350\n","UVM_ERROR @ 6294776116 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark\n"]}]}},"passed":439,"total":453,"percent":96.90949227373068}