{"block":{"name":"pattgen","variant":null,"commit":"afb7e07f4dc198eec01c4b00b311910c211ed15e","commit_short":"afb7e07","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/afb7e07f4dc198eec01c4b00b311910c211ed15e","revision_info":"GitHub Revision: [`afb7e07`](https://github.com/lowrisc/opentitan/tree/afb7e07f4dc198eec01c4b00b311910c211ed15e)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-08T15:00:26Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":3.0,"sim_time":166.86979,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":15.918646,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.918880999999999,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":3.0,"sim_time":187.578957,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":50.932550000000006,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":23.129204,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.918880999999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":50.932550000000006,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":63,"total":63,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3602.158375854604,"sim_time":0.0,"passed":23,"total":50,"percent":46.0}},"passed":23,"total":50,"percent":46.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":76.0,"sim_time":4393.360018,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":29.732806,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10801.0,"sim_time":0.0,"passed":22,"total":50,"percent":44.0}},"passed":22,"total":50,"percent":44.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":13.685171,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":23.320144,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":127.486052,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":127.486052,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":15.918646,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.918880999999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":50.932550000000006,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":18.243896,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":15.918646,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":13.918880999999999,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":1.0,"sim_time":50.932550000000006,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":18.243896,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":182,"total":237,"percent":76.79324894514768},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":185.72437599999998,"passed":5,"total":5,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":140.556057,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":185.72437599999998,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":124.00000000000001,"sim_time":19121.546017,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0}},"passed":0,"total":50,"percent":0.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":132.0,"sim_time":10034.258597999999,"passed":41,"total":50,"percent":82.0}},"passed":41,"total":50,"percent":82.0}},"passed":41,"total":50,"percent":82.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.64461094902766571080880688940795229249452165998634210634896844917362058982739","seed":64461094902766571080880688940795229249452165998634210634896844917362058982739,"line":183,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3817318841 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3817318841 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 3817518841 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.26856479485815320311462600332561892177227413020103547396817904999075768415532","seed":26856479485815320311462600332561892177227413020103547396817904999075768415532,"line":253,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1767462333 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1767462333 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/10\n","UVM_INFO @ 1767493584 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.70745308759057722166795364560194664935947842903303992914528007045665988978433","seed":70745308759057722166795364560194664935947842903303992914528007045665988978433,"line":189,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 919277133 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 919277133 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 919327133 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.61789892487119184908827758587546691410555882493273177364437589433014549450270","seed":61789892487119184908827758587546691410555882493273177364437589433014549450270,"line":115,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1243459572 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1243459572 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1243819572 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.653014922190502439463552884295896095497165090374379939917009077093365628502","seed":653014922190502439463552884295896095497165090374379939917009077093365628502,"line":168,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3461022283 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3461022283 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 3461312605 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.26913934565142618644334659590456300296948648262698813450607678422363302136202","seed":26913934565142618644334659590456300296948648262698813450607678422363302136202,"line":117,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2641701101 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2641701101 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2641951103 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.23239892399768076326644197770152372726063492023172411391735366866484524610119","seed":23239892399768076326644197770152372726063492023172411391735366866484524610119,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 446620169 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 446620169 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 446786837 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.69811462454644545660388218198111044651202262865291815494761787965751499974412","seed":69811462454644545660388218198111044651202262865291815494761787965751499974412,"line":129,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1142449611 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1142449611 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1142491277 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.9055776801855663811037256863957547511321155824115463202555471901738676755923","seed":9055776801855663811037256863957547511321155824115463202555471901738676755923,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 475477143 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 475477143 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 475607577 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"9.pattgen_stress_all_with_rand_reset.5072821289792778601738725963943942895396220464914879464369394806294023364522","seed":5072821289792778601738725963943942895396220464914879464369394806294023364522,"line":175,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6941988796 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6941988796 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 6942148796 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.59116657651481404144743610811519620593169707655857173473109705268387046232674","seed":59116657651481404144743610811519620593169707655857173473109705268387046232674,"line":114,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 909216186 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 909216186 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 909591189 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.77618033129375686620344939210885932587594672598358523618180867868073518168439","seed":77618033129375686620344939210885932587594672598358523618180867868073518168439,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1074764588 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1074764588 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1074827090 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.109811868001627594860781018465331804577795320828240240088363896756456887638677","seed":109811868001627594860781018465331804577795320828240240088363896756456887638677,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 580405387 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 580405387 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 580931707 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"13.pattgen_stress_all_with_rand_reset.2647041172065371505744393244279199974536797865123706062878784367112625378219","seed":2647041172065371505744393244279199974536797865123706062878784367112625378219,"line":127,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1305624365 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1305624365 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1305708701 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.73094230631717433923253326403540916606024966089046061151336922265742634413171","seed":73094230631717433923253326403540916606024966089046061151336922265742634413171,"line":147,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3891896992 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3891896992 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 3892666222 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.67045503995674950933418346512944357302274598330003735213025882975242943862670","seed":67045503995674950933418346512944357302274598330003735213025882975242943862670,"line":114,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 412203518 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 412203518 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 412288626 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.71410026500846835525422204840507214144607672708343545593315794980841654813106","seed":71410026500846835525422204840507214144607672708343545593315794980841654813106,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 157681513 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 157681513 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 157752220 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.91716421297183810361453972321796585971498245445904539619670424811889914315939","seed":91716421297183810361453972321796585971498245445904539619670424811889914315939,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 235270828 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 235270828 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 235398490 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.24109029211133598795406565937602238565345588194139479525308293079620548341353","seed":24109029211133598795406565937602238565345588194139479525308293079620548341353,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 587559538 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 587559538 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 587642010 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.14289771621525351272888070178410156609484150341904262224663544702623792743887","seed":14289771621525351272888070178410156609484150341904262224663544702623792743887,"line":189,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1769778066 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1769778066 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1769923227 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.13059163820081746559921169207919762029794584123583981309821972599544435840971","seed":13059163820081746559921169207919762029794584123583981309821972599544435840971,"line":236,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1967354555 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1967354555 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 1967395791 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.41688824702112562223051944379488822670623555746245460436701747384562292693251","seed":41688824702112562223051944379488822670623555746245460436701747384562292693251,"line":118,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2523783057 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2523783057 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2523863057 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.42563813695531571011189731081624627631087859400060842745284931028485816427981","seed":42563813695531571011189731081624627631087859400060842745284931028485816427981,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 211994945 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 211994945 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 212054945 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"26.pattgen_stress_all_with_rand_reset.27283165274871100281733818444834766802261273803490890005031055360773503526701","seed":27283165274871100281733818444834766802261273803490890005031055360773503526701,"line":190,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/26.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2405532951 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2405532951 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 2405824620 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.26703028775667685776396558060701451810040554030659229607836800116347095741737","seed":26703028775667685776396558060701451810040554030659229607836800116347095741737,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 740280948 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 740280948 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 740342172 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.25877986099628645230364992318224758202526955731399547936948381576841305062553","seed":25877986099628645230364992318224758202526955731399547936948381576841305062553,"line":206,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10761442197 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 10761442197 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 10762042197 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.44402865668113040167009025346040695614215721508106364094233576189542632853167","seed":44402865668113040167009025346040695614215721508106364094233576189542632853167,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 408615237 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 408615237 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 408695237 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.87167090242459389722124415450020913227517769537486408929692931606358719344554","seed":87167090242459389722124415450020913227517769537486408929692931606358719344554,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 114565164 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 114565164 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 114627666 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.73147021428278641443866865441548565798857251638235094838128665790579119639384","seed":73147021428278641443866865441548565798857251638235094838128665790579119639384,"line":199,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1320165773 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1320165773 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 1320196700 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.31992485546791233735825762538738776371180938867525605003096812024979458590282","seed":31992485546791233735825762538738776371180938867525605003096812024979458590282,"line":206,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2574141759 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2574141759 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 2574304551 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.2694071492579523541914021534469729848604112985452993067031243512728427091413","seed":2694071492579523541914021534469729848604112985452993067031243512728427091413,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1627159801 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1627159801 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1627194889 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.99083426519057788549785012523365541797210401517917124237176117489650977794435","seed":99083426519057788549785012523365541797210401517917124237176117489650977794435,"line":242,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1492135212 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1492135212 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 5/5\n","UVM_INFO @ 1492215212 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.77258325679492108728043787718535442501357328218742970865243176076438373005855","seed":77258325679492108728043787718535442501357328218742970865243176076438373005855,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 108977214 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 108977214 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 108997622 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.51010924765311901592424179211708587841325638526142281613782812703487221004879","seed":51010924765311901592424179211708587841325638526142281613782812703487221004879,"line":224,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2258278575 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2258278575 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 2258398575 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.55141607727570812729668830483012249876426703387458834254703509797537803550870","seed":55141607727570812729668830483012249876426703387458834254703509797537803550870,"line":141,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2181914806 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2181914806 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 2182039804 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.9101162500074298772492477394212807353597054977050354790939076662701738252734","seed":9101162500074298772492477394212807353597054977050354790939076662701738252734,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 130404126 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 130404126 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 130477045 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.19103848403257066741153700458697230069970199878437154811898937958752355424836","seed":19103848403257066741153700458697230069970199878437154811898937958752355424836,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 970601227 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 970601227 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 970892896 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.31052265212655152109854713615016064347526413034631230302733407204223909744684","seed":31052265212655152109854713615016064347526413034631230302733407204223909744684,"line":115,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4321800765 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4321800765 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 4322164401 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.7100430914359153351794819765759116541135185932043673486289107506715397496834","seed":7100430914359153351794819765759116541135185932043673486289107506715397496834,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3212200762 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3212200762 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 3212409097 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.31858992198675330890315072124653545851337577575508746861002825779592749765913","seed":31858992198675330890315072124653545851337577575508746861002825779592749765913,"line":228,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3186317547 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3186317547 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 3186357547 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.20402533703436568179098804734082298991770094016960491479210856669769318292875","seed":20402533703436568179098804734082298991770094016960491479210856669769318292875,"line":149,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2651217639 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2651217639 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 2651537639 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.25694030022892807888392206519480146484580984139937817433648695405170343583266","seed":25694030022892807888392206519480146484580984139937817433648695405170343583266,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 142947056 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 142947056 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 143065478 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.69439773141787698646622089162159791520605708679635742478778297150623982368837","seed":69439773141787698646622089162159791520605708679635742478778297150623982368837,"line":189,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 266349265 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 266349265 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 266390081 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.7894217386860317736385067023613392576455090255196540804373704361146591780130","seed":7894217386860317736385067023613392576455090255196540804373704361146591780130,"line":187,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 23340843159 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 23340843159 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 23341509827 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.69447439434369223289683170203305439066130277637153783928894009940171028851376","seed":69447439434369223289683170203305439066130277637153783928894009940171028851376,"line":241,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 9469789472 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 9469789472 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 9470289472 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.2419983550924442378383012578053389737321125807839973735035316360790943480844","seed":2419983550924442378383012578053389737321125807839973735035316360790943480844,"line":127,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1451691099 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1451691099 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1451732766 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.43668517435934970766865647542728874771558200150456381768005277574628501610651","seed":43668517435934970766865647542728874771558200150456381768005277574628501610651,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1294964812 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1294964812 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1295964812 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"pattgen_perf","qual_name":"2.pattgen_perf.47804138857633958069091758433627206555933754734764124889210954065072654622471","seed":47804138857633958069091758433627206555933754734764124889210954065072654622471,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"3.pattgen_perf.25475966566007361898592352749405173554422457783171302473269646693957894595952","seed":25475966566007361898592352749405173554422457783171302473269646693957894595952,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"8.pattgen_perf.112204483732465397177333353331507596706640153299522397231509797037839659967454","seed":112204483732465397177333353331507596706640153299522397231509797037839659967454,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"17.pattgen_perf.47851397110894322151002307473166990642923316487487453972047772764254542331371","seed":47851397110894322151002307473166990642923316487487453972047772764254542331371,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"21.pattgen_perf.73450694891044260544091836747149601726229215754089167375752945482279240550404","seed":73450694891044260544091836747149601726229215754089167375752945482279240550404,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"22.pattgen_perf.368420996487799744681996174847354778817312150394767023453929667468420397303","seed":368420996487799744681996174847354778817312150394767023453929667468420397303,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"30.pattgen_perf.61903033635218044736952590527755202484648672018181279377177582642311136384617","seed":61903033635218044736952590527755202484648672018181279377177582642311136384617,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"33.pattgen_perf.54289038536068013234168819612320207971622404011770059607456986185117326446419","seed":54289038536068013234168819612320207971622404011770059607456986185117326446419,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_perf","qual_name":"49.pattgen_perf.14073079482778239129169899090887153952123347072140192779049288334208554240394","seed":14073079482778239129169899090887153952123347072140192779049288334208554240394,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_perf/latest/run.log","log_context":["UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"2.pattgen_inactive_level.21705026560720967654226806627543021935288197125820240515420028580944562809919","seed":21705026560720967654226806627543021935288197125820240515420028580944562809919,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10016619613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"pattgen_stress_all","qual_name":"3.pattgen_stress_all.80602917259116913383487022096669883409310852956941923112661187818334002041976","seed":80602917259116913383487022096669883409310852956941923112661187818334002041976,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"5.pattgen_perf.3042444615596197784442434457815664878262389466808502136045609248052293268667","seed":3042444615596197784442434457815664878262389466808502136045609248052293268667,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"7.pattgen_stress_all.82418669978537434362349754160478432002536412111793405783641019126378665222525","seed":82418669978537434362349754160478432002536412111793405783641019126378665222525,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"10.pattgen_perf.53081197724198116955645715471782629888693592012654683104243862057048057669522","seed":53081197724198116955645715471782629888693592012654683104243862057048057669522,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"11.pattgen_perf.65203792832019426200870037810888744832823855755964281772492636815005788974254","seed":65203792832019426200870037810888744832823855755964281772492636815005788974254,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"14.pattgen_perf.69534637930760382147497591015565377379806440065289718454907050169250352256690","seed":69534637930760382147497591015565377379806440065289718454907050169250352256690,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"14.pattgen_stress_all.114335597036190180667025810117933557709235382958858595385690530580805613266916","seed":114335597036190180667025810117933557709235382958858595385690530580805613266916,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"15.pattgen_perf.59320884662132985280125385229253650711266517438372648583765457966836194092936","seed":59320884662132985280125385229253650711266517438372648583765457966836194092936,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"16.pattgen_perf.18529270287419017895755502722619647118860306445831466609180869670820061979933","seed":18529270287419017895755502722619647118860306445831466609180869670820061979933,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"16.pattgen_stress_all.47925494234637674579212443128373987637415297624234108791522135597002960575143","seed":47925494234637674579212443128373987637415297624234108791522135597002960575143,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"19.pattgen_perf.46088526016975178873197629276035099475512469479189933136320867631131491286775","seed":46088526016975178873197629276035099475512469479189933136320867631131491286775,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"20.pattgen_perf.94359463824041664657602865141823988685982805582920903888535103363583107022206","seed":94359463824041664657602865141823988685982805582920903888535103363583107022206,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"25.pattgen_perf.5635116863133194366766011019607281627659621726790151011153393287386734626454","seed":5635116863133194366766011019607281627659621726790151011153393287386734626454,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"27.pattgen_perf.114252986908227871235321524862314053059717940997360152462558230429739241506201","seed":114252986908227871235321524862314053059717940997360152462558230429739241506201,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"31.pattgen_perf.43033112826050771696658826654062367464567191185092556058746832274506148953345","seed":43033112826050771696658826654062367464567191185092556058746832274506148953345,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"31.pattgen_stress_all.80495288748628082276869137145718567984403703476556572843037186809835321126515","seed":80495288748628082276869137145718567984403703476556572843037186809835321126515,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"32.pattgen_stress_all.2410990710177352090345800175014983997695967480925696788580380666143378803263","seed":2410990710177352090345800175014983997695967480925696788580380666143378803263,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"34.pattgen_perf.109664209734768090415132318947122688083897476880460825652500865157085564213834","seed":109664209734768090415132318947122688083897476880460825652500865157085564213834,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.79395440603628554791424467173579221564383596298809313056079702593466775966413","seed":79395440603628554791424467173579221564383596298809313056079702593466775966413,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"35.pattgen_perf.103752251319760310101352673554199338104003624551922494401657809262448918816379","seed":103752251319760310101352673554199338104003624551922494401657809262448918816379,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"38.pattgen_perf.88945582934700088148143981589369143138534258301119975747471643728527821579372","seed":88945582934700088148143981589369143138534258301119975747471643728527821579372,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"39.pattgen_stress_all.39630774888657687879436131005051340058195671860952978873230507433397602486911","seed":39630774888657687879436131005051340058195671860952978873230507433397602486911,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"41.pattgen_stress_all.55821927988428040081348531448159000485903263804755718306463200624909773974728","seed":55821927988428040081348531448159000485903263804755718306463200624909773974728,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"42.pattgen_perf.16425928816531056709580042621446015867785477481647189726168040360723063618559","seed":16425928816531056709580042621446015867785477481647189726168040360723063618559,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.83778027934495031620508196875252560320574725644115571986422633307709237066192","seed":83778027934495031620508196875252560320574725644115571986422633307709237066192,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"44.pattgen_perf.73675411697729933673024522500491392185830637427462829201995032200633796820145","seed":73675411697729933673024522500491392185830637427462829201995032200633796820145,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"44.pattgen_stress_all.51765890396384028217683101978689650266497293259405090873337193390568575407779","seed":51765890396384028217683101978689650266497293259405090873337193390568575407779,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"45.pattgen_perf.85704843254964907392447990522824397603035840794121584865641968831270253330083","seed":85704843254964907392447990522824397603035840794121584865641968831270253330083,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"46.pattgen_stress_all.94489307703093705281520168194106845759296187349669087534441053166412898429146","seed":94489307703093705281520168194106845759296187349669087534441053166412898429146,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_stress_all/latest/run.log","log_context":[]},{"name":"pattgen_perf","qual_name":"48.pattgen_perf.78891790017371308746915081658542648330133776712935944401816044070151083630863","seed":78891790017371308746915081658542648330133776712935944401816044070151083630863,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_perf/latest/run.log","log_context":[]},{"name":"pattgen_stress_all","qual_name":"48.pattgen_stress_all.76489324203097355885891295980487976881083115691969944471708148270072353619679","seed":76489324203097355885891295980487976881083115691969944471708148270072353619679,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all/latest/run.log","log_context":[]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)":[{"name":"pattgen_inactive_level","qual_name":"4.pattgen_inactive_level.19612531650434638020185812910487371561282384184984462482305555132030406179962","seed":19612531650434638020185812910487371561282384184984462482305555132030406179962,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10034258598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"45.pattgen_inactive_level.77974165587156375360708665950162358440464321885740487156934385898726570391321","seed":77974165587156375360708665950162358440464321885740487156934385898726570391321,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10025647083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared:":[{"name":"pattgen_stress_all","qual_name":"6.pattgen_stress_all.68614563780804179315364329224057707662936085576498676258569489456631401505761","seed":68614563780804179315364329224057707662936085576498676258569489456631401505761,"line":138,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10153\n"]},{"name":"pattgen_stress_all","qual_name":"9.pattgen_stress_all.67278303416774281593515974140425423695200491539688278091504983095781359850209","seed":67278303416774281593515974140425423695200491539688278091504983095781359850209,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @12365\n"]},{"name":"pattgen_stress_all","qual_name":"12.pattgen_stress_all.72630099872419538546016315441064127450803658616659973951753935933425572650680","seed":72630099872419538546016315441064127450803658616659973951753935933425572650680,"line":133,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10180\n"]},{"name":"pattgen_stress_all","qual_name":"15.pattgen_stress_all.41247510070502317151035751562479816007484850104144643968772281218340747881800","seed":41247510070502317151035751562479816007484850104144643968772281218340747881800,"line":141,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10139\n"]},{"name":"pattgen_stress_all","qual_name":"18.pattgen_stress_all.68957852425279273699737183214096232861299131097023751216400493988938291345948","seed":68957852425279273699737183214096232861299131097023751216400493988938291345948,"line":167,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10247\n"]},{"name":"pattgen_stress_all","qual_name":"20.pattgen_stress_all.61947826109299173796306801350348098914453898709546007054692741487453314212278","seed":61947826109299173796306801350348098914453898709546007054692741487453314212278,"line":132,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @12063\n"]},{"name":"pattgen_stress_all","qual_name":"22.pattgen_stress_all.104379920909876000564237649118283677399677882957798228312978060592259208821995","seed":104379920909876000564237649118283677399677882957798228312978060592259208821995,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10224\n"]},{"name":"pattgen_stress_all","qual_name":"25.pattgen_stress_all.27317276525904387730069788952716415081319166497285972862844984286019747146267","seed":27317276525904387730069788952716415081319166497285972862844984286019747146267,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11461\n"]},{"name":"pattgen_stress_all","qual_name":"27.pattgen_stress_all.18978744025478697569813263342146114672757821023719480088095052945856742034908","seed":18978744025478697569813263342146114672757821023719480088095052945856742034908,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10185\n"]},{"name":"pattgen_stress_all","qual_name":"28.pattgen_stress_all.61187567873777953856286299233207832526921336226679360958764509914441871790095","seed":61187567873777953856286299233207832526921336226679360958764509914441871790095,"line":145,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/28.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10244\n"]},{"name":"pattgen_stress_all","qual_name":"29.pattgen_stress_all.105965046611568480290243964262381215280702470775940981024090197256445167344026","seed":105965046611568480290243964262381215280702470775940981024090197256445167344026,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10180\n"]},{"name":"pattgen_stress_all","qual_name":"30.pattgen_stress_all.106366486605056702436373423489414569242325605597710203263699603417839067266373","seed":106366486605056702436373423489414569242325605597710203263699603417839067266373,"line":141,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all/latest/run.log","log_context":["----------------------------------------\n","Name         Type          Size   Value \n","----------------------------------------\n","exp_item     pattgen_item  -      @10386\n"]},{"name":"pattgen_stress_all","qual_name":"33.pattgen_stress_all.72744575179533175529142322315950997291817189870647290614238640623445555677817","seed":72744575179533175529142322315950997291817189870647290614238640623445555677817,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10221\n"]},{"name":"pattgen_stress_all","qual_name":"35.pattgen_stress_all.38789503504780668078774788766527053071314283893830683814919057358104656874830","seed":38789503504780668078774788766527053071314283893830683814919057358104656874830,"line":145,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10163\n"]},{"name":"pattgen_stress_all","qual_name":"40.pattgen_stress_all.32587029447019373007393312412986345819679737979124458617260160191715109689236","seed":32587029447019373007393312412986345819679737979124458617260160191715109689236,"line":146,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @10170\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23)":[{"name":"pattgen_inactive_level","qual_name":"9.pattgen_inactive_level.60908874057785549793043140531772715409652943121194577802397770024850825070149","seed":60908874057785549793043140531772715409652943121194577802397770024850825070149,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10086379152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard]":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.97280308862639784244720911539239733620655725877109657176044340460396213640328","seed":97280308862639784244720911539239733620655725877109657176044340460396213640328,"line":129,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.16759613429090553522531733144923443479160002007672077286836128534170581126635","seed":16759613429090553522531733144923443479160002007672077286836128534170581126635,"line":120,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.6874292376923430429341589161288054682265110392221493867572043427777903961471","seed":6874292376923430429341589161288054682265110392221493867572043427777903961471,"line":126,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["--> channel 1 item mismatch!\n","--> EXP:\n","------------------------------------\n","Name      Type          Size  Value \n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)":[{"name":"pattgen_inactive_level","qual_name":"15.pattgen_inactive_level.1433904621158980219328191639793925268711544414119764122392364286048801955241","seed":1433904621158980219328191639793925268711544414119764122392364286048801955241,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10018121971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"21.pattgen_inactive_level.36191659111317268434810041332061416087068988055436173706264182023991045120331","seed":36191659111317268434810041332061416087068988055436173706264182023991045120331,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10025145137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20)":[{"name":"pattgen_inactive_level","qual_name":"43.pattgen_inactive_level.52267971571723606399013108883485291100117710606052661271757975305697581465862","seed":52267971571723606399013108883485291100117710606052661271757975305697581465862,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10024980212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)":[{"name":"pattgen_inactive_level","qual_name":"46.pattgen_inactive_level.53350857715269112334718191401822318690729160231248729507346555503572312872700","seed":53350857715269112334718191401822318690729160231248729507346555503572312872700,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10019911759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)":[{"name":"pattgen_inactive_level","qual_name":"48.pattgen_inactive_level.30068549052944192234187906733817692330737174540075578498420884843735996060241","seed":30068549052944192234187906733817692330737174540075578498420884843735996060241,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10063806931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":289,"total":403,"percent":71.712158808933}