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"max_time":22.41,"sim_time":4759.7285839999995,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":22.41,"sim_time":4759.7285839999995,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":22.41,"sim_time":4759.7285839999995,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":15.75,"sim_time":4407.2852920000005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":33.98,"sim_time":4705.480442,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":33.98,"sim_time":4705.480442,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":33.98,"sim_time":4705.480442,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":35.66,"sim_time":3469.5234840000003,"passed":10,"total":10,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":9.95,"sim_time":2769.086113,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":33.98,"sim_time":4705.480442,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":466.14,"sim_time":326217.003742,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":13.2,"sim_time":5752.52672,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":13.2,"sim_time":5752.52672,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":635.72,"sim_time":252940.32038299998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":544.96,"sim_time":147033.240225,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":504.86,"sim_time":193048.00450799998,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.15,"sim_time":17.197221000000003,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.11,"sim_time":27.661877,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":4.04,"sim_time":337.77123700000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":4.04,"sim_time":337.77123700000004,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.33,"sim_time":64.909425,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.64,"sim_time":114.247478,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.96,"sim_time":2981.127678,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.83,"sim_time":382.199622,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.33,"sim_time":64.909425,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":2.64,"sim_time":114.247478,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.96,"sim_time":2981.127678,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.83,"sim_time":382.199622,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":207,"total":228,"percent":90.78947368421052},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.71,"sim_time":96.160747,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":18.86,"sim_time":2440.223552,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":18.86,"sim_time":2440.223552,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":496.74,"sim_time":88407.196402,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.1,"branch":98.4,"condition_expression":96.56,"toggle":83.54,"fsm":89.36},"assertion":94.64,"functional":97.92},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.21908803506212972718913559106097914902170862553748972744185771897326893172677","seed":21908803506212972718913559106097914902170862553748972744185771897326893172677,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4054366 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4054366 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[923])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.50398042082835361647870113181932624607148923415703302536427597762659627629899","seed":50398042082835361647870113181932624607148923415703302536427597762659627629899,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4237670 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4237670 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[941])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.43496276920192983231824417430056082726692395241095339805627789355150481080094","seed":43496276920192983231824417430056082726692395241095339805627789355150481080094,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4282718 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4282718 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.78653330833399926242934055778425614987049527575954042256760379719682119762946","seed":78653330833399926242934055778425614987049527575954042256760379719682119762946,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    956780 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    956780 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[902])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.79122700172814709838344214186338875156117957474697181188015486809255858977190","seed":79122700172814709838344214186338875156117957474697181188015486809255858977190,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3721087 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3721087 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[983])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.74251536087413468837250227973055116470581951081501994855181147815707975419908","seed":74251536087413468837250227973055116470581951081501994855181147815707975419908,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    868996 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    868996 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[998])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.17823820842392337002786645808231573842089846781104005826207182296918850445652","seed":17823820842392337002786645808231573842089846781104005826207182296918850445652,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5454550 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5454550 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[896])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.259627620603792851193740913588821762370667453818786147443358959664045216004","seed":259627620603792851193740913588821762370667453818786147443358959664045216004,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1268448 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1268448 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.33357980221038862467646780802527423622432570196991136299698002084937761577033","seed":33357980221038862467646780802527423622432570196991136299698002084937761577033,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1246995 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1246995 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[931])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.24341218193516713121914889269616077459031011242216885810294188436674777983072","seed":24341218193516713121914889269616077459031011242216885810294188436674777983072,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2033371 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2033371 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.110592305867382188917849216835299773751467762607126659266339989569942295248221","seed":110592305867382188917849216835299773751467762607126659266339989569942295248221,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4044497 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4044497 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[923])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.98192711611595685119216255753424525327401918836984245872599451644163502444035","seed":98192711611595685119216255753424525327401918836984245872599451644163502444035,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4170076 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4170076 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[944])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.45691954675224322033378663699087277981352784506014788305100529010988767495169","seed":45691954675224322033378663699087277981352784506014788305100529010988767495169,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    788233 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    788233 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[920])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.97868779050964708186754940913498475165699579152934731971196225347220226521651","seed":97868779050964708186754940913498475165699579152934731971196225347220226521651,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   9826426 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   9826426 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[924])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.42686003283296720085044041650228359624731405183861130189153252081844056735659","seed":42686003283296720085044041650228359624731405183861130189153252081844056735659,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1179637 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1179637 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[968])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.4018918979845247100881813931873492959950357453143727313656672476447437740052","seed":4018918979845247100881813931873492959950357453143727313656672476447437740052,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1061231 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1061231 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[948])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.90822752649846002918499077112190878540851922066704331032888618098613776664974","seed":90822752649846002918499077112190878540851922066704331032888618098613776664974,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1075684 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1075684 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[924])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.92123857398894769938124465045696009036696782620965166771995012911686078045247","seed":92123857398894769938124465045696009036696782620965166771995012911686078045247,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3493275 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3493275 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[910])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.93651008260643668665491525445809696110154776138752451700734400572682910651651","seed":93651008260643668665491525445809696110154776138752451700734400572682910651651,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3725881 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3725881 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[964])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.101298192734244114585713560976917664960217027284047728375843169448279054023377","seed":101298192734244114585713560976917664960217027284047728375843169448279054023377,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    875416 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    875416 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[946])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.70932739931386203837327213901071250929757702292756118633743988846236315971480","seed":70932739931386203837327213901071250929757702292756118633743988846236315971480,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1148036 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe74800 [111001110100100000000000] vs 0x0 [0]) \n","UVM_ERROR @   1174036 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c8cc4 [1011001000110011000100] vs 0x0 [0]) \n","UVM_ERROR @   1238036 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd13928 [110100010011100100101000] vs 0x0 [0]) \n","UVM_ERROR @   1317036 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x45d630 [10001011101011000110000] vs 0x0 [0]) \n"]}]}},"passed":235,"total":256,"percent":91.796875}