{"block":{"name":"sysrst_ctrl","variant":null,"commit":"afb7e07f4dc198eec01c4b00b311910c211ed15e","commit_short":"afb7e07","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/afb7e07f4dc198eec01c4b00b311910c211ed15e","revision_info":"GitHub Revision: [`afb7e07`](https://github.com/lowrisc/opentitan/tree/afb7e07f4dc198eec01c4b00b311910c211ed15e)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-08T15:00:26Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"sysrst_ctrl_smoke":{"max_time":9.33,"sim_time":2112.028276,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"input_output_inverted":{"tests":{"sysrst_ctrl_in_out_inverted":{"max_time":10.28,"sim_time":2458.914494,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_ec_rst":{"tests":{"sysrst_ctrl_combo_detect_ec_rst":{"max_time":5.64,"sim_time":2444.723627,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"combo_detect_ec_rst_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_ec_rst_with_pre_cond":{"max_time":10.94,"sim_time":2549.27477,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_hw_reset":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.76,"sim_time":6054.218381,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.19,"sim_time":2054.161845,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"sysrst_ctrl_csr_bit_bash":{"max_time":7.43,"sim_time":4200.010767,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"sysrst_ctrl_csr_aliasing":{"max_time":6.54,"sim_time":3329.6229900000003,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"sysrst_ctrl_csr_mem_rw_with_rand_reset":{"max_time":5.61,"sim_time":2115.406673,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"sysrst_ctrl_csr_rw":{"max_time":5.19,"sim_time":2054.161845,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":6.54,"sim_time":3329.6229900000003,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":43,"total":43,"percent":100.0},"V2":{"testpoints":{"combo_detect":{"tests":{"sysrst_ctrl_combo_detect":{"max_time":215.42,"sim_time":86813.485542,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"combo_detect_with_pre_cond":{"tests":{"sysrst_ctrl_combo_detect_with_pre_cond":{"max_time":543.78,"sim_time":210825.671232,"passed":92,"total":100,"percent":92.0}},"passed":92,"total":100,"percent":92.0},"auto_block_key_outputs":{"tests":{"sysrst_ctrl_auto_blk_key_output":{"max_time":554.23,"sim_time":182784.114839,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"keyboard_input_triggered_interrupt":{"tests":{"sysrst_ctrl_edge_detect":{"max_time":601.64,"sim_time":596784.31164,"passed":47,"total":50,"percent":94.0}},"passed":47,"total":50,"percent":94.0},"pin_output_keyboard_inversion_control":{"tests":{"sysrst_ctrl_pin_override_test":{"max_time":11.35,"sim_time":2512.2519989999996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pin_input_value_accessibility":{"tests":{"sysrst_ctrl_pin_access_test":{"max_time":8.9,"sim_time":2151.5850469999996,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ec_power_on_reset":{"tests":{"sysrst_ctrl_ec_pwr_on_rst":{"max_time":1508.75,"sim_time":817651.512172,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"flash_write_protect_output":{"tests":{"sysrst_ctrl_flash_wr_prot_out":{"max_time":10.96,"sim_time":2610.3237400000003,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"ultra_low_power_test":{"tests":{"sysrst_ctrl_ultra_low_pwr":{"max_time":6.64,"sim_time":5899.789546,"passed":7,"total":10,"percent":70.0}},"passed":7,"total":10,"percent":70.0},"sysrst_ctrl_feature_disable":{"tests":{"sysrst_ctrl_feature_disable":{"max_time":64.13,"sim_time":30246.940322000002,"passed":2,"total":2,"percent":100.0}},"passed":2,"total":2,"percent":100.0},"stress_all":{"tests":{"sysrst_ctrl_stress_all":{"max_time":382.55,"sim_time":146366.69825,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"sysrst_ctrl_alert_test":{"max_time":7.32,"sim_time":2011.4652400000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"sysrst_ctrl_intr_test":{"max_time":9.54,"sim_time":2009.6929490000002,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":7.46,"sim_time":2032.7087120000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_illegal_access":{"tests":{"sysrst_ctrl_tl_errors":{"max_time":7.46,"sim_time":2032.7087120000003,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"tl_d_outstanding_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.76,"sim_time":6054.218381,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.19,"sim_time":2054.161845,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":6.54,"sim_time":3329.6229900000003,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.86,"sim_time":7895.276918,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"sysrst_ctrl_csr_hw_reset":{"max_time":5.76,"sim_time":6054.218381,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_csr_rw":{"max_time":5.19,"sim_time":2054.161845,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_csr_aliasing":{"max_time":6.54,"sim_time":3329.6229900000003,"passed":1,"total":1,"percent":100.0},"sysrst_ctrl_same_csr_outstanding":{"max_time":21.86,"sim_time":7895.276918,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":270,"total":284,"percent":95.07042253521126},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"sysrst_ctrl_sec_cm":{"max_time":67.84,"sim_time":22051.368723,"passed":5,"total":5,"percent":100.0},"sysrst_ctrl_tl_intg_err":{"max_time":126.81,"sim_time":42412.44084,"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"sysrst_ctrl_tl_intg_err":{"max_time":126.81,"sim_time":42412.44084,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"sysrst_ctrl_stress_all_with_rand_reset":{"max_time":67.09,"sim_time":827744.524826,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":99.33,"branch":99.44,"condition_expression":97.88,"toggle":100.0,"fsm":92.95},"assertion":97.89,"functional":91.03},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) \u0001":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"0.sysrst_ctrl_ultra_low_pwr.11059392244986061250924521849036658807606294529770360782711100434001722884238","seed":11059392244986061250924521849036658807606294529770360782711100434001722884238,"line":658,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 3320291485 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) \n","UVM_INFO @ 3320291485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error":[{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"2.sysrst_ctrl_ultra_low_pwr.70107580581798277218021001414813524770850301741269365825750857953525053602664","seed":70107580581798277218021001414813524770850301741269365825750857953525053602664,"line":659,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 5249641424 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 5249641424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_ultra_low_pwr","qual_name":"4.sysrst_ctrl_ultra_low_pwr.2676621596901387849306258444171947584184197685829714926428006661372109702050","seed":2676621596901387849306258444171947584184197685829714926428006661372109702050,"line":659,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log","log_context":["UVM_ERROR @ 4467850477 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 4467850477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"9.sysrst_ctrl_edge_detect.109173743676978976790133385647887446929694824047660421823559282154942620351807","seed":109173743676978976790133385647887446929694824047660421823559282154942620351807,"line":665,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2695372853 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2695372853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"25.sysrst_ctrl_edge_detect.86481491571420413710628949354839354830591871789733583045682268435749471586218","seed":86481491571420413710628949354839354830591871789733583045682268435749471586218,"line":664,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2379225874 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2379225874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_edge_detect","qual_name":"42.sysrst_ctrl_edge_detect.75453237298093000875151060452417050200645339759261798737951196558005869705664","seed":75453237298093000875151060452417050200645339759261798737951196558005869705664,"line":662,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest/run.log","log_context":["UVM_ERROR @ 2531239786 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly\n","UVM_INFO @ 2531239786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"37.sysrst_ctrl_combo_detect_with_pre_cond.3943610376817633640297595689393124870437930205976705841921144903167585629299","seed":3943610376817633640297595689393124870437930205976705841921144903167585629299,"line":670,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 16619349152 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 16619349152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"57.sysrst_ctrl_combo_detect_with_pre_cond.56333048163634018205181748018184764892249473768637077788240833981878740258678","seed":56333048163634018205181748018184764892249473768637077788240833981878740258678,"line":684,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 51578949757 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a\n","UVM_INFO @ 51578991423 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32\n","UVM_INFO @ 53408068380 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 53408170489 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*])":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"40.sysrst_ctrl_combo_detect_with_pre_cond.82550093422128547119978444256254875558498103708875216148078957384566239131195","seed":82550093422128547119978444256254875558498103708875216148078957384566239131195,"line":674,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 28754442564 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 28754442564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"63.sysrst_ctrl_combo_detect_with_pre_cond.53412949926640846053853926940037642310485952459547319869143485989530066072022","seed":53412949926640846053853926940037642310485952459547319869143485989530066072022,"line":666,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 23796276514 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e\n","UVM_INFO @ 23796297348 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c\n","UVM_INFO @ 24895830419 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0\n","UVM_INFO @ 24910830419 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= b\n"]},{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"78.sysrst_ctrl_combo_detect_with_pre_cond.41354840340226987563842632806951451468569347046800386262398270961907378723517","seed":41354840340226987563842632806951451468569347046800386262398270961907378723517,"line":679,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 26050523481 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) \n","UVM_INFO @ 26050523481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(4) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"41.sysrst_ctrl_combo_detect_with_pre_cond.24262674976098441428785805956816811206872573093546866637711748206848416116039","seed":24262674976098441428785805956816811206872573093546866637711748206848416116039,"line":699,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_INFO @ 19249258690 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1\n","UVM_INFO @ 19269258690 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0\n","UVM_INFO @ 29421979175 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x21\n","UVM_INFO @ 29422685063 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x31\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(4) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"43.sysrst_ctrl_combo_detect_with_pre_cond.95902026559471994397019446785694194593832806039185736786527712374342587497624","seed":95902026559471994397019446785694194593832806039185736786527712374342587497624,"line":668,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 13855935226 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(4) +/-4 \n","UVM_INFO @ 13855935226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-*":[{"name":"sysrst_ctrl_combo_detect_with_pre_cond","qual_name":"98.sysrst_ctrl_combo_detect_with_pre_cond.106772533542182717928015278017569249250425838205272316743010079394544177343183","seed":106772533542182717928015278017569249250425838205272316743010079394544177343183,"line":726,"log_path":"/nightly/current_run/scratch/reseed_opt/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log","log_context":["UVM_ERROR @ 70317985791 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-4 \n","UVM_INFO @ 70317985791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":326,"total":340,"percent":95.88235294117646}