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[scoreboard] alert fatal has unexpected timeout error":[{"name":"otbn_rf_bignum_intg_err","qual_name":"3.otbn_rf_bignum_intg_err.95601258392882952465864643008670879509122803193601301678586612403545784179640","seed":95601258392882952465864643008670879509122803193601301678586612403545784179640,"line":114,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/3.otbn_rf_bignum_intg_err/latest/run.log","log_context":["UVM_INFO @ 308695614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otbn_stress_all_with_rand_reset","qual_name":"4.otbn_stress_all_with_rand_reset.61453344426455722699628830356856079347416323643014892009549859173744389683933","seed":61453344426455722699628830356856079347416323643014892009549859173744389683933,"line":165,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  39117495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"otbn_stress_all","qual_name":"3.otbn_stress_all.54507457739257647581859553110694787309555097908920051242160341768411214243889","seed":54507457739257647581859553110694787309555097908920051242160341768411214243889,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/3.otbn_stress_all/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]},{"name":"otbn_escalate","qual_name":"45.otbn_escalate.50671475478322482025509854798427162769928754664491378786934689853970009400826","seed":50671475478322482025509854798427162769928754664491378786934689853970009400826,"line":null,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/45.otbn_escalate/latest/run.log","log_context":["                        ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 122, in _gen_loop_head\n","    enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)\n","                             ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^\n","  File \"/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py\", line 67, in _pick_bodysize\n","    assert bodysize is not None\n","           ^^^^^^^^^^^^^^^^^^^^\n","AssertionError\n","ninja: build stopped: subcommand failed.\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1\n"]}],"UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"7.otbn_stress_all_with_rand_reset.98040312744644610537468755506342033882193783369245650780221735405684359323816","seed":98040312744644610537468755506342033882193783369245650780221735405684359323816,"line":355,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 3897758482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)":[{"name":"otbn_stress_all_with_rand_reset","qual_name":"9.otbn_stress_all_with_rand_reset.73703981184056594730889318306173080230861249365616140577605344632451685332094","seed":73703981184056594730889318306173080230861249365616140577605344632451685332094,"line":305,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 827434992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_controller.sv,703): Assertion NoStallOnBranch has failed":[{"name":"otbn_ctrl_redun","qual_name":"11.otbn_ctrl_redun.86143493797706916425942453818600807179402602134854088745599165258554049493596","seed":86143493797706916425942453818600807179402602134854088745599165258554049493596,"line":116,"log_path":"/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log","log_context":["UVM_ERROR @ 167106879 ps: (otbn_controller.sv:703) [ASSERT FAILED] NoStallOnBranch\n","UVM_INFO @ 167106879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}]}},"passed":423,"total":436,"percent":97.01834862385321}