{"block":{"name":"pattgen","variant":null,"commit":"9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a","commit_short":"9b0af25","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a","revision_info":"GitHub Revision: [`9b0af25`](https://github.com/lowrisc/opentitan/tree/9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a)"},"tool":{"name":"xcelium","version":"unknown"},"timestamp":"2026-05-15T15:00:24Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/pattgen/data/pattgen_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"pattgen_smoke":{"max_time":4.0,"sim_time":111.78947199999999,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"csr_hw_reset":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.325793,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":25.108752,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"pattgen_csr_bit_bash":{"max_time":2.0,"sim_time":102.63457399999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":17.610006000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"pattgen_csr_mem_rw_with_rand_reset":{"max_time":2.0,"sim_time":27.172256,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"pattgen_csr_rw":{"max_time":2.0,"sim_time":25.108752,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":17.610006000000002,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0}},"passed":63,"total":63,"percent":100.0},"V2":{"testpoints":{"perf":{"tests":{"pattgen_perf":{"max_time":3602.079607689753,"sim_time":0.0,"passed":25,"total":50,"percent":50.0}},"passed":25,"total":50,"percent":50.0},"cnt_rollover":{"tests":{"cnt_rollover":{"max_time":53.0,"sim_time":2676.237306,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"error":{"tests":{"pattgen_error":{"max_time":2.0,"sim_time":17.279894,"passed":50,"total":50,"percent":100.0}},"passed":50,"total":50,"percent":100.0},"stress_all":{"tests":{"pattgen_stress_all":{"max_time":10802.188294770196,"sim_time":0.0,"passed":16,"total":50,"percent":32.0}},"passed":16,"total":50,"percent":32.0},"alert_test":{"tests":{"pattgen_alert_test":{"max_time":2.0,"sim_time":132.404454,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"pattgen_intr_test":{"max_time":2.0,"sim_time":37.695176,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":67.035365,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"pattgen_tl_errors":{"max_time":3.0,"sim_time":67.035365,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.325793,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":25.108752,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":17.610006000000002,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":14.117631,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"pattgen_csr_hw_reset":{"max_time":1.0,"sim_time":27.325793,"passed":1,"total":1,"percent":100.0},"pattgen_csr_rw":{"max_time":2.0,"sim_time":25.108752,"passed":5,"total":5,"percent":100.0},"pattgen_csr_aliasing":{"max_time":2.0,"sim_time":17.610006000000002,"passed":1,"total":1,"percent":100.0},"pattgen_same_csr_outstanding":{"max_time":2.0,"sim_time":14.117631,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":198,"total":257,"percent":77.04280155642023},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":66.942689,"passed":25,"total":25,"percent":100.0},"pattgen_sec_cm":{"max_time":2.0,"sim_time":74.88238700000001,"passed":5,"total":5,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"pattgen_tl_intg_err":{"max_time":2.0,"sim_time":66.942689,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"V3":{"testpoints":{"stress_all_with_rand_reset":{"tests":{"pattgen_stress_all_with_rand_reset":{"max_time":118.0,"sim_time":17304.640611000003,"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0}},"passed":3,"total":50,"percent":6.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"pattgen_inactive_level":{"max_time":219.0,"sim_time":10004.78918,"passed":34,"total":50,"percent":68.0}},"passed":34,"total":50,"percent":68.0}},"passed":34,"total":50,"percent":68.0}},"coverage":{"code":{"block":100.0,"line_statement":100.0,"branch":100.0,"condition_expression":null,"toggle":96.61,"fsm":null},"assertion":96.95,"functional":89.42},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/cov_report/index.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.":[{"name":"pattgen_stress_all_with_rand_reset","qual_name":"0.pattgen_stress_all_with_rand_reset.63664425844087122589158745132939872305192886662026993875930476105319630932598","seed":63664425844087122589158745132939872305192886662026993875930476105319630932598,"line":190,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 5832246787 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 5832246787 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 5832406787 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"1.pattgen_stress_all_with_rand_reset.45298523475039433245733595696573499112036375292555662935804936585816511573466","seed":45298523475039433245733595696573499112036375292555662935804936585816511573466,"line":219,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4073550088 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4073550088 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 4073670088 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"2.pattgen_stress_all_with_rand_reset.112941098879191363902685801605348338197492236751304684450510026336939392516923","seed":112941098879191363902685801605348338197492236751304684450510026336939392516923,"line":175,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4884269900 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4884269900 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 4884353234 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"3.pattgen_stress_all_with_rand_reset.42574758852887082795343900011520206242905151651687256864859217184747918684435","seed":42574758852887082795343900011520206242905151651687256864859217184747918684435,"line":243,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1432914910 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1432914910 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1432945522 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"4.pattgen_stress_all_with_rand_reset.93000167162377439687301519720692877997830143128948417348496287688612598713970","seed":93000167162377439687301519720692877997830143128948417348496287688612598713970,"line":153,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2963382293 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2963382293 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 2963502293 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"5.pattgen_stress_all_with_rand_reset.26313413082085389253503977516853681255851919092592352534998859883331017296593","seed":26313413082085389253503977516853681255851919092592352534998859883331017296593,"line":229,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2451560001 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2451560001 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2451755652 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"6.pattgen_stress_all_with_rand_reset.27463143123613021159546180482509948709730169978448602080417818067773933051248","seed":27463143123613021159546180482509948709730169978448602080417818067773933051248,"line":213,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 407764905 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 407764905 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 407858658 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"7.pattgen_stress_all_with_rand_reset.27069608932020877636806998486283269303307521041245554975277149423282394157957","seed":27069608932020877636806998486283269303307521041245554975277149423282394157957,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 218889572 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 218889572 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 218929572 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"8.pattgen_stress_all_with_rand_reset.48114396132584867902877169974087235363108326339394690354082606981457721488861","seed":48114396132584867902877169974087235363108326339394690354082606981457721488861,"line":122,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 705377050 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 705377050 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 705427050 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"10.pattgen_stress_all_with_rand_reset.99190342536990761808039501394486687345443678064355603726234226704522429550274","seed":99190342536990761808039501394486687345443678064355603726234226704522429550274,"line":168,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 8305649650 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 8305649650 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 8305803496 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"11.pattgen_stress_all_with_rand_reset.108210555840187037011377333250914942848653462295778122852999415953039944010392","seed":108210555840187037011377333250914942848653462295778122852999415953039944010392,"line":232,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2313850259 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2313850259 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 2313970259 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"12.pattgen_stress_all_with_rand_reset.14105207356221648441214564064193696497466127459143423520005872214442071853291","seed":14105207356221648441214564064193696497466127459143423520005872214442071853291,"line":131,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1023225263 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1023225263 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1023275263 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"14.pattgen_stress_all_with_rand_reset.68604181529767675874397874947460988522177574593548712519685611625580980297745","seed":68604181529767675874397874947460988522177574593548712519685611625580980297745,"line":146,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1246401784 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1246401784 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1246681784 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"15.pattgen_stress_all_with_rand_reset.70318056321160151364948819086992591093501101879718552434824680957953541884813","seed":70318056321160151364948819086992591093501101879718552434824680957953541884813,"line":115,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 310872496 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 310872496 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 310941460 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"16.pattgen_stress_all_with_rand_reset.32705347829179141435238787459417960760597069812166192754180647374653682787678","seed":32705347829179141435238787459417960760597069812166192754180647374653682787678,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 207312868 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 207312868 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 207389792 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"17.pattgen_stress_all_with_rand_reset.106728593822904317049527019664425833600665879369766240856231649201369521681741","seed":106728593822904317049527019664425833600665879369766240856231649201369521681741,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 932861880 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 932861880 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 932933308 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"18.pattgen_stress_all_with_rand_reset.114447073043091560947190772822499196326135013044142336178196458010316454848329","seed":114447073043091560947190772822499196326135013044142336178196458010316454848329,"line":255,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4148790054 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4148790054 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 4148890054 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"19.pattgen_stress_all_with_rand_reset.45881070075579599673925980168730489110241009572077356501730386211241573012030","seed":45881070075579599673925980168730489110241009572077356501730386211241573012030,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1652369587 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1652369587 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1652661256 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"20.pattgen_stress_all_with_rand_reset.51919673234324808812866010790930141971861524346803880766039242002844031128121","seed":51919673234324808812866010790930141971861524346803880766039242002844031128121,"line":131,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3106117582 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3106117582 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 3106357582 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"21.pattgen_stress_all_with_rand_reset.48692588253719394383880221851734812387171545546125648693781306136349148655571","seed":48692588253719394383880221851734812387171545546125648693781306136349148655571,"line":176,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3803866214 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3803866214 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 3803991215 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"22.pattgen_stress_all_with_rand_reset.41405824313259552628313335675949966974819793579710884916688337631491788099084","seed":41405824313259552628313335675949966974819793579710884916688337631491788099084,"line":124,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 405208213 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 405208213 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 405281132 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"23.pattgen_stress_all_with_rand_reset.35846918972682023378611951534238176104322652295575090344901886674712979019135","seed":35846918972682023378611951534238176104322652295575090344901886674712979019135,"line":151,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 858030553 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 858030553 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 858120553 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"24.pattgen_stress_all_with_rand_reset.91397580258664683380349386718822209148697849334723754100088430556152374366790","seed":91397580258664683380349386718822209148697849334723754100088430556152374366790,"line":293,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7417582216 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7417582216 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 7417748884 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"25.pattgen_stress_all_with_rand_reset.11857400305120162570840416919308141597418632791101882454056058873821086672319","seed":11857400305120162570840416919308141597418632791101882454056058873821086672319,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6594450977 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6594450977 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/5\n","UVM_INFO @ 6594867647 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"27.pattgen_stress_all_with_rand_reset.44017837583673914426415393450246589717777583384539661425158532214085726279171","seed":44017837583673914426415393450246589717777583384539661425158532214085726279171,"line":119,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1811969481 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1811969481 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1812177811 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"28.pattgen_stress_all_with_rand_reset.105483291426416147225105380076987772453368598121067645583506975205671932274502","seed":105483291426416147225105380076987772453368598121067645583506975205671932274502,"line":143,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/28.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 230576800 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 230576800 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 230668636 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"29.pattgen_stress_all_with_rand_reset.55477358546031040330520063032996097933529038063730849201949905347826453533326","seed":55477358546031040330520063032996097933529038063730849201949905347826453533326,"line":139,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2037635346 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2037635346 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 2037775346 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"30.pattgen_stress_all_with_rand_reset.74716215403941102511187546198225632942263833580495166179400398691459550726042","seed":74716215403941102511187546198225632942263833580495166179400398691459550726042,"line":226,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1533339387 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1533339387 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/5\n","UVM_INFO @ 1533429387 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"31.pattgen_stress_all_with_rand_reset.103110391204464350010839467602903230326987133370860891021826094218085790369416","seed":103110391204464350010839467602903230326987133370860891021826094218085790369416,"line":381,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 7731220732 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 7731220732 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 7/10\n","UVM_INFO @ 7731363588 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"32.pattgen_stress_all_with_rand_reset.31466089709632296427538259020207940367429558696329490396906060802278516633479","seed":31466089709632296427538259020207940367429558696329490396906060802278516633479,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 798194261 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 798194261 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 798348107 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"33.pattgen_stress_all_with_rand_reset.67693336483640819170841608536009881542253352625811484374321154555447764954428","seed":67693336483640819170841608536009881542253352625811484374321154555447764954428,"line":161,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1020352921 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1020352921 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 1020384172 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"34.pattgen_stress_all_with_rand_reset.54874611665670097900699787307747794289953510807560170236316415178891072255502","seed":54874611665670097900699787307747794289953510807560170236316415178891072255502,"line":178,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 6404466408 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 6404466408 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 6404819352 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"35.pattgen_stress_all_with_rand_reset.87928515076600477575903239116707887665648256436084370516411440370028802333429","seed":87928515076600477575903239116707887665648256436084370516411440370028802333429,"line":113,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1770986366 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1770986366 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1771804547 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"36.pattgen_stress_all_with_rand_reset.35660589465675244294284018482082367751417876969491123597087094437712927142071","seed":35660589465675244294284018482082367751417876969491123597087094437712927142071,"line":139,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 878095786 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 878095786 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 878146291 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"37.pattgen_stress_all_with_rand_reset.42254919935839822514242128971997563184133726483804077949449980947881659705971","seed":42254919935839822514242128971997563184133726483804077949449980947881659705971,"line":225,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 10322581440 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 10322581440 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 10322893940 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"38.pattgen_stress_all_with_rand_reset.90159363536972361533058025409716290997799813214177623006448220589132483216531","seed":90159363536972361533058025409716290997799813214177623006448220589132483216531,"line":222,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 15777644828 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 15777644828 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 15778089272 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"39.pattgen_stress_all_with_rand_reset.43298937932386399884958055257689322224216266043993045915636839870753114407126","seed":43298937932386399884958055257689322224216266043993045915636839870753114407126,"line":115,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1100314458 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1100314458 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 1100606127 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"40.pattgen_stress_all_with_rand_reset.110128453249833101556310789523406300604285883547090682771654219024118967081501","seed":110128453249833101556310789523406300604285883547090682771654219024118967081501,"line":127,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/40.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 652381245 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 652381245 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 652504536 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"41.pattgen_stress_all_with_rand_reset.57342474429637156680739871522191281073972355470744412278944549601485189291038","seed":57342474429637156680739871522191281073972355470744412278944549601485189291038,"line":123,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/41.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 1665704587 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 1665704587 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/5\n","UVM_INFO @ 1665827035 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"42.pattgen_stress_all_with_rand_reset.103953567633769209617323114378121613186761613209506347702071432093721319460861","seed":103953567633769209617323114378121613186761613209506347702071432093721319460861,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 400342798 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 400342798 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 400427902 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"43.pattgen_stress_all_with_rand_reset.61931082521537079580218998471250330836445082079184176083145056752770653777848","seed":61931082521537079580218998471250330836445082079184176083145056752770653777848,"line":220,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 2319270786 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 2319270786 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 4/10\n","UVM_INFO @ 2319354118 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"44.pattgen_stress_all_with_rand_reset.20699915685056312796640624646530654096225231240070030188879787578623986671778","seed":20699915685056312796640624646530654096225231240070030188879787578623986671778,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/44.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 764170565 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 764170565 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 764250565 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"45.pattgen_stress_all_with_rand_reset.88986541862856392604319575409015693836480117622845408526911653690040881088048","seed":88986541862856392604319575409015693836480117622845408526911653690040881088048,"line":212,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4510588339 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4510588339 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 4510838341 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"46.pattgen_stress_all_with_rand_reset.93509903989679560883750040189282545038897711582965023117677179807880207955948","seed":93509903989679560883750040189282545038897711582965023117677179807880207955948,"line":116,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 603331050 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 603331050 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 1/10\n","UVM_INFO @ 603382595 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"47.pattgen_stress_all_with_rand_reset.112516783217651301199465672483672081012466367771576064769270286544758966874679","seed":112516783217651301199465672483672081012466367771576064769270286544758966874679,"line":148,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 4860327719 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 4860327719 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 2/10\n","UVM_INFO @ 4860549941 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"48.pattgen_stress_all_with_rand_reset.9885668029430294706012857903487418311272585421966683820620361681017978376148","seed":9885668029430294706012857903487418311272585421966683820620361681017978376148,"line":193,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 3830299489 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 3830299489 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/10\n","UVM_INFO @ 3830503569 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]},{"name":"pattgen_stress_all_with_rand_reset","qual_name":"49.pattgen_stress_all_with_rand_reset.85143728641321754431409311907221001755255518266935443975870703884774292115685","seed":85143728641321754431409311907221001755255518266935443975870703884774292115685,"line":193,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_ERROR @ 766085336 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. \n","UVM_INFO @ 766085336 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n","Issuing reset for run 3/5\n","UVM_INFO @ 766269008 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] \n"]}],"Job timed out after * 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@11361\n"]},{"name":"pattgen_stress_all","qual_name":"16.pattgen_stress_all.108565683873923541769006625013799049409557370381491196929617116819353191847080","seed":108565683873923541769006625013799049409557370381491196929617116819353191847080,"line":152,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/16.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11365\n"]},{"name":"pattgen_stress_all","qual_name":"18.pattgen_stress_all.99009050127150702140681459489803695297755649986147314544926876483513544350758","seed":99009050127150702140681459489803695297755649986147314544926876483513544350758,"line":130,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11338\n"]},{"name":"pattgen_stress_all","qual_name":"21.pattgen_stress_all.115052942165181897758777849353959887671324277621119386896191869254782147594125","seed":115052942165181897758777849353959887671324277621119386896191869254782147594125,"line":146,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/21.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11228\n"]},{"name":"pattgen_stress_all","qual_name":"22.pattgen_stress_all.85619209953390358108326955533916638974184448642192997382084585226309750692236","seed":85619209953390358108326955533916638974184448642192997382084585226309750692236,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/22.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11346\n"]},{"name":"pattgen_stress_all","qual_name":"23.pattgen_stress_all.68611455523502374633243627638959952040805096277391186272873188224663481360019","seed":68611455523502374633243627638959952040805096277391186272873188224663481360019,"line":137,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/23.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @13801\n"]},{"name":"pattgen_stress_all","qual_name":"27.pattgen_stress_all.110861797356895819884458182443465336185810746961618266397437273800271825681937","seed":110861797356895819884458182443465336185810746961618266397437273800271825681937,"line":137,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11344\n"]},{"name":"pattgen_stress_all","qual_name":"29.pattgen_stress_all.9613611996052735957464967571273993085187140793063840193329859635774164238206","seed":9613611996052735957464967571273993085187140793063840193329859635774164238206,"line":132,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/29.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11393\n"]},{"name":"pattgen_stress_all","qual_name":"31.pattgen_stress_all.107360642219078771344163686641068474264929516310413983450613388906764205764358","seed":107360642219078771344163686641068474264929516310413983450613388906764205764358,"line":156,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/31.pattgen_stress_all/latest/run.log","log_context":["--------------------------------------\n","Name        Type          Size  Value \n","--------------------------------------\n","exp_item    pattgen_item  -     @11330\n"]},{"name":"pattgen_stress_all","qual_name":"33.pattgen_stress_all.89528906654742628074799006969497283611450204571728166436531377273039498791493","seed":89528906654742628074799006969497283611450204571728166436531377273039498791493,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/33.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11318\n"]},{"name":"pattgen_stress_all","qual_name":"34.pattgen_stress_all.20701385587416416284447550270380109606389478743472522308660388748073122930747","seed":20701385587416416284447550270380109606389478743472522308660388748073122930747,"line":135,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11301\n"]},{"name":"pattgen_stress_all","qual_name":"36.pattgen_stress_all.113642203109368422857073630803181139233057390164735714272189082425212641231605","seed":113642203109368422857073630803181139233057390164735714272189082425212641231605,"line":157,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11250\n"]},{"name":"pattgen_stress_all","qual_name":"37.pattgen_stress_all.97326733885779274157038518982449507625204489656076189468334945233300364597199","seed":97326733885779274157038518982449507625204489656076189468334945233300364597199,"line":138,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/37.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11374\n"]},{"name":"pattgen_stress_all","qual_name":"39.pattgen_stress_all.31508883322020846969177351739863655414932043278599998518055037841320415966494","seed":31508883322020846969177351739863655414932043278599998518055037841320415966494,"line":158,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/39.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11371\n"]},{"name":"pattgen_stress_all","qual_name":"42.pattgen_stress_all.10973904522708312208461274605715151183794613007461967973124633930924291796935","seed":10973904522708312208461274605715151183794613007461967973124633930924291796935,"line":139,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/42.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11304\n"]},{"name":"pattgen_stress_all","qual_name":"43.pattgen_stress_all.69186789389166917803584332787874757523749446250084873128952965896115536594419","seed":69186789389166917803584332787874757523749446250084873128952965896115536594419,"line":142,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/43.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11256\n"]},{"name":"pattgen_stress_all","qual_name":"47.pattgen_stress_all.28272316119802842003585290634645347625551762997594305404529078254108298153124","seed":28272316119802842003585290634645347625551762997594305404529078254108298153124,"line":145,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/47.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11313\n"]},{"name":"pattgen_stress_all","qual_name":"48.pattgen_stress_all.27714646371069491095664142994871807031066518309206417957297527182351732008490","seed":27714646371069491095664142994871807031066518309206417957297527182351732008490,"line":125,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11330\n"]},{"name":"pattgen_stress_all","qual_name":"49.pattgen_stress_all.38577756178503217935766325175100787234047740218016942808420929605126829314716","seed":38577756178503217935766325175100787234047740218016942808420929605126829314716,"line":136,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_stress_all/latest/run.log","log_context":["------------------------------------\n","Name      Type          Size  Value \n","------------------------------------\n","exp_item  pattgen_item  -     @11336\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)":[{"name":"pattgen_inactive_level","qual_name":"3.pattgen_inactive_level.107856460396545831776271568164754428592671863189809626610634359388482014837177","seed":107856460396545831776271568164754428592671863189809626610634359388482014837177,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10006713316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"36.pattgen_inactive_level.10457015939023883772339991098950286739828803430071820853843347022484226287655","seed":10457015939023883772339991098950286739828803430071820853843347022484226287655,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10025046662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22)":[{"name":"pattgen_inactive_level","qual_name":"5.pattgen_inactive_level.55494784206449830617567917099272241328131828532725560293863292066250746661180","seed":55494784206449830617567917099272241328131828532725560293863292066250746661180,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10034514057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"45.pattgen_inactive_level.61931922210672533817324838139256288457944893830621379544749728343685356218472","seed":61931922210672533817324838139256288457944893830621379544749728343685356218472,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10097296601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)":[{"name":"pattgen_inactive_level","qual_name":"6.pattgen_inactive_level.2554214035152763742507431239551649579682419375296763183800622135120422941107","seed":2554214035152763742507431239551649579682419375296763183800622135120422941107,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10042857442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)":[{"name":"pattgen_inactive_level","qual_name":"8.pattgen_inactive_level.64820610012703628763858910998594025296407387480208435856002849293121321455423","seed":64820610012703628763858910998594025296407387480208435856002849293121321455423,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10078094909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"12.pattgen_inactive_level.32519799926210258584719339182652120080300837660361240252425633665270499424835","seed":32519799926210258584719339182652120080300837660361240252425633665270499424835,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10004789180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)":[{"name":"pattgen_inactive_level","qual_name":"13.pattgen_inactive_level.66456598290830782919624721258165026907970164909529057083263703405803398077816","seed":66456598290830782919624721258165026907970164909529057083263703405803398077816,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10015414079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"27.pattgen_inactive_level.85414713190295624714502466229614946510090080209270957885558092694102321990081","seed":85414713190295624714502466229614946510090080209270957885558092694102321990081,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10045214568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19)":[{"name":"pattgen_inactive_level","qual_name":"18.pattgen_inactive_level.111452288551774690251568180323459755489732089927922542861086309995788706190030","seed":111452288551774690251568180323459755489732089927922542861086309995788706190030,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10143888247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"48.pattgen_inactive_level.70667603732983592489902547711294943632142422530555728874720601732006473112210","seed":70667603732983592489902547711294943632142422530555728874720601732006473112210,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10147974725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)":[{"name":"pattgen_inactive_level","qual_name":"19.pattgen_inactive_level.31954569629629427489482085497221595435526018840448321689144690543809877511982","seed":31954569629629427489482085497221595435526018840448321689144690543809877511982,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10022094384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"pattgen_inactive_level","qual_name":"34.pattgen_inactive_level.52661400772015275574163313822390921195030234839772571168289123765024816995729","seed":52661400772015275574163313822390921195030234839772571168289123765024816995729,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10020144856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)":[{"name":"pattgen_inactive_level","qual_name":"49.pattgen_inactive_level.78324656139627727031444962023035213032099711483700208969725204632996495508096","seed":78324656139627727031444962023035213032099711483700208969725204632996495508096,"line":99,"log_path":"/nightly/current_run/scratch/reseed_opt/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log","log_context":["UVM_INFO @ 10022184582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":321,"total":443,"percent":72.46049661399549}