{"block":{"name":"spi_device","variant":"1r1w","commit":"9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a","commit_short":"9b0af25","branch":"reseed_opt","url":"https://github.com/martin-velay/opentitan/tree/9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a","revision_info":"GitHub Revision: [`9b0af25`](https://github.com/lowrisc/opentitan/tree/9b0af252fdb3bc34a669aa3f01e2f63b2d1ba71a)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-05-15T15:00:24Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/spi_device_1r1w/data/spi_device_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"spi_device_flash_and_tpm":{"max_time":231.97,"sim_time":35050.832476,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"csr_hw_reset":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.25,"sim_time":31.125966000000002,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"spi_device_csr_rw":{"max_time":3.15,"sim_time":94.893046,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"csr_bit_bash":{"tests":{"spi_device_csr_bit_bash":{"max_time":32.28,"sim_time":5780.345609,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_aliasing":{"tests":{"spi_device_csr_aliasing":{"max_time":8.97,"sim_time":386.9037,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"spi_device_csr_mem_rw_with_rand_reset":{"max_time":4.04,"sim_time":128.21133500000002,"passed":5,"total":5,"percent":100.0}},"passed":5,"total":5,"percent":100.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"spi_device_csr_rw":{"max_time":3.15,"sim_time":94.893046,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.97,"sim_time":386.9037,"passed":1,"total":1,"percent":100.0}},"passed":6,"total":6,"percent":100.0},"mem_walk":{"tests":{"spi_device_mem_walk":{"max_time":0.97,"sim_time":13.214881,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"mem_partial_access":{"tests":{"spi_device_mem_partial_access":{"max_time":1.94,"sim_time":147.939206,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"V2":{"testpoints":{"csb_read":{"tests":{"spi_device_csb_read":{"max_time":1.19,"sim_time":18.284035,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mem_parity":{"tests":{"spi_device_mem_parity":{"max_time":1.12,"sim_time":4.695951,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"mem_cfg":{"tests":{"spi_device_ram_cfg":{"max_time":1.08,"sim_time":3.858045,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"tpm_read":{"tests":{"spi_device_tpm_rw":{"max_time":3.63,"sim_time":281.03395400000005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tpm_write":{"tests":{"spi_device_tpm_rw":{"max_time":3.63,"sim_time":281.03395400000005,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tpm_hw_reg":{"tests":{"spi_device_tpm_read_hw_reg":{"max_time":17.95,"sim_time":11748.785039999999,"passed":10,"total":10,"percent":100.0},"spi_device_tpm_sts_read":{"max_time":1.35,"sim_time":202.46388399999998,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"tpm_fully_random_case":{"tests":{"spi_device_tpm_all":{"max_time":32.21,"sim_time":8567.209895,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"pass_cmd_filtering":{"tests":{"spi_device_pass_cmd_filtering":{"max_time":13.55,"sim_time":5351.753396,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"pass_addr_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":32.54,"sim_time":8204.59916,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"pass_payload_translation":{"tests":{"spi_device_pass_addr_payload_swap":{"max_time":32.54,"sim_time":8204.59916,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_info_slots":{"tests":{"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"cmd_read_status":{"tests":{"spi_device_intercept":{"max_time":13.06,"sim_time":876.501414,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_read_jedec":{"tests":{"spi_device_intercept":{"max_time":13.06,"sim_time":876.501414,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_read_sfdp":{"tests":{"spi_device_intercept":{"max_time":13.06,"sim_time":876.501414,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_fast_read":{"tests":{"spi_device_intercept":{"max_time":13.06,"sim_time":876.501414,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_read_pipeline":{"tests":{"spi_device_intercept":{"max_time":13.06,"sim_time":876.501414,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"flash_cmd_upload":{"tests":{"spi_device_upload":{"max_time":12.8,"sim_time":1921.741007,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_command":{"tests":{"spi_device_mailbox":{"max_time":22.84,"sim_time":5122.625190000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_cross_outside_command":{"tests":{"spi_device_mailbox":{"max_time":22.84,"sim_time":5122.625190000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"mailbox_cross_inside_command":{"tests":{"spi_device_mailbox":{"max_time":22.84,"sim_time":5122.625190000001,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"cmd_read_buffer":{"tests":{"spi_device_flash_mode":{"max_time":30.12,"sim_time":19148.64702,"passed":10,"total":10,"percent":100.0},"spi_device_read_buffer_direct":{"max_time":10.48,"sim_time":921.0746350000001,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"cmd_dummy_cycle":{"tests":{"spi_device_mailbox":{"max_time":22.84,"sim_time":5122.625190000001,"passed":10,"total":10,"percent":100.0},"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":20,"total":20,"percent":100.0},"quad_spi":{"tests":{"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"dual_spi":{"tests":{"spi_device_flash_all":{"max_time":224.69,"sim_time":40804.337746,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"4b_3b_feature":{"tests":{"spi_device_cfg_cmd":{"max_time":8.67,"sim_time":836.137877,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"write_enable_disable":{"tests":{"spi_device_cfg_cmd":{"max_time":8.67,"sim_time":836.137877,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"TPM_with_flash_or_passthrough_mode":{"tests":{"spi_device_flash_and_tpm":{"max_time":231.97,"sim_time":35050.832476,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tpm_and_flash_trans_with_min_inactive_time":{"tests":{"spi_device_flash_and_tpm_min_idle":{"max_time":619.24,"sim_time":329828.65606,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"stress_all":{"tests":{"spi_device_stress_all":{"max_time":320.02,"sim_time":56495.166344,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"alert_test":{"tests":{"spi_device_alert_test":{"max_time":1.12,"sim_time":21.280011,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"intr_test":{"tests":{"spi_device_intr_test":{"max_time":1.16,"sim_time":51.070837,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"spi_device_tl_errors":{"max_time":5.37,"sim_time":315.36146,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_illegal_access":{"tests":{"spi_device_tl_errors":{"max_time":5.37,"sim_time":315.36146,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0},"tl_d_outstanding_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.25,"sim_time":31.125966000000002,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":3.15,"sim_time":94.893046,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.97,"sim_time":386.9037,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.76,"sim_time":229.26256899999998,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0},"tl_d_partial_access":{"tests":{"spi_device_csr_hw_reset":{"max_time":1.25,"sim_time":31.125966000000002,"passed":1,"total":1,"percent":100.0},"spi_device_csr_rw":{"max_time":3.15,"sim_time":94.893046,"passed":5,"total":5,"percent":100.0},"spi_device_csr_aliasing":{"max_time":8.97,"sim_time":386.9037,"passed":1,"total":1,"percent":100.0},"spi_device_same_csr_outstanding":{"max_time":4.76,"sim_time":229.26256899999998,"passed":5,"total":5,"percent":100.0}},"passed":12,"total":12,"percent":100.0}},"passed":242,"total":263,"percent":92.01520912547528},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"spi_device_sec_cm":{"max_time":1.64,"sim_time":773.469859,"passed":5,"total":5,"percent":100.0},"spi_device_tl_intg_err":{"max_time":24.93,"sim_time":1633.625764,"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"sec_cm_bus_integrity":{"tests":{"spi_device_tl_intg_err":{"max_time":24.93,"sim_time":1633.625764,"passed":25,"total":25,"percent":100.0}},"passed":25,"total":25,"percent":100.0}},"passed":30,"total":30,"percent":100.0},"unmapped":{"testpoints":{"Unmapped":{"tests":{"spi_device_flash_mode_ignore_cmds":{"max_time":242.76000000000002,"sim_time":138388.463419,"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"passed":10,"total":10,"percent":100.0}},"coverage":{"code":{"block":null,"line_statement":98.9,"branch":98.28,"condition_expression":96.49,"toggle":83.54,"fsm":89.36},"assertion":94.64,"functional":96.53},"cov_report_page":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])":[{"name":"spi_device_mem_parity","qual_name":"0.spi_device_mem_parity.40642296095526300407602764538205194690811993220738838155729753631791162082251","seed":40642296095526300407602764538205194690811993220738838155729753631791162082251,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2694960 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2694960 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"1.spi_device_mem_parity.77316814467018091241623987764308515696098420621241567867609500636348580163849","seed":77316814467018091241623987764308515696098420621241567867609500636348580163849,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3431891 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3431891 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[954])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"2.spi_device_mem_parity.39994929089984427097543873022212567432845383488828860062355667332139068433981","seed":39994929089984427097543873022212567432845383488828860062355667332139068433981,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/2.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4179281 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4179281 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[989])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"3.spi_device_mem_parity.5954286303583267794143274235735607953052157228048297464744874587076800814655","seed":5954286303583267794143274235735607953052157228048297464744874587076800814655,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/3.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4102570 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4102570 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[967])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"4.spi_device_mem_parity.91122606943308076975362685761538333148456625359103008610479357820131413689467","seed":91122606943308076975362685761538333148456625359103008610479357820131413689467,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/4.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    940884 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    940884 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"5.spi_device_mem_parity.46761072794004454526207883776058071098575206369919500048907978695954653738593","seed":46761072794004454526207883776058071098575206369919500048907978695954653738593,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/5.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @    848965 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @    848965 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[919])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"6.spi_device_mem_parity.105787905002308775533804346266128029391470455322263486005364348146703627161157","seed":105787905002308775533804346266128029391470455322263486005364348146703627161157,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/6.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4679951 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4679951 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[950])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"7.spi_device_mem_parity.61396341704133097215465742980626156167642988481398801168033988985682052178020","seed":61396341704133097215465742980626156167642988481398801168033988985682052178020,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/7.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5099796 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5099796 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[972])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"8.spi_device_mem_parity.105217382142072632808108870129516006500250742401085856206707566231191603405251","seed":105217382142072632808108870129516006500250742401085856206707566231191603405251,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/8.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1215902 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1215902 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"9.spi_device_mem_parity.93216174952890979432995453247951697100619524904191412303669965775069057291470","seed":93216174952890979432995453247951697100619524904191412303669965775069057291470,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/9.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5031744 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5031744 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[997])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"10.spi_device_mem_parity.107735365335471097116466952115018409656934637313266607142586722879953733370677","seed":107735365335471097116466952115018409656934637313266607142586722879953733370677,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/10.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   5071625 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   5071625 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"11.spi_device_mem_parity.85008170612927383005226081683499814479971825351714902798316264388329565849796","seed":85008170612927383005226081683499814479971825351714902798316264388329565849796,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/11.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3945945 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3945945 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[903])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"12.spi_device_mem_parity.99795889884897745529148034945151800967203140014510320546455805054825965289521","seed":99795889884897745529148034945151800967203140014510320546455805054825965289521,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/12.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3578821 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3578821 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"13.spi_device_mem_parity.36730055052329931700928773762260617704783766873375151834156701815546058103684","seed":36730055052329931700928773762260617704783766873375151834156701815546058103684,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/13.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4950378 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4950378 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[951])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"14.spi_device_mem_parity.33392984833038034142158936861908196605566348737001756359431209952682320673381","seed":33392984833038034142158936861908196605566348737001756359431209952682320673381,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/14.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   4952171 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   4952171 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[905])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"15.spi_device_mem_parity.72938968525764453290419703914799097324231708766189739437911555017672840627307","seed":72938968525764453290419703914799097324231708766189739437911555017672840627307,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/15.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   2096277 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   2096277 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"16.spi_device_mem_parity.89837753425429221073135976717174652049186536747456536496239702085945809702266","seed":89837753425429221073135976717174652049186536747456536496239702085945809702266,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/16.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1201547 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1201547 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"17.spi_device_mem_parity.114240560449816139317510280686892548196611765790006554808791579385162719394917","seed":114240560449816139317510280686892548196611765790006554808791579385162719394917,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/17.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   3600937 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   3600937 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[992])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"18.spi_device_mem_parity.85148446010138246454696277222354341388868535758530793730502244017321609379659","seed":85148446010138246454696277222354341388868535758530793730502244017321609379659,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/18.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   1839793 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   1839793 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[919])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]},{"name":"spi_device_mem_parity","qual_name":"19.spi_device_mem_parity.41205976807050972676148109937610336115721527562670728245501026769102855840163","seed":41205976807050972676148109937610336115721527562670728245501026769102855840163,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/19.spi_device_mem_parity/latest/run.log","log_context":[" Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n","UVM_ERROR @   7200499 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))  \n","UVM_ERROR @   7200499 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[897])\n"," Either the name is incorrect, or you may not have PLI/ACC visibility to that name\n"]}],"UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])":[{"name":"spi_device_ram_cfg","qual_name":"0.spi_device_ram_cfg.74616070169915480949243936175884453484953013249131549021135238927583284290137","seed":74616070169915480949243936175884453484953013249131549021135238927583284290137,"line":76,"log_path":"/nightly/current_run/scratch/reseed_opt/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log","log_context":["UVM_ERROR @   1139045 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3fb8d9 [1111111011100011011001] vs 0x0 [0]) \n","UVM_ERROR @   1174045 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e0a7b [1111100000101001111011] vs 0x0 [0]) \n","UVM_ERROR @   1229045 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12b607 [100101011011000000111] vs 0x0 [0]) \n","UVM_ERROR @   1272045 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x64bc0c [11001001011110000001100] vs 0x0 [0]) \n"]}]}},"passed":290,"total":311,"percent":93.2475884244373}